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3d3befa7 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> | |
8 | * | |
9 | * (C) Copyright 2003 | |
10 | * Texas Instruments, <www.ti.com> | |
11 | * Kshitij Gupta <Kshitij@ti.com> | |
12 | * | |
13 | * (C) Copyright 2004 | |
14 | * ARM Ltd. | |
15 | * Philippe Robin, <philippe.robin@arm.com> | |
16 | * | |
17 | * See file CREDITS for list of people who contributed to this | |
18 | * project. | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or | |
21 | * modify it under the terms of the GNU General Public License as | |
22 | * published by the Free Software Foundation; either version 2 of | |
23 | * the License, or (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
fe7eb5d8 | 27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
3d3befa7 WD |
28 | * GNU General Public License for more details. |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; if not, write to the Free Software | |
32 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
33 | * MA 02111-1307 USA | |
34 | */ | |
35 | ||
36 | #include <common.h> | |
10efa024 | 37 | #include <netdev.h> |
7c045d0b | 38 | #include <asm/io.h> |
701ed16e | 39 | #include "arm-ebi.h" |
10efa024 | 40 | |
d87080b7 WD |
41 | DECLARE_GLOBAL_DATA_PTR; |
42 | ||
3d3befa7 WD |
43 | void peripheral_power_enable (void); |
44 | ||
45 | #if defined(CONFIG_SHOW_BOOT_PROGRESS) | |
46 | void show_boot_progress(int progress) | |
47 | { | |
716c1dcb | 48 | printf("Boot reached stage %d\n", progress); |
3d3befa7 WD |
49 | } |
50 | #endif | |
51 | ||
52 | #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) | |
53 | ||
3d3befa7 WD |
54 | /* |
55 | * Miscellaneous platform dependent initialisations | |
56 | */ | |
57 | ||
58 | int board_init (void) | |
59 | { | |
701ed16e LW |
60 | u32 val; |
61 | ||
3d3befa7 | 62 | /* arch number of Integrator Board */ |
576afd4f JCPV |
63 | #ifdef CONFIG_ARCH_CINTEGRATOR |
64 | gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR; | |
65 | #else | |
731215eb | 66 | gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR; |
576afd4f | 67 | #endif |
3d3befa7 WD |
68 | |
69 | /* adress of boot parameters */ | |
70 | gd->bd->bi_boot_params = 0x00000100; | |
71 | ||
bc54f309 WD |
72 | gd->flags = 0; |
73 | ||
0148e8cb WD |
74 | #ifdef CONFIG_CM_REMAP |
75 | extern void cm_remap(void); | |
76 | cm_remap(); /* remaps writeable memory to 0x00000000 */ | |
77 | #endif | |
716c1dcb | 78 | |
701ed16e LW |
79 | /* |
80 | * The system comes up with the flash memory non-writable and | |
81 | * configuration locked. If we want U-Boot to be used for flash | |
82 | * access we cannot have the flash memory locked. | |
83 | */ | |
84 | writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG); | |
85 | val = readl(EBI_BASE + EBI_CSR1_REG); | |
86 | val &= EBI_CSR_WREN_MASK; | |
87 | val |= EBI_CSR_WREN_ENABLE; | |
88 | writel(val, EBI_BASE + EBI_CSR1_REG); | |
89 | writel(0, EBI_BASE + EBI_LOCK_REG); | |
90 | ||
3d3befa7 WD |
91 | icache_enable (); |
92 | ||
3d3befa7 WD |
93 | return 0; |
94 | } | |
95 | ||
3d3befa7 WD |
96 | int misc_init_r (void) |
97 | { | |
98 | #ifdef CONFIG_PCI | |
99 | pci_init(); | |
100 | #endif | |
101 | setenv("verify", "n"); | |
102 | return (0); | |
103 | } | |
104 | ||
46b5ccbf LW |
105 | /* |
106 | * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot | |
107 | * from there, which means we cannot test the RAM underneath the ROM at this | |
108 | * point. It will be unmapped later on, when we are executing from the | |
109 | * relocated in RAM U-Boot. We simply assume that this RAM is usable if the | |
110 | * RAM on higher addresses works fine. | |
111 | */ | |
112 | #define REMAPPED_FLASH_SZ 0x40000 | |
113 | ||
3d3befa7 WD |
114 | int dram_init (void) |
115 | { | |
26c82638 | 116 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
0148e8cb WD |
117 | #ifdef CONFIG_CM_SPD_DETECT |
118 | { | |
119 | extern void dram_query(void); | |
7c045d0b LW |
120 | u32 cm_reg_sdram; |
121 | u32 sdram_shift; | |
0148e8cb WD |
122 | |
123 | dram_query(); /* Assembler accesses to CM registers */ | |
716c1dcb | 124 | /* Queries the SPD values */ |
0148e8cb WD |
125 | |
126 | /* Obtain the SDRAM size from the CM SDRAM register */ | |
127 | ||
7c045d0b | 128 | cm_reg_sdram = readl(CM_BASE + OS_SDRAM); |
716c1dcb WD |
129 | /* Register SDRAM size |
130 | * | |
131 | * 0xXXXXXXbbb000bb 16 MB | |
132 | * 0xXXXXXXbbb001bb 32 MB | |
133 | * 0xXXXXXXbbb010bb 64 MB | |
134 | * 0xXXXXXXbbb011bb 128 MB | |
135 | * 0xXXXXXXbbb100bb 256 MB | |
0148e8cb | 136 | * |
0148e8cb | 137 | */ |
7c045d0b | 138 | sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; |
46b5ccbf LW |
139 | gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + |
140 | REMAPPED_FLASH_SZ, | |
26c82638 | 141 | 0x01000000 << sdram_shift); |
0148e8cb | 142 | } |
26c82638 | 143 | #else |
46b5ccbf LW |
144 | gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + |
145 | REMAPPED_FLASH_SZ, | |
26c82638 | 146 | PHYS_SDRAM_1_SIZE); |
0148e8cb | 147 | #endif /* CM_SPD_DETECT */ |
46b5ccbf LW |
148 | /* We only have one bank of RAM, set it to whatever was detected */ |
149 | gd->bd->bi_dram[0].size = gd->ram_size; | |
0148e8cb | 150 | |
3d3befa7 WD |
151 | return 0; |
152 | } | |
74f4304e | 153 | |
7194ab80 | 154 | #ifdef CONFIG_CMD_NET |
10efa024 BW |
155 | int board_eth_init(bd_t *bis) |
156 | { | |
7194ab80 BW |
157 | int rc = 0; |
158 | #ifdef CONFIG_SMC91111 | |
159 | rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); | |
160 | #endif | |
7194ab80 | 161 | rc += pci_eth_init(bis); |
7194ab80 | 162 | return rc; |
10efa024 | 163 | } |
576afd4f | 164 | #endif |