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3d3befa7 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> | |
8 | * | |
9 | * (C) Copyright 2003 | |
10 | * Texas Instruments, <www.ti.com> | |
11 | * Kshitij Gupta <Kshitij@ti.com> | |
12 | * | |
13 | * (C) Copyright 2004 | |
14 | * ARM Ltd. | |
15 | * Philippe Robin, <philippe.robin@arm.com> | |
16 | * | |
1a459660 | 17 | * SPDX-License-Identifier: GPL-2.0+ |
3d3befa7 WD |
18 | */ |
19 | ||
20 | #include <common.h> | |
7194ab80 | 21 | #include <netdev.h> |
3d3befa7 | 22 | |
d87080b7 WD |
23 | DECLARE_GLOBAL_DATA_PTR; |
24 | ||
3d3befa7 WD |
25 | #if defined(CONFIG_SHOW_BOOT_PROGRESS) |
26 | void show_boot_progress(int progress) | |
27 | { | |
28 | printf("Boot reached stage %d\n", progress); | |
29 | } | |
30 | #endif | |
31 | ||
32 | #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) | |
33 | ||
3d3befa7 WD |
34 | /* |
35 | * Miscellaneous platform dependent initialisations | |
36 | */ | |
37 | ||
d388298a | 38 | int board_early_init_f (void) |
3d3befa7 | 39 | { |
3d3befa7 WD |
40 | /* |
41 | * set clock frequency: | |
42 | * VERSATILE_REFCLK is 32KHz | |
43 | * VERSATILE_TIMCLK is 1MHz | |
44 | */ | |
45 | *(volatile unsigned int *)(VERSATILE_SCTL_BASE) |= | |
46 | ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | | |
47 | (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel)); | |
48 | ||
d388298a SB |
49 | return 0; |
50 | } | |
51 | ||
52 | int board_init (void) | |
53 | { | |
3d3befa7 | 54 | /* arch number of Versatile Board */ |
731215eb | 55 | gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB; |
3d3befa7 WD |
56 | |
57 | /* adress of boot parameters */ | |
58 | gd->bd->bi_boot_params = 0x00000100; | |
59 | ||
bc54f309 WD |
60 | gd->flags = 0; |
61 | ||
3d3befa7 WD |
62 | icache_enable (); |
63 | ||
3d3befa7 WD |
64 | return 0; |
65 | } | |
66 | ||
67 | ||
68 | int misc_init_r (void) | |
69 | { | |
70 | setenv("verify", "n"); | |
71 | return (0); | |
72 | } | |
73 | ||
3d3befa7 WD |
74 | /****************************** |
75 | Routine: | |
76 | Description: | |
77 | ******************************/ | |
78 | int dram_init (void) | |
79 | { | |
d388298a | 80 | /* dram_init must store complete ramsize in gd->ram_size */ |
689d0fa3 | 81 | gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |
d388298a | 82 | PHYS_SDRAM_1_SIZE); |
3d3befa7 WD |
83 | return 0; |
84 | } | |
7194ab80 BW |
85 | |
86 | #ifdef CONFIG_CMD_NET | |
87 | int board_eth_init(bd_t *bis) | |
88 | { | |
89 | int rc = 0; | |
90 | #ifdef CONFIG_SMC91111 | |
91 | rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); | |
92 | #endif | |
93 | return rc; | |
94 | } | |
95 | #endif |