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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / board / atc / atc.c
CommitLineData
7aa78614
WD		 1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ioports.h>
26#include <mpc8260.h>
66fd3d1c 27#include <pci.h>
7aa78614
WD		 28
29/*
30 * I/O Port configuration table
31 *
32 * if conf is 1, then that port pin will be configured at boot time
33 * according to the five values podr/pdir/ppar/psor/pdat for that entry
34 */
35
36const iop_conf_t iop_conf_tab[4][32] = {
37
38 /* Port A configuration */
39 { /* conf ppar psor pdir podr pdat */
40 /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
41 /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
42 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
43 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
44 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
45 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
46 /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */
47 /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */
48 /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */
49 /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */
50 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
51 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
52 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
53 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
54 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
55 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
56 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
57 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
58 /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */
59 /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */
60 /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */
61 /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */
62#if 1
63 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
64 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
65#else
66 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
67 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
68#endif
69 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
70 /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */
71 /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */
72 /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */
73 /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */
74 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
75 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */
76 /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */
77 },
78
79 /* Port B configuration */
80 { /* conf ppar psor pdir podr pdat */
81 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
82 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
83 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
84 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
85 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
86 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
87 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
88 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
89 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
90 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
91 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
92 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
93 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
94 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
a57a496f
WD		 95 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
96 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
97 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
98 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
99 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
100 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
101 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
102 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
103 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
104 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD */
105 /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
106 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
107 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
108 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD */
7aa78614
WD		 109 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */
110 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */
111 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */
112 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */
113 },
114
115 /* Port C */
116 { /* conf ppar psor pdir podr pdat */
117 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
118 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
119 /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */
120 /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */
121 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
122 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
123 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
124 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
125 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */
126 /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */
127 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
128 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
129 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
130 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
a57a496f
WD		 131 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */
132 /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
7aa78614
WD		 133#if 0
134 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
135#else
136 /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* PC15 */
137#endif
138 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
139 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
140 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
141 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
142 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
143 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */
144 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
145 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
146 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
147 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
148 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
149 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
150 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
151 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
152 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */
153 },
154
155 /* Port D */
156 { /* conf ppar psor pdir podr pdat */
157 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
158 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
159 /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */
160 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
161 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
162 /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */
163 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
164 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
165 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
166 /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
167 /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
168 /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
169 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
170 /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
171 /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
172 /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
173#if defined(CONFIG_SOFT_I2C)
174 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
175 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
176#else
177#if defined(CONFIG_HARD_I2C)
178 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
179 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
180#else /* normal I/O port pins */
181 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
182 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
183#endif
184#endif
185 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
186 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
187 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
188 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
189 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
190 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
191 /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
192 /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
193 /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
194#if 0
195 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
196#else
197 /* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* PD4 */
198#endif
199 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */
200 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */
201 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */
202 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */
203 }
204};
205
15ef8a5d
WD		 206/*
207 * UPMB initialization table
208 */
209#define _NOT_USED_ 0xFFFFFFFF
8bde7f77 210
15ef8a5d
WD		 211static const uint rtc_table[] =
212{
213 /*
214 * Single Read. (Offset 0 in UPMA RAM)
215 */
8bde7f77
WD		 216 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800,
217 0xfaf2080, 0xfaf2080, 0xfff2400, 0x1fff6c05, /* last */
15ef8a5d
WD		 218 /*
219 * Burst Read. (Offset 8 in UPMA RAM)
220 */
221 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
222 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
223 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
224 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
225 /*
226 * Single Write. (Offset 18 in UPMA RAM)
227 */
8bde7f77 228 0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800,
15ef8a5d
WD		 229 0xfaf2080, 0xfaf2080, 0xfaf2400, 0x1fbf6c05, /* last */
230 /*
231 * Burst Write. (Offset 20 in UPMA RAM)
232 */
233 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
234 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
235 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
236 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
237 /*
238 * Refresh (Offset 30 in UPMA RAM)
239 */
240 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
241 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
242 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
243 /*
244 * Exception. (Offset 3c in UPMA RAM)
245 */
246 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
8bde7f77
WD		 247};
248
7aa78614
WD		 249/* ------------------------------------------------------------------------- */
250
251/* Check Board Identity:
252 */
253int checkboard (void)
254{
255 printf ("Board: ATC\n");
256 return 0;
257}
258
259/* ------------------------------------------------------------------------- */
260
261/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
262 *
263 * This routine performs standard 8260 initialization sequence
264 * and calculates the available memory size. It may be called
265 * several times to try different SDRAM configurations on both
266 * 60x and local buses.
267 */
268static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
269 ulong orx, volatile uchar * base)
270{
271 volatile uchar c = 0xff;
7aa78614
WD		 272 volatile uint *sdmr_ptr;
273 volatile uint *orx_ptr;
c83bf6a2 274 ulong maxsize, size;
7aa78614 275 int i;
7aa78614
WD		 276
277 /* We must be able to test a location outsize the maximum legal size
278 * to find out THAT we are outside; but this address still has to be
279 * mapped by the controller. That means, that the initial mapping has
280 * to be (at least) twice as large as the maximum expected size.
281 */
282 maxsize = (1 + (~orx | 0x7fff)) / 2;
283
6d0f6bcf 284 /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
7aa78614
WD		 285 * we are configuring CS1 if base != 0
286 */
287 sdmr_ptr = &memctl->memc_psdmr;
288 orx_ptr = &memctl->memc_or2;
289
290 *orx_ptr = orx;
291
292 /*
293 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
294 *
295 * "At system reset, initialization software must set up the
296 * programmable parameters in the memory controller banks registers
297 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
298 * system software should execute the following initialization sequence
299 * for each SDRAM device.
300 *
301 * 1. Issue a PRECHARGE-ALL-BANKS command
302 * 2. Issue eight CBR REFRESH commands
303 * 3. Issue a MODE-SET command to initialize the mode register
304 *
305 * The initial commands are executed by setting P/LSDMR[OP] and
306 * accessing the SDRAM with a single-byte transaction."
307 *
308 * The appropriate BRx/ORx registers have already been set when we
6d0f6bcf 309 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
7aa78614
WD		 310 */
311
312 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
313 *base = c;
314
315 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
316 for (i = 0; i < 8; i++)
317 *base = c;
318
319 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
6d0f6bcf 320 *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
7aa78614
WD		 321
322 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
323 *base = c;
324
c83bf6a2 325 size = get_ram_size((long *)base, maxsize);
7aa78614 326
c83bf6a2 327 *orx_ptr = orx | ~(size - 1);
7aa78614 328
c83bf6a2 329 return (size);
7aa78614
WD		 330}
331
15ef8a5d
WD		 332int misc_init_r(void)
333{
6d0f6bcf 334 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
15ef8a5d 335 volatile memctl8260_t *memctl = &immap->im_memctl;
8bde7f77 336
15ef8a5d 337 upmconfig(UPMA, (uint *)rtc_table, sizeof(rtc_table) / sizeof(uint));
8bde7f77 338 memctl->memc_mamr = MxMR_RLFx_6X | MxMR_WLFx_6X | MxMR_OP_NORM;
15ef8a5d
WD		 339
340 return (0);
341}
8bde7f77 342
9973e3c6 343phys_size_t initdram (int board_type)
7aa78614 344{
6d0f6bcf 345 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
7aa78614
WD		 346 volatile memctl8260_t *memctl = &immap->im_memctl;
347
6d0f6bcf 348#ifndef CONFIG_SYS_RAMBOOT
7aa78614
WD		 349 ulong size8, size9;
350#endif
351 long psize;
352
353 psize = 8 * 1024 * 1024;
354
6d0f6bcf
JCPV		 355 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
356 memctl->memc_psrt = CONFIG_SYS_PSRT;
7aa78614 357
6d0f6bcf 358#ifndef CONFIG_SYS_RAMBOOT
7aa78614
WD		 359 /* 60x SDRAM setup:
360 */
6d0f6bcf
JCPV		 361 size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
362 (uchar *) CONFIG_SYS_SDRAM_BASE);
363 size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
364 (uchar *) CONFIG_SYS_SDRAM_BASE);
7aa78614
WD		 365
366 if (size8 < size9) {
367 psize = size9;
368 printf ("(60x:9COL) ");
369 } else {
6d0f6bcf
JCPV		 370 psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
371 (uchar *) CONFIG_SYS_SDRAM_BASE);
7aa78614
WD		 372 printf ("(60x:8COL) ");
373 }
374
6d0f6bcf 375#endif /* CONFIG_SYS_RAMBOOT */
7aa78614
WD		 376
377 icache_enable ();
378
379 return (psize);
380}
381
fcec2eb9 382#if defined(CONFIG_CMD_DOC)
7aa78614
WD		 383void doc_init (void)
384{
6d0f6bcf 385 doc_probe (CONFIG_SYS_DOC_BASE);
7aa78614
WD		 386}
387#endif
66fd3d1c
WD		 388
389#ifdef CONFIG_PCI
390struct pci_controller hose;
391
392extern void pci_mpc8250_init(struct pci_controller *);
393
394void pci_init_board(void)
395{
396 pci_mpc8250_init(&hose);
397}
398#endif
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