[people/ms/u-boot.git] / board / atmel / at91sam9263ek / at91sam9263ek.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian.pop@leadtechdesign.com>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/sizes.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91sam9263_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_CMD_NAND
static void at91sam9263ek_nand_hw_init(void)
{
	unsigned long csa;

	/* Enable CS3 */
	csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
	at91_sys_write(AT91_MATRIX_EBI0CSA,
		       csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);

	/* Configure SMC CS3 for NAND/SmartMedia */
	at91_sys_write(AT91_SMC_SETUP(3),
		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(3),
		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
	at91_sys_write(AT91_SMC_CYCLE(3),
		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
	at91_sys_write(AT91_SMC_MODE(3),
		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		       AT91_SMC_EXNWMODE_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
		       AT91_SMC_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
		       AT91_SMC_DBW_8 |
#endif
		       AT91_SMC_TDF_(2));

	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
				      1 << AT91SAM9263_ID_PIOCDE);

	/* Configure RDY/BSY */
	at91_set_gpio_input(AT91_PIN_PA22, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(AT91_PIN_PD15, 1);
}
#endif

#ifdef CONFIG_MACB
static void at91sam9263ek_macb_hw_init(void)
{
	/* Enable clock */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);

	/*
	 * Disable pull-up on:
	 *	RXDV (PC25) => PHY normal mode (not Test mode)
	 * 	ERX0 (PE25) => PHY ADDR0
	 *	ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
	 *
	 * PHY has internal pull-down
	 */
	writel(pin_to_mask(AT91_PIN_PC25),
	       pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
	writel(pin_to_mask(AT91_PIN_PE25) |
	       pin_to_mask(AT91_PIN_PE26),
	       pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);

	/* Need to reset PHY -> 500ms reset */
	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
				     AT91_RSTC_URSTEN);

	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);

	/* Wait for end hardware reset */
	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));

	/* Restore NRST value */
	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
				     (AT91_RSTC_ERSTL & (0x0 << 8)) |
				     AT91_RSTC_URSTEN);

	/* Re-enable pull-up */
	writel(pin_to_mask(AT91_PIN_PC25),
	       pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
	writel(pin_to_mask(AT91_PIN_PE25) |
	       pin_to_mask(AT91_PIN_PE26),
	       pin_to_controller(AT91_PIN_PE0) + PIO_PUER);

	at91_set_A_periph(AT91_PIN_PE21, 0);	/* ETXCK_EREFCK */
	at91_set_B_periph(AT91_PIN_PC25, 0);	/* ERXDV */
	at91_set_A_periph(AT91_PIN_PE25, 0);	/* ERX0 */
	at91_set_A_periph(AT91_PIN_PE26, 0);	/* ERX1 */
	at91_set_A_periph(AT91_PIN_PE27, 0);	/* ERXER */
	at91_set_A_periph(AT91_PIN_PE28, 0);	/* ETXEN */
	at91_set_A_periph(AT91_PIN_PE23, 0);	/* ETX0 */
	at91_set_A_periph(AT91_PIN_PE24, 0);	/* ETX1 */
	at91_set_A_periph(AT91_PIN_PE30, 0);	/* EMDIO */
	at91_set_A_periph(AT91_PIN_PE29, 0);	/* EMDC */

#ifndef CONFIG_RMII
	at91_set_A_periph(AT91_PIN_PE22, 0);	/* ECRS */
	at91_set_B_periph(AT91_PIN_PC26, 0);	/* ECOL */
	at91_set_B_periph(AT91_PIN_PC22, 0);	/* ERX2 */
	at91_set_B_periph(AT91_PIN_PC23, 0);	/* ERX3 */
	at91_set_B_periph(AT91_PIN_PC27, 0);	/* ERXCK */
	at91_set_B_periph(AT91_PIN_PC20, 0);	/* ETX2 */
	at91_set_B_periph(AT91_PIN_PC21, 0);	/* ETX3 */
	at91_set_B_periph(AT91_PIN_PC24, 0);	/* ETXER */
#endif

}
#endif

#ifdef CONFIG_USB_OHCI_NEW
static void at91sam9263ek_uhp_hw_init(void)
{
	/* Enable VBus on UHP ports */
	at91_set_gpio_output(AT91_PIN_PA21, 0);
	at91_set_gpio_output(AT91_PIN_PA24, 0);
}
#endif

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	vl_col:		240,
	vl_row:		320,
	vl_clk:		4965000,
	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
			ATMEL_LCDC_INVFRAME_INVERTED,
	vl_bpix:	3,
	vl_tft:		1,
	vl_hsync_len:	5,
	vl_left_margin:	1,
	vl_right_margin:33,
	vl_vsync_len:	1,
	vl_upper_margin:1,
	vl_lower_margin:0,
	mmio:		AT91SAM9263_LCDC_BASE,
};

void lcd_enable(void)
{
	at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power up */
}

void lcd_disable(void)
{
	at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power down */
}

static void at91sam9263ek_lcd_hw_init(void)
{
	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD13 */
	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD21 */
	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */

	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);

	gd->fb_base = AT91SAM9263_SRAM0_BASE;
}

#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>

void lcd_show_board_info(void)
{
	ulong dram_size, nand_size;
	int i;
	char temp[32];

	lcd_printf ("%s\n", U_BOOT_VERSION);
	lcd_printf ("(C) 2008 ATMEL Corp\n");
	lcd_printf ("at91support@atmel.com\n");
	lcd_printf ("%s CPU at %s MHz\n",
		AT91_CPU_NAME,
		strmhz(temp, AT91_CPU_CLOCK));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;
	nand_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i].size;
	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
		dram_size >> 20,
		nand_size >> 20 );
}
#endif /* CONFIG_LCD_INFO */
#endif

int board_init(void)
{
	/* Enable Ctrlc */
	console_init_f();

	/* arch number of AT91SAM9263EK-Board */
	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
	/* adress of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	at91_serial_hw_init();
#ifdef CONFIG_CMD_NAND
	at91sam9263ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
	at91_set_gpio_output(AT91_PIN_PE20, 1);	/* select spi0 clock */
	at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_MACB
	at91sam9263ek_macb_hw_init();
#endif
#ifdef CONFIG_USB_OHCI_NEW
	at91sam9263ek_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
	at91sam9263ek_lcd_hw_init();
#endif
	return 0;
}

int dram_init(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
	return 0;
}

#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
	/*
	 * Initialize ethernet HW addr prior to starting Linux,
	 * needed for nfsroot
	 */
	eth_init(gd->bd);
#endif
}
#endif

int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_MACB
	rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
#endif
	return rc;
}
Commit	Line	Data
8e429b3e SP	1	/*
	2	* (C) Copyright 2007-2008
	3	* Stelian Pop <stelian.pop@leadtechdesign.com>
	4	* Lead Tech Design <www.leadtechdesign.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
56a2479c	26	#include <asm/sizes.h>
8e429b3e SP	27	#include <asm/arch/at91sam9263.h>
	28	#include <asm/arch/at91sam9263_matrix.h>
	29	#include <asm/arch/at91sam9_smc.h>
1332a2a0	30	#include <asm/arch/at91_common.h>
8e429b3e SP	31	#include <asm/arch/at91_pmc.h>
	32	#include <asm/arch/at91_rstc.h>
	33	#include <asm/arch/gpio.h>
	34	#include <asm/arch/io.h>
3ae071e4	35	#include <asm/arch/hardware.h>
56a2479c SP	36	#include <lcd.h>
56a2479c SP	37	#include <atmel_lcdc.h>
8e429b3e SP	38	#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
	39	#include <net.h>
	40	#endif
3ae071e4	41	#include <netdev.h>
8e429b3e SP	42
	43	DECLARE_GLOBAL_DATA_PTR;
	44
	45	/* ------------------------------------------------------------------------- */
	46	/*
	47	* Miscelaneous platform dependent initialisations
	48	*/
	49
8e429b3e SP	50	#ifdef CONFIG_CMD_NAND
	51	static void at91sam9263ek_nand_hw_init(void)
	52	{
	53	unsigned long csa;
	54
	55	/* Enable CS3 */
	56	csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
	57	at91_sys_write(AT91_MATRIX_EBI0CSA,
	58	csa \| AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
	59
	60	/* Configure SMC CS3 for NAND/SmartMedia */
	61	at91_sys_write(AT91_SMC_SETUP(3),
d3bcdf83 PV	62	AT91_SMC_NWESETUP_(1) \| AT91_SMC_NCS_WRSETUP_(0) \|
d3bcdf83 PV	63	AT91_SMC_NRDSETUP_(1) \| AT91_SMC_NCS_RDSETUP_(0));
8e429b3e SP	64	at91_sys_write(AT91_SMC_PULSE(3),
	65	AT91_SMC_NWEPULSE_(3) \| AT91_SMC_NCS_WRPULSE_(3) \|
	66	AT91_SMC_NRDPULSE_(3) \| AT91_SMC_NCS_RDPULSE_(3));
	67	at91_sys_write(AT91_SMC_CYCLE(3),
	68	AT91_SMC_NWECYCLE_(5) \| AT91_SMC_NRDCYCLE_(5));
	69	at91_sys_write(AT91_SMC_MODE(3),
	70	AT91_SMC_READMODE \| AT91_SMC_WRITEMODE \|
	71	AT91_SMC_EXNWMODE_DISABLE \|
6d0f6bcf	72	#ifdef CONFIG_SYS_NAND_DBW_16
8e429b3e	73	AT91_SMC_DBW_16 \|
6d0f6bcf	74	#else /* CONFIG_SYS_NAND_DBW_8 */
8e429b3e SP	75	AT91_SMC_DBW_8 \|
	76	#endif
	77	AT91_SMC_TDF_(2));
	78
	79	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA \|
	80	1 << AT91SAM9263_ID_PIOCDE);
	81
	82	/* Configure RDY/BSY */
	83	at91_set_gpio_input(AT91_PIN_PA22, 1);
	84
	85	/* Enable NandFlash */
	86	at91_set_gpio_output(AT91_PIN_PD15, 1);
	87	}
	88	#endif
	89
8e429b3e SP	90	#ifdef CONFIG_MACB
	91	static void at91sam9263ek_macb_hw_init(void)
	92	{
	93	/* Enable clock */
	94	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
	95
	96	/*
	97	* Disable pull-up on:
	98	* RXDV (PC25) => PHY normal mode (not Test mode)
	99	* ERX0 (PE25) => PHY ADDR0
	100	* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
	101	*
	102	* PHY has internal pull-down
	103	*/
	104	writel(pin_to_mask(AT91_PIN_PC25),
	105	pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
	106	writel(pin_to_mask(AT91_PIN_PE25) \|
	107	pin_to_mask(AT91_PIN_PE26),
	108	pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
	109
	110	/* Need to reset PHY -> 500ms reset */
	111	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY \|
19bd6884	112	(AT91_RSTC_ERSTL & (0x0D << 8)) \|
8e429b3e SP	113	AT91_RSTC_URSTEN);
	114
	115	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY \| AT91_RSTC_EXTRST);
	116
	117	/* Wait for end hardware reset */
	118	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
	119
19bd6884 SP	120	/* Restore NRST value */
	121	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY \|
	122	(AT91_RSTC_ERSTL & (0x0 << 8)) \|
	123	AT91_RSTC_URSTEN);
	124
8e429b3e SP	125	/* Re-enable pull-up */
	126	writel(pin_to_mask(AT91_PIN_PC25),
	127	pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
	128	writel(pin_to_mask(AT91_PIN_PE25) \|
	129	pin_to_mask(AT91_PIN_PE26),
	130	pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
	131
	132	at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
	133	at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
	134	at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
	135	at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
	136	at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
	137	at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
	138	at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
	139	at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
	140	at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
	141	at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
	142
	143	#ifndef CONFIG_RMII
	144	at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
	145	at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
	146	at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
	147	at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
	148	at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
	149	at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
	150	at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
	151	at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
	152	#endif
	153
	154	}
	155	#endif
	156
	157	#ifdef CONFIG_USB_OHCI_NEW
	158	static void at91sam9263ek_uhp_hw_init(void)
	159	{
	160	/* Enable VBus on UHP ports */
	161	at91_set_gpio_output(AT91_PIN_PA21, 0);
	162	at91_set_gpio_output(AT91_PIN_PA24, 0);
	163	}
	164	#endif
	165
56a2479c SP	166	#ifdef CONFIG_LCD
	167	vidinfo_t panel_info = {
	168	vl_col: 240,
	169	vl_row: 320,
	170	vl_clk: 4965000,
	171	vl_sync: ATMEL_LCDC_INVLINE_INVERTED \|
	172	ATMEL_LCDC_INVFRAME_INVERTED,
	173	vl_bpix: 3,
	174	vl_tft: 1,
	175	vl_hsync_len: 5,
	176	vl_left_margin: 1,
	177	vl_right_margin:33,
	178	vl_vsync_len: 1,
	179	vl_upper_margin:1,
	180	vl_lower_margin:0,
	181	mmio: AT91SAM9263_LCDC_BASE,
	182	};
	183
	184	void lcd_enable(void)
	185	{
	186	at91_set_gpio_value(AT91_PIN_PA30, 1); /* power up */
	187	}
	188
	189	void lcd_disable(void)
	190	{
	191	at91_set_gpio_value(AT91_PIN_PA30, 0); /* power down */
	192	}
	193
	194	static void at91sam9263ek_lcd_hw_init(void)
	195	{
	196	at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
	197	at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
	198	at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
	199	at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
	200	at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
	201	at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
	202	at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
	203	at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
	204	at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
	205	at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
	206	at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
	207	at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
	208	at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
	209	at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
	210	at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
	211	at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
	212	at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
	213	at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
	214	at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
	215	at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
	216	at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
	217	at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
	218
	219	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
	220
	221	gd->fb_base = AT91SAM9263_SRAM0_BASE;
	222	}
6b59e03e HS	223
	224	#ifdef CONFIG_LCD_INFO
	225	#include <nand.h>
	226	#include <version.h>
	227
	228	void lcd_show_board_info(void)
	229	{
	230	ulong dram_size, nand_size;
	231	int i;
	232	char temp[32];
	233
	234	lcd_printf ("%s\n", U_BOOT_VERSION);
	235	lcd_printf ("(C) 2008 ATMEL Corp\n");
	236	lcd_printf ("at91support@atmel.com\n");
	237	lcd_printf ("%s CPU at %s MHz\n",
	238	AT91_CPU_NAME,
ad229a44	239	strmhz(temp, AT91_CPU_CLOCK));
6b59e03e HS	240
	241	dram_size = 0;
	242	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
	243	dram_size += gd->bd->bi_dram[i].size;
	244	nand_size = 0;
	245	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
	246	nand_size += nand_info[i].size;
	247	lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
	248	dram_size >> 20,
	249	nand_size >> 20 );
	250	}
	251	#endif /* CONFIG_LCD_INFO */
56a2479c SP	252	#endif
56a2479c SP	253
8e429b3e SP	254	int board_init(void)
	255	{
	256	/* Enable Ctrlc */
	257	console_init_f();
	258
	259	/* arch number of AT91SAM9263EK-Board */
	260	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
	261	/* adress of boot parameters */
	262	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	263
1332a2a0	264	at91_serial_hw_init();
8e429b3e SP	265	#ifdef CONFIG_CMD_NAND
	266	at91sam9263ek_nand_hw_init();
	267	#endif
	268	#ifdef CONFIG_HAS_DATAFLASH
7ebafb7e JCPV	269	at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */
7ebafb7e JCPV	270	at91_spi0_hw_init(1 << 0);
8e429b3e SP	271	#endif
	272	#ifdef CONFIG_MACB
	273	at91sam9263ek_macb_hw_init();
	274	#endif
	275	#ifdef CONFIG_USB_OHCI_NEW
	276	at91sam9263ek_uhp_hw_init();
56a2479c SP	277	#endif
	278	#ifdef CONFIG_LCD
	279	at91sam9263ek_lcd_hw_init();
8e429b3e SP	280	#endif
	281	return 0;
	282	}
	283
	284	int dram_init(void)
	285	{
	286	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	287	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
	288	return 0;
	289	}
	290
	291	#ifdef CONFIG_RESET_PHY_R
	292	void reset_phy(void)
	293	{
	294	#ifdef CONFIG_MACB
	295	/*
	296	* Initialize ethernet HW addr prior to starting Linux,
	297	* needed for nfsroot
	298	*/
	299	eth_init(gd->bd);
	300	#endif
	301	}
	302	#endif
3ae071e4 BW	303
	304	int board_eth_init(bd_t *bis)
	305	{
	306	int rc = 0;
	307	#ifdef CONFIG_MACB
d8003fa0	308	rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
3ae071e4 BW	309	#endif
	310	return rc;
	311	}