[people/ms/u-boot.git] / board / atmel / at91sam9263ek / at91sam9263ek.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <linux/sizes.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hardware.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
#include <netdev.h>
#include <atmel_mci.h>

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_CMD_NAND
static void at91sam9263ek_nand_hw_init(void)
{
	unsigned long csa;
	at91_smc_t    *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
	at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;

	/* Enable CS3 */
	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
	writel(csa, &matrix->csa[0]);

	/* Enable CS3 */

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);

	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
		&smc->cs[3].pulse);

	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
		&smc->cs[3].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
		       AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
		       AT91_SMC_MODE_DBW_8 |
#endif
		       AT91_SMC_MODE_TDF_CYCLE(2),
		&smc->cs[3].mode);

	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOCDE);

	/* Configure RDY/BSY */
	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif

#ifdef CONFIG_MACB
static void at91sam9263ek_macb_hw_init(void)
{
	at91_pio_t	*pio	= (at91_pio_t *) ATMEL_BASE_PIO;

	at91_periph_clk_enable(ATMEL_ID_EMAC);

	/*
	 * Disable pull-up on:
	 *	RXDV (PC25) => PHY normal mode (not Test mode)
	 * 	ERX0 (PE25) => PHY ADDR0
	 *	ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
	 *
	 * PHY has internal pull-down
	 */
	writel(1 << 25, &pio->pioc.pudr);
	writel((1 << 25) | (1 <<26), &pio->pioe.pudr);

	at91_phy_reset();

	/* Re-enable pull-up */
	writel(1 << 25, &pio->pioc.puer);
	writel((1 << 25) | (1 <<26), &pio->pioe.puer);

	at91_macb_hw_init();
}
#endif

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	.vl_col =		240,
	.vl_row =		320,
	.vl_clk =		4965000,
	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
				ATMEL_LCDC_INVFRAME_INVERTED,
	.vl_bpix =		3,
	.vl_tft =		1,
	.vl_hsync_len =		5,
	.vl_left_margin =	1,
	.vl_right_margin =	33,
	.vl_vsync_len =		1,
	.vl_upper_margin =	1,
	.vl_lower_margin =	0,
	.mmio =			ATMEL_BASE_LCDC,
};

void lcd_enable(void)
{
	at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power up */
}

void lcd_disable(void)
{
	at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power down */
}

static void at91sam9263ek_lcd_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */

	at91_periph_clk_enable(ATMEL_ID_LCDC);
	gd->fb_base = ATMEL_BASE_SRAM0;
}

#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>

#ifdef CONFIG_MTD_NOR_FLASH
extern flash_info_t flash_info[];
#endif

void lcd_show_board_info(void)
{
	ulong dram_size, nand_size;
#ifdef CONFIG_MTD_NOR_FLASH
	ulong flash_size;
#endif
	int i;
	char temp[32];

	lcd_printf ("%s\n", U_BOOT_VERSION);
	lcd_printf ("(C) 2008 ATMEL Corp\n");
	lcd_printf ("at91support@atmel.com\n");
	lcd_printf ("%s CPU at %s MHz\n",
		ATMEL_CPU_NAME,
		strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;
	nand_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i]->size;
#ifdef CONFIG_MTD_NOR_FLASH
	flash_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
		flash_size += flash_info[i].size;
#endif
	lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
		dram_size >> 20,
		nand_size >> 20 );
#ifdef CONFIG_MTD_NOR_FLASH
	lcd_printf (",\n  %ld MB NOR",
		flash_size >> 20);
#endif
	lcd_puts ("\n");
}
#endif /* CONFIG_LCD_INFO */
#endif

#ifdef CONFIG_GENERIC_ATMEL_MCI
int board_mmc_init(bd_t *bd)
{
	at91_mci_hw_init();

	return atmel_mci_init((void *)ATMEL_BASE_MCI1);
}
#endif

int board_early_init_f(void)
{
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOB);
	at91_periph_clk_enable(ATMEL_ID_PIOCDE);

	at91_seriald_hw_init();
	return 0;
}

int board_init(void)
{
	/* arch number of AT91SAM9263EK-Board */
	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_CMD_NAND
	at91sam9263ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
	at91_set_pio_output(AT91_PIO_PORTE, 20, 1);	/* select spi0 clock */
	at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_MACB
	at91sam9263ek_macb_hw_init();
#endif
#ifdef CONFIG_USB_OHCI_NEW
	at91_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
	at91sam9263ek_lcd_hw_init();
#endif
	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
		CONFIG_SYS_SDRAM_SIZE);

	return 0;
}

#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
}
#endif

int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_MACB
	rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
#endif
	return rc;
}
Commit	Line	Data
8e429b3e SP	1	/*
8e429b3e SP	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
8e429b3e SP	4	* Lead Tech Design <www.leadtechdesign.com>
8e429b3e SP	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
8e429b3e SP	7	*/
	8
	9	#include <common.h>
1ace4022	10	#include <linux/sizes.h>
8e429b3e	11	#include <asm/arch/at91sam9263.h>
8e429b3e	12	#include <asm/arch/at91sam9_smc.h>
1332a2a0	13	#include <asm/arch/at91_common.h>
1b34f00c JS	14	#include <asm/arch/at91_matrix.h>
1b34f00c JS	15	#include <asm/arch/at91_pio.h>
dc39ae95	16	#include <asm/arch/clk.h>
cd46b0f2 XH	17	#include <asm/io.h>
cd46b0f2 XH	18	#include <asm/arch/gpio.h>
3ae071e4	19	#include <asm/arch/hardware.h>
56a2479c SP	20	#include <lcd.h>
56a2479c SP	21	#include <atmel_lcdc.h>
8e429b3e SP	22	#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
	23	#include <net.h>
	24	#endif
3ae071e4	25	#include <netdev.h>
81724e09	26	#include <atmel_mci.h>
8e429b3e SP	27
	28	DECLARE_GLOBAL_DATA_PTR;
	29
	30	/* ------------------------------------------------------------------------- */
	31	/*
	32	* Miscelaneous platform dependent initialisations
	33	*/
	34
8e429b3e SP	35	#ifdef CONFIG_CMD_NAND
	36	static void at91sam9263ek_nand_hw_init(void)
	37	{
	38	unsigned long csa;
cd46b0f2 XH	39	at91_smc_t smc = (at91_smc_t ) ATMEL_BASE_SMC0;
cd46b0f2 XH	40	at91_matrix_t matrix = (at91_matrix_t ) ATMEL_BASE_MATRIX;
1b34f00c JS	41
	42	/* Enable CS3 */
	43	csa = readl(&matrix->csa[0]) \| AT91_MATRIX_CSA_EBI_CS3A;
	44	writel(csa, &matrix->csa[0]);
8e429b3e SP	45
8e429b3e SP	46	/* Enable CS3 */
8e429b3e SP	47
8e429b3e SP	48	/* Configure SMC CS3 for NAND/SmartMedia */
1b34f00c JS	49	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(0) \|
	50	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(0),
	51	&smc->cs[3].setup);
	52
	53	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(3) \|
	54	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(3),
	55	&smc->cs[3].pulse);
	56
	57	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
	58	&smc->cs[3].cycle);
	59	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	60	AT91_SMC_MODE_EXNW_DISABLE \|
6d0f6bcf	61	#ifdef CONFIG_SYS_NAND_DBW_16
1b34f00c	62	AT91_SMC_MODE_DBW_16 \|
6d0f6bcf	63	#else /* CONFIG_SYS_NAND_DBW_8 */
1b34f00c	64	AT91_SMC_MODE_DBW_8 \|
8e429b3e	65	#endif
1b34f00c JS	66	AT91_SMC_MODE_TDF_CYCLE(2),
1b34f00c JS	67	&smc->cs[3].mode);
8e429b3e	68
70341e2e WY	69	at91_periph_clk_enable(ATMEL_ID_PIOA);
70341e2e WY	70	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
8e429b3e SP	71
8e429b3e SP	72	/* Configure RDY/BSY */
cd46b0f2	73	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
8e429b3e SP	74
8e429b3e SP	75	/* Enable NandFlash */
cd46b0f2	76	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
8e429b3e SP	77	}
	78	#endif
	79
8e429b3e SP	80	#ifdef CONFIG_MACB
	81	static void at91sam9263ek_macb_hw_init(void)
	82	{
cd46b0f2	83	at91_pio_t pio = (at91_pio_t ) ATMEL_BASE_PIO;
4535a24c	84
70341e2e	85	at91_periph_clk_enable(ATMEL_ID_EMAC);
8e429b3e SP	86
	87	/*
	88	* Disable pull-up on:
	89	* RXDV (PC25) => PHY normal mode (not Test mode)
	90	* ERX0 (PE25) => PHY ADDR0
	91	* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
	92	*
	93	* PHY has internal pull-down
	94	*/
1b34f00c JS	95	writel(1 << 25, &pio->pioc.pudr);
1b34f00c JS	96	writel((1 << 25) \| (1 <<26), &pio->pioe.pudr);
0aafde1d	97
4535a24c	98	at91_phy_reset();
19bd6884	99
8e429b3e	100	/* Re-enable pull-up */
1b34f00c JS	101	writel(1 << 25, &pio->pioc.puer);
1b34f00c JS	102	writel((1 << 25) \| (1 <<26), &pio->pioe.puer);
8e429b3e	103
e2c0476f	104	at91_macb_hw_init();
8e429b3e SP	105	}
	106	#endif
	107
56a2479c SP	108	#ifdef CONFIG_LCD
56a2479c SP	109	vidinfo_t panel_info = {
c346e466 JH	110	.vl_col = 240,
	111	.vl_row = 320,
	112	.vl_clk = 4965000,
	113	.vl_sync = ATMEL_LCDC_INVLINE_INVERTED \|
	114	ATMEL_LCDC_INVFRAME_INVERTED,
	115	.vl_bpix = 3,
	116	.vl_tft = 1,
	117	.vl_hsync_len = 5,
	118	.vl_left_margin = 1,
	119	.vl_right_margin = 33,
	120	.vl_vsync_len = 1,
	121	.vl_upper_margin = 1,
	122	.vl_lower_margin = 0,
	123	.mmio = ATMEL_BASE_LCDC,
56a2479c SP	124	};
	125
	126	void lcd_enable(void)
	127	{
1b34f00c	128	at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */
56a2479c SP	129	}
	130
	131	void lcd_disable(void)
	132	{
1b34f00c	133	at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */
56a2479c SP	134	}
	135
	136	static void at91sam9263ek_lcd_hw_init(void)
	137	{
1b34f00c JS	138	at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
	139	at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
	140	at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
	141	at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
	142	at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
	143	at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
	144	at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
	145	at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
	146	at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
	147	at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
	148	at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
	149	at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
	150	at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
	151	at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
	152	at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
	153	at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
	154	at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
	155	at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
	156	at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
	157	at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
	158	at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
	159	at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
	160
70341e2e	161	at91_periph_clk_enable(ATMEL_ID_LCDC);
cd46b0f2	162	gd->fb_base = ATMEL_BASE_SRAM0;
56a2479c	163	}
6b59e03e HS	164
	165	#ifdef CONFIG_LCD_INFO
	166	#include <nand.h>
	167	#include <version.h>
	168
e856bdcf	169	#ifdef CONFIG_MTD_NOR_FLASH
1b3b7c64 JCPV	170	extern flash_info_t flash_info[];
	171	#endif
	172
6b59e03e HS	173	void lcd_show_board_info(void)
	174	{
	175	ulong dram_size, nand_size;
e856bdcf	176	#ifdef CONFIG_MTD_NOR_FLASH
1b3b7c64 JCPV	177	ulong flash_size;
1b3b7c64 JCPV	178	#endif
6b59e03e HS	179	int i;
	180	char temp[32];
	181
	182	lcd_printf ("%s\n", U_BOOT_VERSION);
	183	lcd_printf ("(C) 2008 ATMEL Corp\n");
	184	lcd_printf ("at91support@atmel.com\n");
	185	lcd_printf ("%s CPU at %s MHz\n",
cd46b0f2	186	ATMEL_CPU_NAME,
dc39ae95	187	strmhz(temp, get_cpu_clk_rate()));
6b59e03e HS	188
	189	dram_size = 0;
	190	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
	191	dram_size += gd->bd->bi_dram[i].size;
	192	nand_size = 0;
	193	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
b616d9b0	194	nand_size += nand_info[i]->size;
e856bdcf	195	#ifdef CONFIG_MTD_NOR_FLASH
1b3b7c64 JCPV	196	flash_size = 0;
	197	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
	198	flash_size += flash_info[i].size;
	199	#endif
	200	lcd_printf (" %ld MB SDRAM, %ld MB NAND",
6b59e03e HS	201	dram_size >> 20,
6b59e03e HS	202	nand_size >> 20 );
e856bdcf	203	#ifdef CONFIG_MTD_NOR_FLASH
1b3b7c64 JCPV	204	lcd_printf (",\n %ld MB NOR",
	205	flash_size >> 20);
	206	#endif
	207	lcd_puts ("\n");
6b59e03e HS	208	}
6b59e03e HS	209	#endif /* CONFIG_LCD_INFO */
56a2479c SP	210	#endif
56a2479c SP	211
81724e09 AH	212	#ifdef CONFIG_GENERIC_ATMEL_MCI
	213	int board_mmc_init(bd_t *bd)
	214	{
	215	at91_mci_hw_init();
	216
	217	return atmel_mci_init((void *)ATMEL_BASE_MCI1);
	218	}
	219	#endif
	220
cd46b0f2 XH	221	int board_early_init_f(void)
cd46b0f2 XH	222	{
70341e2e WY	223	at91_periph_clk_enable(ATMEL_ID_PIOA);
	224	at91_periph_clk_enable(ATMEL_ID_PIOB);
	225	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
cd46b0f2	226
2feb7366	227	at91_seriald_hw_init();
cd46b0f2 XH	228	return 0;
	229	}
	230
8e429b3e SP	231	int board_init(void)
8e429b3e SP	232	{
8e429b3e SP	233	/* arch number of AT91SAM9263EK-Board */
	234	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
	235	/* adress of boot parameters */
cd46b0f2	236	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
8e429b3e	237
8e429b3e SP	238	#ifdef CONFIG_CMD_NAND
	239	at91sam9263ek_nand_hw_init();
	240	#endif
	241	#ifdef CONFIG_HAS_DATAFLASH
1b34f00c	242	at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */
7ebafb7e	243	at91_spi0_hw_init(1 << 0);
8e429b3e SP	244	#endif
	245	#ifdef CONFIG_MACB
	246	at91sam9263ek_macb_hw_init();
	247	#endif
	248	#ifdef CONFIG_USB_OHCI_NEW
f3f91f88	249	at91_uhp_hw_init();
56a2479c SP	250	#endif
	251	#ifdef CONFIG_LCD
	252	at91sam9263ek_lcd_hw_init();
8e429b3e SP	253	#endif
	254	return 0;
	255	}
	256
	257	int dram_init(void)
	258	{
cd46b0f2 XH	259	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
	260	CONFIG_SYS_SDRAM_SIZE);
	261
8e429b3e SP	262	return 0;
	263	}
	264
	265	#ifdef CONFIG_RESET_PHY_R
	266	void reset_phy(void)
	267	{
8e429b3e SP	268	}
8e429b3e SP	269	#endif
3ae071e4 BW	270
	271	int board_eth_init(bd_t *bis)
	272	{
	273	int rc = 0;
	274	#ifdef CONFIG_MACB
cd46b0f2	275	rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
3ae071e4 BW	276	#endif
	277	return rc;
	278	}