[people/ms/u-boot.git] / board / atmel / sama5d2_xplained / sama5d2_xplained.c

/*
 * Copyright (C) 2015 Atmel Corporation
 *		      Wenyou.Yang <wenyou.yang@atmel.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <debug_uart.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_pio4.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/atmel_sdhci.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sama5d2.h>

DECLARE_GLOBAL_DATA_PTR;

static void board_usb_hw_init(void)
{
	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
}

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_DM_VIDEO
	at91_video_show_board_info();
#endif
	return 0;
}
#endif

#ifdef CONFIG_DEBUG_UART_BOARD_INIT
static void board_uart1_hw_init(void)
{
	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1);	/* URXD1 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);	/* UTXD1 */

	at91_periph_clk_enable(ATMEL_ID_UART1);
}

void board_debug_uart_init(void)
{
	board_uart1_hw_init();
}
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
#ifdef CONFIG_DEBUG_UART
	debug_uart_init();
#endif

	return 0;
}
#endif

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_CMD_USB
	board_usb_hw_init();
#endif

	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);
	return 0;
}

#define AT24MAC_MAC_OFFSET	0x9a

#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
#ifdef CONFIG_I2C_EEPROM
	at91_set_ethaddr(AT24MAC_MAC_OFFSET);
#endif

	return 0;
}
#endif

/* SPL */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
}

static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
{
	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);

	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
		    ATMEL_MPDDRC_CR_NR_ROW_14 |
		    ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
		    ATMEL_MPDDRC_CR_DIC_DS |
		    ATMEL_MPDDRC_CR_DIS_DLL |
		    ATMEL_MPDDRC_CR_NB_8BANKS |
		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);

	ddrc->rtr = 0x511;

	ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
		      3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
		      4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
		      9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
		      3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
		      4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
		      4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
		      4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);

	ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET |
		      29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
		      0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
		      3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET);

	ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET |
		      0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
		      4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
		      7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
}

void mem_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
	struct atmel_mpddrc_config ddrc_config;
	u32 reg;

	ddrc_conf(&ddrc_config);

	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
	writel(AT91_PMC_DDR, &pmc->scer);

	reg = readl(&mpddrc->io_calibr);
	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
	reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
	writel(reg, &mpddrc->io_calibr);

	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
	       &mpddrc->rd_data_path);

	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);

	writel(0x3, &mpddrc->cal_mr4);
	writel(64, &mpddrc->tim_cal);
}

void at91_pmc_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	u32 tmp;

	/*
	 * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
	 * so we need to slow down and configure MCKR accordingly.
	 * This is why we have a special flavor of the switching function.
	 */
	tmp = AT91_PMC_MCKR_PLLADIV_2 |
	      AT91_PMC_MCKR_MDIV_3 |
	      AT91_PMC_MCKR_CSS_MAIN;
	at91_mck_init_down(tmp);

	tmp = AT91_PMC_PLLAR_29 |
	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
	      AT91_PMC_PLLXR_MUL(82) |
	      AT91_PMC_PLLXR_DIV(1);
	at91_plla_init(tmp);

	writel(0x0 << 8, &pmc->pllicpr);

	tmp = AT91_PMC_MCKR_H32MXDIV |
	      AT91_PMC_MCKR_PLLADIV_2 |
	      AT91_PMC_MCKR_MDIV_3 |
	      AT91_PMC_MCKR_CSS_PLLA;
	at91_mck_init(tmp);
}
#endif
Commit	Line	Data
75238f23 WY	1	/*
	2	* Copyright (C) 2015 Atmel Corporation
	3	* Wenyou.Yang <wenyou.yang@atmel.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
2992dd83	9	#include <debug_uart.h>
75238f23 WY	10	#include <asm/io.h>
75238f23 WY	11	#include <asm/arch/at91_common.h>
75238f23	12	#include <asm/arch/atmel_pio4.h>
37dadbca	13	#include <asm/arch/atmel_mpddrc.h>
75238f23 WY	14	#include <asm/arch/atmel_sdhci.h>
	15	#include <asm/arch/clk.h>
	16	#include <asm/arch/gpio.h>
	17	#include <asm/arch/sama5d2.h>
	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
75238f23 WY	21	static void board_usb_hw_init(void)
	22	{
	23	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
	24	}
	25
d2cd09bb WY	26	#ifdef CONFIG_BOARD_LATE_INIT
d2cd09bb WY	27	int board_late_init(void)
75238f23	28	{
d2cd09bb WY	29	#ifdef CONFIG_DM_VIDEO
	30	at91_video_show_board_info();
	31	#endif
	32	return 0;
75238f23	33	}
d2cd09bb	34	#endif
75238f23	35
ed03b1ba	36	#ifdef CONFIG_DEBUG_UART_BOARD_INIT
75238f23 WY	37	static void board_uart1_hw_init(void)
	38	{
	39	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */
	40	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
	41
	42	at91_periph_clk_enable(ATMEL_ID_UART1);
	43	}
	44
2992dd83 WY	45	void board_debug_uart_init(void)
	46	{
	47	board_uart1_hw_init();
	48	}
	49	#endif
	50
	51	#ifdef CONFIG_BOARD_EARLY_INIT_F
75238f23 WY	52	int board_early_init_f(void)
75238f23 WY	53	{
2992dd83 WY	54	#ifdef CONFIG_DEBUG_UART
2992dd83 WY	55	debug_uart_init();
2992dd83	56	#endif
75238f23 WY	57
	58	return 0;
	59	}
2992dd83	60	#endif
75238f23 WY	61
	62	int board_init(void)
	63	{
	64	/* address of boot parameters */
	65	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	66
75238f23 WY	67	#ifdef CONFIG_CMD_USB
	68	board_usb_hw_init();
	69	#endif
75238f23 WY	70
	71	return 0;
	72	}
	73
	74	int dram_init(void)
	75	{
	76	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
	77	CONFIG_SYS_SDRAM_SIZE);
	78	return 0;
	79	}
	80
34e2819d	81	#define AT24MAC_MAC_OFFSET 0x9a
0daa2e18 WY	82
	83	#ifdef CONFIG_MISC_INIT_R
	84	int misc_init_r(void)
	85	{
34e2819d WY	86	#ifdef CONFIG_I2C_EEPROM
	87	at91_set_ethaddr(AT24MAC_MAC_OFFSET);
	88	#endif
0daa2e18 WY	89
	90	return 0;
	91	}
	92	#endif
	93
37dadbca WY	94	/* SPL */
	95	#ifdef CONFIG_SPL_BUILD
	96	void spl_board_init(void)
	97	{
37dadbca WY	98	}
	99
	100	static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
	101	{
	102	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS \| ATMEL_MPDDRC_MD_DDR3_SDRAM);
	103
	104	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 \|
	105	ATMEL_MPDDRC_CR_NR_ROW_14 \|
	106	ATMEL_MPDDRC_CR_CAS_DDR_CAS5 \|
	107	ATMEL_MPDDRC_CR_DIC_DS \|
	108	ATMEL_MPDDRC_CR_DIS_DLL \|
	109	ATMEL_MPDDRC_CR_NB_8BANKS \|
	110	ATMEL_MPDDRC_CR_DECOD_INTERLEAVED \|
	111	ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
	112
	113	ddrc->rtr = 0x511;
	114
	115	ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET \|
	116	3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \|
	117	4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET \|
	118	9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET \|
	119	3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET \|
	120	4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET \|
	121	4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET \|
	122	4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
	123
	124	ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET \|
	125	29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET \|
	126	0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET \|
	127	3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET);
	128
	129	ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET \|
	130	0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET \|
	131	0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET \|
	132	4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET \|
	133	7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
	134	}
	135
	136	void mem_init(void)
	137	{
	138	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	139	struct atmel_mpddr mpddrc = (struct atmel_mpddr )ATMEL_BASE_MPDDRC;
	140	struct atmel_mpddrc_config ddrc_config;
	141	u32 reg;
	142
	143	ddrc_conf(&ddrc_config);
	144
	145	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
	146	writel(AT91_PMC_DDR, &pmc->scer);
	147
	148	reg = readl(&mpddrc->io_calibr);
	149	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
	150	reg \|= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
	151	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
	152	reg \|= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
	153	writel(reg, &mpddrc->io_calibr);
	154
	155	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
	156	&mpddrc->rd_data_path);
	157
	158	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
	159
	160	writel(0x3, &mpddrc->cal_mr4);
	161	writel(64, &mpddrc->tim_cal);
162	}
163
164	void at91_pmc_init(void)
165	{
166	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
167	u32 tmp;
168
23a19e03 WY	169	/*
	170	* while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
	171	* so we need to slow down and configure MCKR accordingly.
	172	* This is why we have a special flavor of the switching function.
	173	*/
	174	tmp = AT91_PMC_MCKR_PLLADIV_2 \|
	175	AT91_PMC_MCKR_MDIV_3 \|
	176	AT91_PMC_MCKR_CSS_MAIN;
	177	at91_mck_init_down(tmp);
	178
37dadbca WY	179	tmp = AT91_PMC_PLLAR_29 \|
	180	AT91_PMC_PLLXR_PLLCOUNT(0x3f) \|
	181	AT91_PMC_PLLXR_MUL(82) \|
	182	AT91_PMC_PLLXR_DIV(1);
	183	at91_plla_init(tmp);
	184
	185	writel(0x0 << 8, &pmc->pllicpr);
	186
	187	tmp = AT91_PMC_MCKR_H32MXDIV \|
	188	AT91_PMC_MCKR_PLLADIV_2 \|
	189	AT91_PMC_MCKR_MDIV_3 \|
	190	AT91_PMC_MCKR_CSS_PLLA;
	191	at91_mck_init(tmp);
	192	}
	193	#endif