[people/ms/u-boot.git] / board / atmel / sama5d4ek / sama5d4ek.c

/*
 * Copyright (C) 2014 Atmel
 *		      Bo Shen <voice.shen@atmel.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/atmel_usba_udc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/sama5d4.h>
#include <atmel_hlcdc.h>
#include <atmel_mci.h>
#include <lcd.h>
#include <mmc.h>
#include <net.h>
#include <netdev.h>
#include <nand.h>
#include <spi.h>
#include <version.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_ATMEL_SPI
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus == 0 && cs == 0;
}

void spi_cs_activate(struct spi_slave *slave)
{
	at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
}

static void sama5d4ek_spi0_hw_init(void)
{
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* SPI0_MISO */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* SPI0_MOSI */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* SPI0_SPCK */

	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);	/* SPI0_CS0 */

	/* Enable clock */
	at91_periph_clk_enable(ATMEL_ID_SPI0);
}
#endif /* CONFIG_ATMEL_SPI */

#ifdef CONFIG_NAND_ATMEL
static void sama5d4ek_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;

	at91_periph_clk_enable(ATMEL_ID_SMC);

	/* Configure SMC CS3 for NAND */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
	       &smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
	       AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
	       &smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
	       &smc->cs[3].cycle);
	writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
	       AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
	       AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3)|
	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
	       AT91_SMC_MODE_EXNW_DISABLE |
	       AT91_SMC_MODE_DBW_8 |
	       AT91_SMC_MODE_TDF_CYCLE(3),
	       &smc->cs[3].mode);

	at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* D0 */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* D1 */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* D2 */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* D3 */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* D4 */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* D5 */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* D6 */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* D7 */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* RE */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* WE */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1);	/* NCS */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1);	/* RDY */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1);	/* ALE */
	at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1);	/* CLE */
}
#endif

#ifdef CONFIG_CMD_USB
static void sama5d4ek_usb_hw_init(void)
{
	at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
	at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
	at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
}
#endif

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	.vl_col = 800,
	.vl_row = 480,
	.vl_clk = 33260000,
	.vl_bpix = LCD_BPP,
	.vl_tft = 1,
	.vl_hsync_len = 5,
	.vl_left_margin = 128,
	.vl_right_margin = 0,
	.vl_vsync_len = 5,
	.vl_upper_margin = 23,
	.vl_lower_margin = 22,
	.mmio = ATMEL_BASE_LCDC,
};

/* No power up/down pin for the LCD pannel */
void lcd_enable(void)	{ /* Empty! */ }
void lcd_disable(void)	{ /* Empty! */ }

unsigned int has_lcdc(void)
{
	return 1;
}

static void sama5d4ek_lcd_hw_init(void)
{
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0);	/* LCDPWM */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0);	/* LCDDEN */

	at91_pio3_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */

	at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */

	at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* LCDD18 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* LCDD19 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* LCDD20 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* LCDD21 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0);	/* LCDD22 */
	at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0);	/* LCDD23 */

	/* Enable clock */
	at91_periph_clk_enable(ATMEL_ID_LCDC);
}

#ifdef CONFIG_LCD_INFO
void lcd_show_board_info(void)
{
	ulong dram_size, nand_size;
	int i;
	char temp[32];

	lcd_printf("%s\n", U_BOOT_VERSION);
	lcd_printf("2014 ATMEL Corp\n");
	lcd_printf("at91@atmel.com\n");
	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
		   strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;

	nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i]->size;
#endif
	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
		   dram_size >> 20, nand_size >> 20);
}
#endif /* CONFIG_LCD_INFO */

#endif /* CONFIG_LCD */

#ifdef CONFIG_GENERIC_ATMEL_MCI
void sama5d4ek_mci1_hw_init(void)
{
	at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1);	/* MCI1 CDA */
	at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1);	/* MCI1 DA0 */
	at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1);	/* MCI1 DA1 */
	at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1);	/* MCI1 DA2 */
	at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1);	/* MCI1 DA3 */
	at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0);	/* MCI1 CLK */

	/*
	 * As the mci io internal pull down is too strong, so if the io needs
	 * external pull up, the pull up resistor will be very small, if so
	 * the power consumption will increase, so disable the interanl pull
	 * down to save the power.
	 */
	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);

	/* Enable clock */
	at91_periph_clk_enable(ATMEL_ID_MCI1);
}

int board_mmc_init(bd_t *bis)
{
	/* Enable power for MCI1 interface */
	at91_set_pio_output(AT91_PIO_PORTE, 15, 0);

	return atmel_mci_init((void *)ATMEL_BASE_MCI1);
}
#endif /* CONFIG_GENERIC_ATMEL_MCI */

#ifdef CONFIG_MACB
void sama5d4ek_macb0_hw_init(void)
{
	at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ETXCK_EREFCK */
	at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* ERXDV */
	at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ERX0 */
	at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ERX1 */
	at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ERXER */
	at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ETXEN */
	at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX0 */
	at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ETX1 */
	at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* EMDIO */
	at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* EMDC */

	/* Enable clock */
	at91_periph_clk_enable(ATMEL_ID_GMAC0);
}
#endif

static void sama5d4ek_serial3_hw_init(void)
{
	at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);	/* TXD3 */
	at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);	/* RXD3 */

	/* Enable clock */
	at91_periph_clk_enable(ATMEL_ID_USART3);
}

int board_early_init_f(void)
{
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOB);
	at91_periph_clk_enable(ATMEL_ID_PIOC);
	at91_periph_clk_enable(ATMEL_ID_PIOD);
	at91_periph_clk_enable(ATMEL_ID_PIOE);

	sama5d4ek_serial3_hw_init();

	return 0;
}

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_ATMEL_SPI
	sama5d4ek_spi0_hw_init();
#endif
#ifdef CONFIG_NAND_ATMEL
	sama5d4ek_nand_hw_init();
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
	sama5d4ek_mci1_hw_init();
#endif
#ifdef CONFIG_MACB
	sama5d4ek_macb0_hw_init();
#endif
#ifdef CONFIG_LCD
	sama5d4ek_lcd_hw_init();
#endif
#ifdef CONFIG_CMD_USB
	sama5d4ek_usb_hw_init();
#endif
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	at91_udp_hw_init();
#endif

	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);
	return 0;
}

int board_eth_init(bd_t *bis)
{
	int rc = 0;

#ifdef CONFIG_MACB
	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
#endif

#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	usba_udc_probe(&pdata);
#ifdef CONFIG_USB_ETH_RNDIS
	usb_eth_initialize(bis);
#endif
#endif

	return rc;
}

/* SPL */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
#ifdef CONFIG_SYS_USE_MMC
	sama5d4ek_mci1_hw_init();
#elif CONFIG_SYS_USE_NANDFLASH
	sama5d4ek_nand_hw_init();
#elif CONFIG_SYS_USE_SERIALFLASH
	sama5d4ek_spi0_hw_init();
#endif
}

static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
{
	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);

	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
		    ATMEL_MPDDRC_CR_NR_ROW_14 |
		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
		    ATMEL_MPDDRC_CR_NB_8BANKS |
		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);

	ddr2->rtr = 0x2b0;

	ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
		      3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
		      3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
		      10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
		      3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);

	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
		      25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
		      23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);

	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
		      2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}

void mem_init(void)
{
	struct atmel_mpddrc_config ddr2;

	ddr2_conf(&ddr2);

	/* Enable MPDDR clock */
	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
	at91_system_clk_enable(AT91_PMC_DDR);

	/* DDRAM2 Controller initialize */
	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
}

void at91_pmc_init(void)
{
	u32 tmp;

	tmp = AT91_PMC_PLLAR_29 |
	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
	      AT91_PMC_PLLXR_MUL(87) |
	      AT91_PMC_PLLXR_DIV(1);
	at91_plla_init(tmp);

	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));

	tmp = AT91_PMC_MCKR_H32MXDIV |
	      AT91_PMC_MCKR_PLLADIV_2 |
	      AT91_PMC_MCKR_MDIV_3 |
	      AT91_PMC_MCKR_CSS_PLLA;
	at91_mck_init(tmp);
}
#endif
Commit	Line	Data
927b901b BS	1	/*
	2	* Copyright (C) 2014 Atmel
	3	* Bo Shen <voice.shen@atmel.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <asm/io.h>
	10	#include <asm/arch/at91_common.h>
927b901b	11	#include <asm/arch/at91_rstc.h>
5a4c9c22	12	#include <asm/arch/atmel_mpddrc.h>
da08d791	13	#include <asm/arch/atmel_usba_udc.h>
927b901b BS	14	#include <asm/arch/gpio.h>
	15	#include <asm/arch/clk.h>
	16	#include <asm/arch/sama5d3_smc.h>
	17	#include <asm/arch/sama5d4.h>
f8009a7a	18	#include <atmel_hlcdc.h>
927b901b BS	19	#include <atmel_mci.h>
	20	#include <lcd.h>
	21	#include <mmc.h>
	22	#include <net.h>
	23	#include <netdev.h>
	24	#include <nand.h>
	25	#include <spi.h>
02fc64d1	26	#include <version.h>
927b901b BS	27
	28	DECLARE_GLOBAL_DATA_PTR;
	29
	30	#ifdef CONFIG_ATMEL_SPI
	31	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	32	{
	33	return bus == 0 && cs == 0;
	34	}
	35
	36	void spi_cs_activate(struct spi_slave *slave)
	37	{
	38	at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
	39	}
	40
	41	void spi_cs_deactivate(struct spi_slave *slave)
	42	{
	43	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
	44	}
	45
	46	static void sama5d4ek_spi0_hw_init(void)
	47	{
2dc63f73 WY	48	at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
	49	at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
	50	at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
927b901b BS	51
	52	at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
	53
	54	/* Enable clock */
	55	at91_periph_clk_enable(ATMEL_ID_SPI0);
	56	}
	57	#endif /* CONFIG_ATMEL_SPI */
	58
	59	#ifdef CONFIG_NAND_ATMEL
	60	static void sama5d4ek_nand_hw_init(void)
	61	{
	62	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	63
	64	at91_periph_clk_enable(ATMEL_ID_SMC);
	65
	66	/* Configure SMC CS3 for NAND */
	67	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(1) \|
	68	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(1),
	69	&smc->cs[3].setup);
	70	writel(AT91_SMC_PULSE_NWE(2) \| AT91_SMC_PULSE_NCS_WR(3) \|
	71	AT91_SMC_PULSE_NRD(2) \| AT91_SMC_PULSE_NCS_RD(3),
	72	&smc->cs[3].pulse);
	73	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
	74	&smc->cs[3].cycle);
	75	writel(AT91_SMC_TIMINGS_TCLR(2) \| AT91_SMC_TIMINGS_TADL(7) \|
	76	AT91_SMC_TIMINGS_TAR(2) \| AT91_SMC_TIMINGS_TRR(3) \|
	77	AT91_SMC_TIMINGS_TWB(7) \| AT91_SMC_TIMINGS_RBNSEL(3)\|
	78	AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
	79	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	80	AT91_SMC_MODE_EXNW_DISABLE \|
	81	AT91_SMC_MODE_DBW_8 \|
	82	AT91_SMC_MODE_TDF_CYCLE(3),
	83	&smc->cs[3].mode);
	84
2dc63f73 WY	85	at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
	86	at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
	87	at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
	88	at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
	89	at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
	90	at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
	91	at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
	92	at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
	93	at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
	94	at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
	95	at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
	96	at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
	97	at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
	98	at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
927b901b BS	99	}
	100	#endif
	101
	102	#ifdef CONFIG_CMD_USB
	103	static void sama5d4ek_usb_hw_init(void)
	104	{
	105	at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
	106	at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
	107	at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
	108	}
	109	#endif
	110
	111	#ifdef CONFIG_LCD
	112	vidinfo_t panel_info = {
	113	.vl_col = 800,
	114	.vl_row = 480,
	115	.vl_clk = 33260000,
927b901b BS	116	.vl_bpix = LCD_BPP,
	117	.vl_tft = 1,
	118	.vl_hsync_len = 5,
	119	.vl_left_margin = 128,
	120	.vl_right_margin = 0,
	121	.vl_vsync_len = 5,
	122	.vl_upper_margin = 23,
	123	.vl_lower_margin = 22,
	124	.mmio = ATMEL_BASE_LCDC,
	125	};
	126
	127	/* No power up/down pin for the LCD pannel */
	128	void lcd_enable(void) { /* Empty! */ }
	129	void lcd_disable(void) { /* Empty! */ }
	130
	131	unsigned int has_lcdc(void)
	132	{
	133	return 1;
	134	}
	135
	136	static void sama5d4ek_lcd_hw_init(void)
	137	{
2dc63f73 WY	138	at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
	139	at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
	140	at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
	141	at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
	142	at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
	143	at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
	144
	145	at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
	146	at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
	147	at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
	148	at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
	149	at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
	150	at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
	151
	152	at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
	153	at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
	154	at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
	155	at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
	156	at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
	157	at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
	158
	159	at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
	160	at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
	161	at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
	162	at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
	163	at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
	164	at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
927b901b BS	165
	166	/* Enable clock */
	167	at91_periph_clk_enable(ATMEL_ID_LCDC);
	168	}
	169
	170	#ifdef CONFIG_LCD_INFO
	171	void lcd_show_board_info(void)
	172	{
	173	ulong dram_size, nand_size;
	174	int i;
	175	char temp[32];
	176
02fc64d1	177	lcd_printf("%s\n", U_BOOT_VERSION);
927b901b BS	178	lcd_printf("2014 ATMEL Corp\n");
	179	lcd_printf("at91@atmel.com\n");
	180	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
	181	strmhz(temp, get_cpu_clk_rate()));
	182
	183	dram_size = 0;
	184	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
	185	dram_size += gd->bd->bi_dram[i].size;
	186
	187	nand_size = 0;
	188	#ifdef CONFIG_NAND_ATMEL
	189	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
b616d9b0	190	nand_size += nand_info[i]->size;
927b901b BS	191	#endif
	192	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
	193	dram_size >> 20, nand_size >> 20);
	194	}
	195	#endif /* CONFIG_LCD_INFO */
	196
	197	#endif /* CONFIG_LCD */
	198
	199	#ifdef CONFIG_GENERIC_ATMEL_MCI
	200	void sama5d4ek_mci1_hw_init(void)
	201	{
2dc63f73 WY	202	at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
	203	at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
	204	at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
	205	at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
	206	at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
	207	at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
927b901b BS	208
	209	/*
	210	* As the mci io internal pull down is too strong, so if the io needs
	211	* external pull up, the pull up resistor will be very small, if so
	212	* the power consumption will increase, so disable the interanl pull
	213	* down to save the power.
	214	*/
2dc63f73 WY	215	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
	216	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
	217	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
	218	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
	219	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
	220	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
927b901b BS	221
	222	/* Enable clock */
	223	at91_periph_clk_enable(ATMEL_ID_MCI1);
	224	}
	225
	226	int board_mmc_init(bd_t *bis)
	227	{
	228	/* Enable power for MCI1 interface */
	229	at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
	230
	231	return atmel_mci_init((void *)ATMEL_BASE_MCI1);
	232	}
	233	#endif /* CONFIG_GENERIC_ATMEL_MCI */
	234
	235	#ifdef CONFIG_MACB
	236	void sama5d4ek_macb0_hw_init(void)
	237	{
2dc63f73 WY	238	at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
	239	at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
	240	at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
	241	at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
	242	at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
	243	at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
	244	at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
	245	at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
	246	at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
	247	at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
927b901b BS	248
	249	/* Enable clock */
	250	at91_periph_clk_enable(ATMEL_ID_GMAC0);
	251	}
	252	#endif
	253
	254	static void sama5d4ek_serial3_hw_init(void)
	255	{
2dc63f73 WY	256	at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
2dc63f73 WY	257	at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
927b901b BS	258
	259	/* Enable clock */
	260	at91_periph_clk_enable(ATMEL_ID_USART3);
	261	}
	262
	263	int board_early_init_f(void)
	264	{
	265	at91_periph_clk_enable(ATMEL_ID_PIOA);
	266	at91_periph_clk_enable(ATMEL_ID_PIOB);
	267	at91_periph_clk_enable(ATMEL_ID_PIOC);
	268	at91_periph_clk_enable(ATMEL_ID_PIOD);
	269	at91_periph_clk_enable(ATMEL_ID_PIOE);
	270
	271	sama5d4ek_serial3_hw_init();
	272
	273	return 0;
	274	}
	275
	276	int board_init(void)
	277	{
	278	/* adress of boot parameters */
	279	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	280
	281	#ifdef CONFIG_ATMEL_SPI
	282	sama5d4ek_spi0_hw_init();
	283	#endif
	284	#ifdef CONFIG_NAND_ATMEL
	285	sama5d4ek_nand_hw_init();
	286	#endif
	287	#ifdef CONFIG_GENERIC_ATMEL_MCI
	288	sama5d4ek_mci1_hw_init();
	289	#endif
	290	#ifdef CONFIG_MACB
	291	sama5d4ek_macb0_hw_init();
	292	#endif
	293	#ifdef CONFIG_LCD
	294	sama5d4ek_lcd_hw_init();
	295	#endif
	296	#ifdef CONFIG_CMD_USB
	297	sama5d4ek_usb_hw_init();
	298	#endif
da08d791 BS	299	#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	300	at91_udp_hw_init();
	301	#endif
927b901b BS	302
	303	return 0;
	304	}
	305
	306	int dram_init(void)
	307	{
	308	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
	309	CONFIG_SYS_SDRAM_SIZE);
	310	return 0;
	311	}
	312
	313	int board_eth_init(bd_t *bis)
	314	{
	315	int rc = 0;
	316
	317	#ifdef CONFIG_MACB
	318	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
	319	#endif
	320
da08d791 BS	321	#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	322	usba_udc_probe(&pdata);
	323	#ifdef CONFIG_USB_ETH_RNDIS
	324	usb_eth_initialize(bis);
	325	#endif
	326	#endif
	327
927b901b BS	328	return rc;
927b901b BS	329	}
5a4c9c22 BS	330
	331	/* SPL */
	332	#ifdef CONFIG_SPL_BUILD
	333	void spl_board_init(void)
	334	{
	335	#ifdef CONFIG_SYS_USE_MMC
	336	sama5d4ek_mci1_hw_init();
	337	#elif CONFIG_SYS_USE_NANDFLASH
	338	sama5d4ek_nand_hw_init();
	339	#elif CONFIG_SYS_USE_SERIALFLASH
	340	sama5d4ek_spi0_hw_init();
	341	#endif
	342	}
	343
7e8702a0	344	static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
5a4c9c22 BS	345	{
	346	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS \| ATMEL_MPDDRC_MD_DDR2_SDRAM);
	347
	348	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 \|
	349	ATMEL_MPDDRC_CR_NR_ROW_14 \|
	350	ATMEL_MPDDRC_CR_CAS_DDR_CAS3 \|
	351	ATMEL_MPDDRC_CR_NB_8BANKS \|
	352	ATMEL_MPDDRC_CR_NDQS_DISABLED \|
	353	ATMEL_MPDDRC_CR_DECOD_INTERLEAVED \|
	354	ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
	355
	356	ddr2->rtr = 0x2b0;
	357
	358	ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET \|
	359	3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \|
	360	3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET \|
	361	10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET \|
	362	3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET \|
	363	2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET \|
	364	2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET \|
	365	2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
	366
	367	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET \|
	368	200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET \|
	369	25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET \|
	370	23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
	371
	372	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET \|
	373	2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET \|
	374	3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET \|
	375	2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET \|
	376	8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
	377	}
	378
	379	void mem_init(void)
	380	{
7e8702a0	381	struct atmel_mpddrc_config ddr2;
5a4c9c22 BS	382
	383	ddr2_conf(&ddr2);
	384
70341e2e	385	/* Enable MPDDR clock */
5a4c9c22	386	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
70341e2e	387	at91_system_clk_enable(AT91_PMC_DDR);
5a4c9c22 BS	388
5a4c9c22 BS	389	/* DDRAM2 Controller initialize */
0c01c3e8	390	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
5a4c9c22 BS	391	}
	392
	393	void at91_pmc_init(void)
	394	{
5a4c9c22 BS	395	u32 tmp;
	396
	397	tmp = AT91_PMC_PLLAR_29 \|
	398	AT91_PMC_PLLXR_PLLCOUNT(0x3f) \|
	399	AT91_PMC_PLLXR_MUL(87) \|
	400	AT91_PMC_PLLXR_DIV(1);
	401	at91_plla_init(tmp);
	402
ede86ed2	403	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
5a4c9c22 BS	404
	405	tmp = AT91_PMC_MCKR_H32MXDIV \|
	406	AT91_PMC_MCKR_PLLADIV_2 \|
	407	AT91_PMC_MCKR_MDIV_3 \|
	408	AT91_PMC_MCKR_CSS_PLLA;
	409	at91_mck_init(tmp);
	410	}
	411	#endif