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* Code cleanup:
[people/ms/u-boot.git] / board / bmw / early_init.S
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afd7f3d0
WD		 1#include <ppc_asm.tmpl>
2#include <mpc824x.h>
3#include <ppc_defs.h>
4#include <asm/cache.h>
5#include <asm/mmu.h>
6
7#define USE_V2_INIT 1 /* Jimmy Blair's initialization. */
8
9
10/*
11 * Initialize the MMU using BAT entries and hardwired TLB
12 * This obviates the need for any code in cpu_init_f which
13 * configures the BAT registers.
14*/
15#define MEMORY_MGMT_MSR_BITS (MSR_DR | MSR_IR) /* Data and Inst Relocate */
16 .global iommu_setup
17 /* Initialize IO/MMU mappings via BAT method Ch. 7,
18 * PPC Programming Reference
8bde7f77 19 */
afd7f3d0
WD		 20iommu_setup:
21
22/* initialize the BAT registers (SPRs 528 - 543 */
23#define mtibat0u(x) mtspr 528,(x) /* SPR 528 (IBAT0U) */
24#define mtibat0l(x) mtspr 529,(x) /* SPR 529 (IBAT0L) */
25#define mtibat1u(x) mtspr 530,(x) /* SPR 530 (IBAT1U) */
26#define mtibat1l(x) mtspr 531,(x) /* SPR 531 (IBAT1L) */
27#define mtibat2u(x) mtspr 532,(x) /* SPR 532 (IBAT2U) */
28#define mtibat2l(x) mtspr 533,(x) /* SPR 533 (IBAT2L) */
29#define mtibat3u(x) mtspr 534,(x) /* SPR 534 (IBAT3U) */
30#define mtibat3l(x) mtspr 535,(x) /* SPR 535 (IBAT3L) */
31#define mtdbat0u(x) mtspr 536,(x) /* SPR 536 (DBAT0U) */
32#define mtdbat0l(x) mtspr 537,(x) /* SPR 537 (DBAT0L) */
33#define mtdbat1u(x) mtspr 538,(x) /* SPR 538 (DBAT1U) */
34#define mtdbat1l(x) mtspr 539,(x) /* SPR 539 (DBAT1L) */
35#define mtdbat2u(x) mtspr 540,(x) /* SPR 540 (DBAT2U) */
36#define mtdbat2l(x) mtspr 541,(x) /* SPR 541 (DBAT2L) */
37#define mtdbat3u(x) mtspr 542,(x) /* SPR 542 (DBAT3U) */
38#define mtdbat3l(x) mtspr 543,(x) /* SPR 543 (DBAT3L) */
39
40
41/* PowerPC processors do not necessarily initialize the BAT
42 registers on power-up or reset. So they are in an unknown
43 state. Before programming the BATs for the first time, all
44 BAT registers MUST have their Vs and Vp bits cleared in the
45 upper BAT half in order to avoid possibly having 2 BATs
46 valid and mapping the same memory region.
47
48 The reason for this is that, even with address translation
49 disabled, multiple BAT hits for an address are treated as
50 programming errors and can cause unpredictable results.
51
52 It is up to the software to make sure it never has 2 IBAT
53 mappings or 2 DBAT mappings that are valid for the same
54 addresses. It is not necessary to perform this code
55 sequence every time the BATs are programmed, only when
56 there is a possibility that there may be overlapping BAT
57 entries.
58
59 When programming the BATs in non-reset scenarios, even if
60 you are sure that your new mapping will not temporarily
61 create overlapping regions, it is still a wise idea to
62 invalidate a BAT entry by setting its upper BAT register to
63 all 0's before programming it. This will avoid having a
64 BAT marked valid that is in an unknown or transient state
65*/
66
8bde7f77 67 addis r5,0,0x0000
afd7f3d0
WD		 68 mtibat0u(r5)
69 mtibat0l(r5)
70 mtibat1u(r5)
71 mtibat1l(r5)
72 mtibat2u(r5)
73 mtibat2l(r5)
74 mtibat3u(r5)
75 mtibat3l(r5)
76 mtdbat0u(r5)
77 mtdbat0l(r5)
78 mtdbat1u(r5)
79 mtdbat1l(r5)
80 mtdbat2u(r5)
81 mtdbat2l(r5)
82 mtdbat3u(r5)
83 mtdbat3l(r5)
8bde7f77 84 isync
afd7f3d0
WD		 85
86/*
87 * Set up I/D BAT0
88 */
8bde7f77
WD		 89 lis r4, CFG_DBAT0L@h
90 ori r4, r4, CFG_DBAT0L@l
91 lis r3, CFG_DBAT0U@h
92 ori r3, r3, CFG_DBAT0U@l
93
94 mtdbat0l(r4)
95 isync
96 mtdbat0u(r3)
97 isync
98 sync
99
100 lis r4, CFG_IBAT0L@h
101 ori r4, r4, CFG_IBAT0L@l
102 lis r3, CFG_IBAT0U@h
103 ori r3, r3, CFG_IBAT0U@l
104
105 isync
106 mtibat0l(r4)
107 isync
afd7f3d0 108 mtibat0u(r3)
8bde7f77 109 isync
afd7f3d0
WD		 110
111/*
112 * Set up I/D BAT1
113 */
8bde7f77
WD		 114 lis r4, CFG_IBAT1L@h
115 ori r4, r4, CFG_IBAT1L@l
116 lis r3, CFG_IBAT1U@h
117 ori r3, r3, CFG_IBAT1U@l
118
119 isync
120 mtibat1l(r4)
121 isync
122 mtibat1u(r3)
123 isync
124 mtdbat1l(r4)
125 isync
126 mtdbat1u(r3)
127 isync
128 sync
afd7f3d0
WD		 129
130/*
131 * Set up I/D BAT2
132 */
8bde7f77
WD		 133 lis r4, CFG_IBAT2L@h
134 ori r4, r4, CFG_IBAT2L@l
135 lis r3, CFG_IBAT2U@h
136 ori r3, r3, CFG_IBAT2U@l
137
138 isync
139 mtibat2l(r4)
140 isync
141 mtibat2u(r3)
142 isync
143 mtdbat2l(r4)
144 isync
145 mtdbat2u(r3)
146 isync
147 sync
afd7f3d0
WD		 148
149/*
150 * Setup I/D BAT3
151 */
8bde7f77
WD		 152 lis r4, CFG_IBAT3L@h
153 ori r4, r4, CFG_IBAT3L@l
154 lis r3, CFG_IBAT3U@h
155 ori r3, r3, CFG_IBAT3U@l
156
157 isync
158 mtibat3l(r4)
159 isync
160 mtibat3u(r3)
161 isync
162 mtdbat3l(r4)
163 isync
164 mtdbat3u(r3)
165 isync
166 sync
afd7f3d0
WD		 167
168
169/*
170 * Invalidate all 64 TLB's
171 */
8bde7f77
WD		 172 lis r3, 0
173 mtctr r3
174 lis r5, 4
afd7f3d0
WD		 175
176tlblp:
8bde7f77
WD		 177 tlbie r3
178 sync
179 addi r3, r3, 0x1000
180 cmplw r3, r5
181 blt tlblp
afd7f3d0 182
8bde7f77 183 sync
afd7f3d0
WD		 184
185/*
186 * Enable Data Translation
187 */
188 lis r4, MEMORY_MGMT_MSR_BITS@h
189 ori r4, r4, MEMORY_MGMT_MSR_BITS@l
190 mfmsr r3
191 or r3, r4, r3
192 mtmsr r3
193 isync
194 sync
195
8bde7f77 196 blr
afd7f3d0
WD		 197
198
199#ifdef USE_V2_INIT
200/* #define USER_I_CACHE_ENABLE 1*/ /* Fast rom boots */
201/* Macro for hiadjust and lo */
202#define HIADJ(arg) arg@ha
203#define HI(arg) arg@h
204#define LO(arg) arg@l
205
206#undef LOADPTR
207#define LOADPTR(reg,const32) \
208 addis reg,r0,HIADJ(const32); addi reg,reg,LO(const32)
209
210.globl early_init_f
211
212early_init_f:
213/* MPC8245/BMW CPCI System Init
214 * Jimmy Blair, Broadcom Corp, 2002.
215 */
8bde7f77
WD		 216 mflr r11
217 /* Zero-out registers */
afd7f3d0
WD		 218
219 addis r0,r0,0
220 mtspr SPRG0,r0
221 mtspr SPRG1,r0
222 mtspr SPRG2,r0
223 mtspr SPRG3,r0
224
225 /* Set MPU/MSR to a known state. Turn on FP */
226
227 LOADPTR (r3, MSR_FP)
228 sync
229 mtmsr r3
230 isync
231
232 /* Init the floating point control/status register */
233
234 mtfsfi 7,0x0
235 mtfsfi 6,0x0
236 mtfsfi 5,0x0
237 mtfsfi 4,0x0
238 mtfsfi 3,0x0
239 mtfsfi 2,0x0
240 mtfsfi 1,0x0
241 mtfsfi 0,0x0
242 isync
243
244 /* Set MPU/MSR to a known state. Turn off FP */
245
246#if 1 /* Turn off floating point (remove to keep FP on) */
8bde7f77 247 andi. r3, r3, 0
afd7f3d0
WD		 248 sync
249 mtmsr r3
250 isync
251#endif
252
253 /* Init the Segment registers */
254
255 andi. r3, r3, 0
256 isync
257 mtsr 0,r3
258 isync
259 mtsr 1,r3
260 isync
261 mtsr 2,r3
262 isync
263 mtsr 3,r3
264 isync
265 mtsr 4,r3
266 isync
267 mtsr 5,r3
268 isync
269 mtsr 6,r3
270 isync
271 mtsr 7,r3
272 isync
273 mtsr 8,r3
274 isync
275 mtsr 9,r3
276 isync
277 mtsr 10,r3
278 isync
279 mtsr 11,r3
280 isync
281 mtsr 12,r3
282 isync
283 mtsr 13,r3
284 isync
285 mtsr 14,r3
286 isync
287 mtsr 15,r3
288 isync
289
290 /* Turn off data and instruction cache control bits */
291
292 mfspr r3, HID0
293 isync
294 rlwinm r4, r3, 0, 18, 15 /* r4 has ICE and DCE bits cleared */
295 sync
296 isync
297 mtspr HID0, r4 /* HID0 = r4 */
298 isync
299
300 /* Get cpu type */
301
302 mfspr r28, PVR
303 rlwinm r28, r28, 16, 16, 31
304
305 /* invalidate the MPU's data/instruction caches */
306
307 lis r3, 0x0
308 cmpli 0, 0, r28, CPU_TYPE_603
309 beq cpuIs603
310 cmpli 0, 0, r28, CPU_TYPE_603E
311 beq cpuIs603
312 cmpli 0, 0, r28, CPU_TYPE_603P
313 beq cpuIs603
314 cmpli 0, 0, r28, CPU_TYPE_604R
315 bne cpuNot604R
316
317cpuIs604R:
318 lis r3, 0x0
319 mtspr HID0, r3 /* disable the caches */
320 isync
321 ori r4, r4, 0x0002 /* disable BTAC by setting bit 30 */
322
323cpuNot604R:
324 ori r3, r3, (HID0_ICFI |HID0_DCI)
325
326cpuIs603:
327 ori r3, r3, (HID0_ICE | HID0_DCE)
328 or r4, r4, r3 /* set bits */
329 sync
330 isync
331 mtspr HID0, r4 /* HID0 = r4 */
332 andc r4, r4, r3 /* clear bits */
333 isync
334 cmpli 0, 0, r28, CPU_TYPE_604
335 beq cpuIs604
336 cmpli 0, 0, r28, CPU_TYPE_604E
337 beq cpuIs604
338 cmpli 0, 0, r28, CPU_TYPE_604R
339 beq cpuIs604
340 mtspr HID0, r4
341 isync
342
343#ifdef USER_I_CACHE_ENABLE
344 b instCacheOn603
345#else
346 b cacheEnableDone
347#endif
348
349cpuIs604:
350 LOADPTR (r5, 0x1000) /* loop count, 0x1000 */
351 mtspr CTR, r5
352loopDelay:
353 nop
354 bdnz loopDelay
355 isync
356 mtspr HID0, r4
357 isync
358
359 /* turn the Instruction cache ON for faster FLASH ROM boots */
360
361#ifdef USER_I_CACHE_ENABLE
362
363 ori r4, r4, (HID0_ICE | HID0_ICFI)
364 isync /* Synchronize for ICE enable */
365 b writeReg4
366instCacheOn603:
367 ori r4, r4, (HID0_ICE | HID0_ICFI)
368 rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */
369
370 /*
8bde7f77
WD		 371 * The setting of the instruction cache enable (ICE) bit must be
372 * preceded by an isync instruction to prevent the cache from being
373 * enabled or disabled while an instruction access is in progress.
374 */
afd7f3d0
WD		 375 isync
376writeReg4:
377 mtspr HID0, r4 /* Enable Instr Cache & Inval cache */
378 cmpli 0, 0, r28, CPU_TYPE_604
379 beq cacheEnableDone
380 cmpli 0, 0, r28, CPU_TYPE_604E
381 beq cacheEnableDone
382
383 mtspr HID0, r3 /* using 2 consec instructions */
384 /* PPC603 recommendation */
385#endif
386cacheEnableDone:
387
388 /* Detect map A or B */
389
390 addis r5,r0, HI(CHRP_REG_ADDR)
391 addis r6,r0, HI(CHRP_REG_DATA)
392 LOADPTR (r7, KAHLUA_ID) /* Kahlua PCI controller ID */
393 LOADPTR (r8, BMC_BASE)
394
395 stwbrx r8,0,(r5)
396 lwbrx r3,0,(r6) /* Store read value to r3 */
397 cmp 0,0,r3,r7
398 beq cr0, X4_KAHLUA_START
399
8bde7f77 400 /* It's not an 8240, is it an 8245? */
afd7f3d0
WD		 401
402 LOADPTR (r7, KAHLUA2_ID) /* Kahlua PCI controller ID */
403 cmp 0,0,r3,r7
404 beq cr0, X4_KAHLUA_START
405
8bde7f77 406 /* Save the PCI controller type in r7 */
afd7f3d0
WD		 407 mr r7, r3
408
409 LOADPTR (r5, PREP_REG_ADDR)
410 LOADPTR (r6, PREP_REG_DATA)
411
412X4_KAHLUA_START:
413 /* MPC8245 changes begin here */
414 LOADPTR (r3, MPC107_PCI_CMD) /* PCI command reg */
415 stwbrx r3,0,r5
416 li r4, 6 /* Command register value */
417 sthbrx r4, 0, r6
418
419 LOADPTR (r3, MPC107_PCI_STAT) /* PCI status reg */
420 stwbrx r3,0,r5
421 li r4, -1 /* Write-to-clear all bits */
422 li r3, 2 /* PCI_STATUS is at +2 offset */
423 sthbrx r4, r3, r6
424
425 /*-------PROC_INT1_ADR */
426
427 LOADPTR (r3, PROC_INT1_ADR) /* Processor I/F Config 1 reg. */
428 stwbrx r3,0,r5
429 LOADPTR (r4, 0xff141b98)
430 stwbrx r4,0,r6
431
432 /*-------PROC_INT2_ADR */
433
434 LOADPTR (r3, PROC_INT2_ADR) /* Processor I/F Config 2 reg. */
435 stwbrx r3,0,r5
8bde7f77 436 lis r4, 0x2000 /* Flush PCI config writes */
afd7f3d0
WD		 437 stwbrx r4,0,r6
438
439 LOADPTR (r9, KAHLUA2_ID)
8bde7f77
WD		 440 cmpl 0, 0, r7, r9
441 bne L1not8245
afd7f3d0 442
8bde7f77 443 /* MIOCR1 -- turn on bit for DLL delay */
afd7f3d0
WD		 444
445 LOADPTR (r3, MIOCR1_ADR_X)
446 stwbrx r3,0,r5
8bde7f77 447 li r4, 0x04
afd7f3d0
WD		 448 stb r4, MIOCR1_SHIFT(r6)
449
8bde7f77
WD		 450 /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
451 /* SDRAM_CLK_DEL (0x77)*/
afd7f3d0
WD		 452
453 LOADPTR (r3, MIOCR2_ADR_X)
454 stwbrx r3,0,r5
8bde7f77 455 li r4, 0x10
afd7f3d0
WD		 456 stb r4, MIOCR2_SHIFT(r6)
457
8bde7f77 458 /* PMCR2 -- set PCI hold delay to <10>b for 33 MHz */
afd7f3d0
WD		 459
460 LOADPTR (r3, PMCR2_ADR_X)
461 stwbrx r3,0,r5
8bde7f77 462 li r4, 0x20
afd7f3d0
WD		 463 stb r4, PMCR2_SHIFT(r6)
464
465 /* Initialize EUMBBAR early since 8245 has internal UART in EUMB */
466
467 LOADPTR (r3, EUMBBAR)
468 stwbrx r3,0,r5
469 LOADPTR (r4, CFG_EUMB_ADDR)
470 stwbrx r4,0,r6
471
472L1not8245:
473
8bde7f77 474 /* Toggle the DLL reset bit in AMBOR */
afd7f3d0
WD		 475
476 LOADPTR (r3, AMBOR)
477 stwbrx r3,0,r5
478 lbz r4, 0(r6)
479
8bde7f77 480 andi. r4, r4, 0xdf
afd7f3d0 481 stb r4, 0(r6) /* Clear DLL_RESET */
8bde7f77 482 sync
afd7f3d0 483
8bde7f77 484 ori r4, r4, 0x20 /* Set DLL_RESET */
afd7f3d0 485 stb r4, 0(r6)
8bde7f77 486 sync
afd7f3d0 487
8bde7f77 488 andi. r4, r4, 0xdf
afd7f3d0
WD		 489 stb r4, 0(r6) /* Clear DLL_RESET */
490
491
492 /* Enable RCS2, use supplied timings */
493 LOADPTR (r3, ERCR1)
494 stwbrx r3,0,r5
495 LOADPTR (r4, 0x80408000)
496 stwbrx r4,0,r6
497
498 /* Disable RCS3 parameters */
499 LOADPTR (r3, ERCR2)
500 stwbrx r3,0,r5
501 LOADPTR (r4, 0x00000000)
502 stwbrx r4,0,r6
503
504 /* RCS3 at 0x70000000, 64KBytes */
505 LOADPTR (r3, ERCR2)
506 stwbrx r3,0,r5
507 LOADPTR (r4, 0x00000004)
508 stwbrx r4,0,r6
509
510 /*-------MCCR1 */
511
512#ifdef INCLUDE_ECC
513#define MC_ECC 1
514#else /* INCLUDE_ECC */
515#define MC_ECC 0
516#endif /* INCLUDE_ECC */
517
518#define MC1_ROMNAL 8 /* 0-15 */
519#define MC1_ROMFAL 11 /* 0-31 */
520#define MC1_DBUS_SIZE 0 /* 0-3, read only */
521#define MC1_BURST 0 /* 0-1 */
522#define MC1_MEMGO 0 /* 0-1 */
523#define MC1_SREN 1 /* 0-1 */
524#define MC1_RAM_TYPE 0 /* 0-1 */
525#define MC1_PCKEN MC_ECC /* 0-1 */
526#define MC1_BANKBITS 0x5555 /* 2 bits/bank 7-0 */
527
528 LOADPTR (r3, MEM_CONT1_ADR) /* Set MCCR1 (F0) */
529 stwbrx r3,0,r5
530 LOADPTR(r4, \
531 MC1_ROMNAL << 28 | MC1_ROMFAL << 23 | \
532 MC1_DBUS_SIZE << 21 | MC1_BURST << 20 | \
533 MC1_MEMGO << 19 | MC1_SREN << 18 | \
534 MC1_RAM_TYPE << 17 | MC1_PCKEN << 16 )
535 li r3, MC1_BANKBITS
8bde7f77
WD		 536 cmpl 0, 0, r7, r9 /* Check for Kahlua2 */
537 bne BankBitsAdd
538 cmpli 0, 0, r3, 0x5555
539 beq K2BankBitsHack /* On 8245, 5555 ==> 0 */
afd7f3d0
WD		 540BankBitsAdd:
541 ori r4, r3, 0
542K2BankBitsHack:
543 stwbrx r4, 0, r6
544
545 /*------- MCCR2 */
546
547#define MC2_TS_WAIT_TIMER 0 /* 0-7 */
548#define MC2_ASRISE 8 /* 0-15 */
549#define MC2_ASFALL 4 /* 0-15 */
550#define MC2_INLINE_PAR_NOT_ECC 0 /* 0-1 */
551#define MC2_WRITE_PARITY_CHK_EN MC_ECC /* 0-1 */
552#define MC2_INLRD_PARECC_CHK_EN MC_ECC /* 0-1 */
553#define MC2_ECC_EN 0 /* 0-1 */
554#define MC2_EDO 0 /* 0-1 */
555/*
556* N.B. This refresh interval looks good up to 85 MHz with Hynix SDRAM.
557* May need to be decreased for 100 MHz
558*/
559#define MC2_REFINT 0x3a5 /* 0-0x3fff */
560#define MC2_RSV_PG 0 /* 0-1 */
561#define MC2_RMW_PAR MC_ECC /* 0-1 */
562
563 LOADPTR (r3, MEM_CONT2_ADR) /* Set MCCR2 (F4) */
564 stwbrx r3,0,r5
565 LOADPTR(r4, \
566 MC2_TS_WAIT_TIMER << 29 | MC2_ASRISE << 25 | \
567 MC2_ASFALL << 21 | MC2_INLINE_PAR_NOT_ECC << 20 | \
568 MC2_WRITE_PARITY_CHK_EN << 19 | \
569 MC2_INLRD_PARECC_CHK_EN << 18 | \
570 MC2_ECC_EN << 17 | MC2_EDO << 16 | \
571 MC2_REFINT << 2 | MC2_RSV_PG << 1 | MC2_RMW_PAR)
8bde7f77
WD		 572 cmpl 0, 0, r7, r9 /* Check for Kahlua2 */
573 bne notK2
574 /* clear Kahlua2 reserved bits */
afd7f3d0
WD		 575 LOADPTR (r3, 0xfffcffff)
576 and r4, r4, r3
577notK2:
578 stwbrx r4,0,r6
579
580 /*------- MCCR3 */
581
582#define MC_BSTOPRE 0x079 /* 0-0x7ff */
583
584#define MC3_BSTOPRE_U (MC_BSTOPRE >> 4 & 0xf)
585#define MC3_REFREC 8 /* 0-15 */
586#define MC3_RDLAT (4+MC_ECC) /* 0-15 */
587#define MC3_CPX 0 /* 0-1 */
588#define MC3_RAS6P 0 /* 0-15 */
589#define MC3_CAS5 0 /* 0-7 */
590#define MC3_CP4 0 /* 0-7 */
591#define MC3_CAS3 0 /* 0-7 */
592#define MC3_RCD2 0 /* 0-7 */
593#define MC3_RP1 0 /* 0-7 */
594
595 LOADPTR (r3, MEM_CONT3_ADR) /* Set MCCR3 (F8) */
596 stwbrx r3,0,r5
597 LOADPTR(r4, \
598 MC3_BSTOPRE_U << 28 | MC3_REFREC << 24 | \
599 MC3_RDLAT << 20 | MC3_CPX << 19 | \
600 MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \
601 MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1)
8bde7f77
WD		 602 cmpl 0, 0, r7, r9 /* Check for Kahlua2 */
603 bne notK2b
604 /* clear Kahlua2 reserved bits */
afd7f3d0
WD		 605 LOADPTR (r3, 0xff000000)
606 and r4, r4, r3
607notK2b:
608 stwbrx r4,0,r6
609
610 /*------- MCCR4 */
611
612#define MC4_PRETOACT 3 /* 0-15 */
613#define MC4_ACTOPRE 5 /* 0-15 */
614#define MC4_WMODE 0 /* 0-1 */
615#define MC4_INLINE MC_ECC /* 0-1 */
616#define MC4_REGISTERED (1-MC_ECC) /* 0-1 */
617#define MC4_BSTOPRE_UU (MC_BSTOPRE >> 8 & 3)
618#define MC4_REGDIMM 0 /* 0-1 */
619#define MC4_SDMODE_CAS 2 /* 0-7 */
620#define MC4_DBUS_RCS1 1 /* 0-1, 8-bit */
621#define MC4_SDMODE_WRAP 0 /* 0-1 */
622#define MC4_SDMODE_BURST 2 /* 0-7 */
623#define MC4_ACTORW 3 /* 0-15 */
624#define MC4_BSTOPRE_L (MC_BSTOPRE & 0xf)
625
626 LOADPTR (r3, MEM_CONT4_ADR) /* Set MCCR4 (FC) */
627 stwbrx r3,0,r5
628 LOADPTR(r4, \
629 MC4_PRETOACT << 28 | MC4_ACTOPRE << 24 | \
630 MC4_WMODE << 23 | MC4_INLINE << 22 | \
631 MC4_REGISTERED << 20 | MC4_BSTOPRE_UU << 18 | \
632 MC4_DBUS_RCS1 << 17 | \
633 MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \
634 MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \
635 MC4_ACTORW << 4 | MC4_BSTOPRE_L)
8bde7f77
WD		 636 cmpl 0, 0, r7, r9 /* Check for Kahlua 2 */
637 bne notK2c
638 /* Turn on Kahlua2 extended ROM space */
afd7f3d0
WD		 639 LOADPTR (r3, 0x00200000)
640 or r4, r4, r3
641notK2c:
642 stwbrx r4,0,r6
643
644#ifdef INCLUDE_ECC
645 /*------- MEM_ERREN1 */
646
647 LOADPTR (r3, MEM_ERREN1_ADR) /* Set MEM_ERREN1 (c0) */
648 stwbrx r3,0,r5
649 lwbrx r4,0,r6
650 ori r4,r4,4 /* Set MEM_PERR_EN */
651 stwbrx r4,0,r6
652#endif /* INCLUDE_ECC */
653
654 /*------- MSAR/MEAR */
655
656 LOADPTR (r3, MEM_START1_ADR) /* Set MSAR1 (80) */
657 stwbrx r3,0,r5
658 LOADPTR (r4, 0xc0804000)
659 stwbrx r4,0,r6
660
661 LOADPTR (r3, MEM_START2_ADR) /* Set MSAR2 (84) */
662 stwbrx r3,0,r5
663 LOADPTR (r4, 0xc0804000)
664 stwbrx r4,0,r6
665
666 LOADPTR (r3, XMEM_START1_ADR) /* Set MESAR1 (88) */
667 stwbrx r3,0,r5
668 LOADPTR (r4, 0x00000000)
669 stwbrx r4,0,r6
670
671 LOADPTR (r3, XMEM_START2_ADR) /* Set MESAR2 (8c) */
672 stwbrx r3,0,r5
673 LOADPTR (r4, 0x01010101)
674 stwbrx r4,0,r6
675
676 LOADPTR (r3, MEM_END1_ADR) /* Set MEAR1 (90) */
677 stwbrx r3,0,r5
678 LOADPTR (r4, 0xffbf7f3f)
679 stwbrx r4,0,r6
680
681 LOADPTR (r3, MEM_END2_ADR) /* Set MEAR2 (94) */
682 stwbrx r3,0,r5
683 LOADPTR (r4, 0xffbf7f3f)
684 stwbrx r4,0,r6
685
686 LOADPTR (r3, XMEM_END1_ADR) /* MEEAR1 (98) */
687 stwbrx r3,0,r5
688 LOADPTR (r4, 0x00000000)
689 stwbrx r4,0,r6
690
691 LOADPTR (r3, XMEM_END2_ADR) /* MEEAR2 (9c) */
692 stwbrx r3,0,r5
693 LOADPTR (r4, 0x01010101)
694 stwbrx r4,0,r6
695
696 /*-------ODCR */
697
698 LOADPTR (r3, ODCR_ADR_X) /* Set ODCR */
699 stwbrx r3,0,r5
700
701 li r4, 0x7f
702 stb r4, ODCR_SHIFT(r6) /* ODCR is at +3 offset */
703
704 /*-------MBEN */
705
706 LOADPTR (r3, MEM_EN_ADR) /* Set MBEN (a0) */
707 stwbrx r3,0,r5
708 li r4, 0x01 /* Enable bank 0 */
709 stb r4, 0(r6) /* MBEN is at +0 offset */
710
711#if 0 /* Jimmy: I think page made is broken */
712 /*-------PGMAX */
713
714 LOADPTR (r3, MPM_ADR_X)
715 stwbrx r3,0,r5
716 li r4, 0x32
717 stb r4, MPM_SHIFT(r6) /* PAGE_MODE is at +3 offset */
718#endif
719
720 /* Wait before initializing other registers */
721
722 lis r4,0x0001
723 mtctr r4
724
725KahluaX4wait200us:
726 bdnz KahluaX4wait200us
727
728 /* Set MEMGO bit */
729
730 LOADPTR (r3, MEM_CONT1_ADR) /* MCCR1 (F0) |= PGMAX */
731 stwbrx r3,0,r5
732 lwbrx r4,0,r6 /* old MCCR1 */
733 oris r4,r4,0x0008 /* MEMGO=1 */
734 stwbrx r4, 0, r6
735
736 /* Wait again */
737
738 addis r4,r0,0x0002
739 ori r4,r4,0xffff
740
741 mtctr r4
742
743KahluaX4wait8ref:
744 bdnz KahluaX4wait8ref
745
746 sync
747 eieio
8bde7f77 748 mtlr r11
afd7f3d0
WD		 749 blr
750
751#else /* USE_V2_INIT */
752
753
afd7f3d0
WD		 754/* U-Boot works, but memory will not run reliably for all address ranges.
755 * Early U-Boot Working init, but 2.4.19 kernel will crash since memory is not
756 * initialized correctly. Could work if debugged.
757 */
758/* PCI Support routines */
759
760 .globl __pci_config_read_32
761__pci_config_read_32:
762 lis r4, 0xfec0
763 stwbrx r3, r0, r4
764 sync
765 lis r4, 0xfee0
766 lwbrx r3, 0, r4
767 blr
768 .globl __pci_config_read_16
769__pci_config_read_16:
770 lis r4, 0xfec0
771 andi. r5, r3, 2
772 stwbrx r3, r0, r4
773 sync
774 oris r4, r5, 0xfee0
775 lhbrx r3, r0, r4
776 blr
777 .globl __pci_config_read_8
778__pci_config_read_8:
779 lis r4, 0xfec0
780 andi. r5, r3, 3
781 stwbrx r3, r0, r4
782 sync
783 oris r4, r5, 0xfee0
784 lbz r3, 0(4)
785 blr
786 .globl __pci_config_write_32
787__pci_config_write_32:
788 lis r5, 0xfec0
789 stwbrx r3, r0, r5
790 sync
791 lis r5, 0xfee0
792 stwbrx r4, r0, r5
793 sync
794 blr
795 .globl __pci_config_write_16
796__pci_config_write_16:
797 lis r5, 0xfec0
798 andi. r6, r3, 2
799 stwbrx r3, r0, 5
800 sync
801 oris r5, r6, 0xfee0
802 sthbrx r4, r0, r5
803 sync
804 blr
805 .globl __pci_config_write_8
806__pci_config_write_8:
807 lis r5, 0xfec0
808 andi. r6, r3, 3
809 stwbrx r3, r0, r5
810 sync
811 oris r5, r6, 0xfee0
812 stb r4, 0(r5)
813 sync
814 blr
815 .globl in_8
816in_8:
817 oris r3, r3, 0xfe00
818 lbz r3,0(r3)
819 blr
820 .globl in_16
821in_16:
822 oris r3, r3, 0xfe00
823 lhbrx r3, 0, r3
824 blr
825 .globl in_16_ne
826in_16_ne:
827 oris r3, r3, 0xfe00
828 lhzx r3, 0, r3
829 blr
830 .globl in_32
831in_32:
832 oris r3, r3, 0xfe00
833 lwbrx r3, 0, r3
834 blr
835 .globl out_8
836out_8:
837 oris r3, r3, 0xfe00
838 stb r4, 0(r3)
839 eieio
840 blr
841 .globl out_16
842out_16:
843 oris r3, r3, 0xfe00
844 sthbrx r4, 0, r3
845 eieio
846 blr
847 .globl out_16_ne
848out_16_ne:
849 oris r3, r3, 0xfe00
850 sth r4, 0(r3)
851 eieio
852 blr
853 .globl out_32
854out_32:
855 oris r3, r3, 0xfe00
856 stwbrx r4, 0, r3
857 eieio
858 blr
859 .globl read_8
860read_8:
861 lbz r3,0(r3)
862 blr
863 .globl read_16
864read_16:
865 lhbrx r3, 0, r3
866 blr
867 .globl read_32
868read_32:
869 lwbrx r3, 0, r3
870 blr
871 .globl read_32_ne
872read_32_ne:
873 lwz r3, 0(r3)
874 blr
875 .globl write_8
876write_8:
877 stb r4, 0(r3)
878 eieio
879 blr
880 .globl write_16
881write_16:
882 sthbrx r4, 0, r3
883 eieio
884 blr
885 .globl write_32
886write_32:
887 stwbrx r4, 0, r3
888 eieio
889 blr
890 .globl write_32_ne
891write_32_ne:
892 stw r4, 0(r3)
893 eieio
894 blr
895
896
897.globl early_init_f
898
899early_init_f:
8bde7f77
WD		 900 mflr r11
901 lis r10, 0x8000
afd7f3d0 902
8bde7f77
WD		 903 /* PCI Latency Timer */
904 li r4, 0x0d
905 ori r3, r10, PLTR@l
906 bl __pci_config_write_8
afd7f3d0 907
8bde7f77
WD		 908 /* Cache Line Size */
909 li r4, 0x08
910 ori r3, r10, PCLSR@l
911 bl __pci_config_write_8
afd7f3d0 912
8bde7f77
WD		 913 /* PCI Cmd */
914 li r4, 6
915 ori r3, r10, PCICR@l
916 bl __pci_config_write_16
afd7f3d0
WD		 917
918#if 1
8bde7f77
WD		 919 /* PCI Stat */
920 ori r3, r10, PCISR@l
921 bl __pci_config_read_16
922 ori r4, r4, 0xffff
923 ori r3, r10, PCISR@l
924 bl __pci_config_write_16
afd7f3d0
WD		 925#endif
926
8bde7f77
WD		 927 /* PICR1 */
928 lis r4, 0xff14
929 ori r4, r4, 0x1b98
930 ori r3, r10, PICR1@l
931 bl __pci_config_write_32
afd7f3d0
WD		 932
933
8bde7f77
WD		 934 /* PICR2 */
935 lis r4, 0x0404
936 ori r4, r4, 0x0004
937 ori r3, r10, PICR2@l
938 bl __pci_config_write_32
afd7f3d0
WD		 939
940 /* MIOCR1 */
8bde7f77
WD		 941 li r4, 0x04
942 ori r3, r10, MIOCR1@l
943 bl __pci_config_write_8
afd7f3d0
WD		 944
945 /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
946 /* SDRAM_CLK_DEL (0x77)*/
8bde7f77
WD		 947 li r4, 0x10
948 ori r3, r10, MIOCR2@l
949 bl __pci_config_write_8
afd7f3d0 950
8bde7f77
WD		 951 /* EUMBBAR */
952 lis r4, 0xfc00
953 ori r3, r10, EUMBBAR@l
954 bl __pci_config_write_32
afd7f3d0
WD		 955
956 /* AMBOR */
957
958 /* Even if Address Map B is not being used (though it should),
8bde7f77 959 * the memory DLL needs to be cleared/set/cleared before using memory.
afd7f3d0
WD		 960 */
961
8bde7f77
WD		 962 ori r3, r10, AMBOR@l
963 bl __pci_config_read_8 /* get Current bits */
afd7f3d0 964
8bde7f77
WD		 965 andi. r4, r4, 0xffdf
966 ori r3, r10, AMBOR@l
967 bl __pci_config_write_16 /* Clear DLL_RESET */
afd7f3d0 968
8bde7f77
WD		 969 ori r4, r4, 0x0020
970 ori r3, r10, AMBOR@l
971 bl __pci_config_write_16 /* Set DLL_RESET */
afd7f3d0 972
8bde7f77
WD		 973 andi. r4, r4, 0xffdf
974 ori r3, r10, AMBOR@l
975 bl __pci_config_write_16 /* Clear DLL_RESET */
afd7f3d0 976
8bde7f77
WD		 977 /* ERCR1 */
978 lis r4, 0x8040 /* Enable RCS2, use supplied timings */
979 ori r4, r4, 0x8000
980 ori r3, r10, ERCR1@l
981 bl __pci_config_write_32
afd7f3d0 982
8bde7f77
WD		 983 /* ERCR2 */
984 lis r4, 0x0000 /* Disable RCS3 parms */
985 ori r4, r4, 0x0000
986 ori r3, r10, ERCR2@l
987 bl __pci_config_write_32
afd7f3d0 988
8bde7f77
WD		 989 /* ERCR3 */
990 lis r4, 0x0000 /* RCS3 at 0x70000000, 64K bytes */
991 ori r4, r4, 0x0004
992 ori r3, r10, ERCR2@l
993 bl __pci_config_write_32
afd7f3d0
WD		 994
995 /* Preserve memgo bit */
8bde7f77 996 /* MCCR1 */
afd7f3d0
WD		 997
998/* lis r4, 0x75a8 / Safe Local ROM = 11+3 clocks */
8bde7f77 999 lis r4, 0x75a0 /* Safe Local ROM = 11+3 clocks */
afd7f3d0
WD		 1000/* lis r4, 0x73a0 / Fast Local ROM = 7+3 clocks */
1001/* oris r4, r4, 0x0010 / Burst ROM/Flash enable */
1002/* oris r4, r4, 0x0004 / Self-refresh enable */
1003
1004/* ori r4,r4,0xFFFF / 16Mbit 2bank SDRAM */
1005/* ori r4,r4,0xAAAA / 256Mbit 4bank SDRAM (8245 only) */
1006/* ori r4,r4,0x5555 / 64Mbit 2bank SDRAM */
8bde7f77 1007 ori r4,r4,0x0000 /* 64Mbit 4bank SDRAM */
afd7f3d0 1008
8bde7f77
WD		 1009 ori r3, r10, MCCR1@l
1010 bl __pci_config_write_32
afd7f3d0 1011
8bde7f77 1012 /* MCCR2 */
afd7f3d0 1013
8bde7f77 1014 lis r4,0x0000
afd7f3d0 1015/* oris r4,r4,0x4000 / TS_WAIT_TIMER = 3 clocks */
8bde7f77
WD		 1016 oris r4,r4,0x1000 /* ASRISE = 8 clocks */
1017 oris r4,r4,0x0080 /* ASFALL = 8 clocks */
afd7f3d0
WD		 1018/* oris r4,r4,0x0010 / SDRAM Parity (else ECC) */
1019/* oris r4,r4,0x0008 / Write parity check */
1020/* oris r4,r4,0x0004 / SDRAM inline reads */
1021
1022
1023/* Select a refresh rate; it needs to match the bus speed; if too */
1024/* slow, data may be lost; if too fast, performance is lost. We */
1025/* use the fastest value so we run at all speeds. */
1026/* Refresh = (15600ns/busclk) - (213 (see UM)). */
1027
1028/* ori r4,r4,0x1d2c / 133 MHz mem bus = 1867 */
1029/* ori r4,r4,0x150c / 100 MHz mem bus = 1347 */
1030/* ori r4,r4,0x10fc / 83 MHz mem bus = 1087 */
1031/* ori r4,r4,0x0cc4 / 66 MHz mem bus = 817 */
8bde7f77 1032 ori r4,r4,0x04cc /* 33 MHz mem bus (SAFE) = 307 */
afd7f3d0
WD		 1033/* ori r4,r4,0x0002 / Reserve a page */
1034/* ori r4,r4,0x0001 / RWM parity */
1035
8bde7f77
WD		 1036 ori r3, r10, MCCR2@l
1037 bl __pci_config_write_32
afd7f3d0
WD		 1038
1039
8bde7f77
WD		 1040 /* MCCR3 */
1041 lis r4,0x0000 /* BSTOPRE_M = 7 (see A/N) */
1042 oris r4,r4,0x0500 /* REFREC = 8 clocks */
1043 ori r3, r10, MCCR3@l
1044 bl __pci_config_write_32
afd7f3d0 1045
8bde7f77
WD		 1046 /* MCCR4 */ /* Turn on registered buffer mode */
1047 lis r4, 0x2000 /* PRETOACT = 3 clocks */
1048 oris r4,r4,0x0400 /* ACTOPRE = 5 clocks */
afd7f3d0
WD		 1049/* oris r4,r4,0x0080 / Enable 8-beat burst (32-bit bus) */
1050/* oris r4,r4,0x0040 / Enable Inline ECC/Parity */
8bde7f77
WD		 1051 oris r4,r4,0x0020 /* EXTROM enabled */
1052 oris r4,r4,0x0010 /* Registered buffers */
afd7f3d0 1053/* oris r4,r4,0x0000 / BSTOPRE_U = 0 (see A/N) */
8bde7f77 1054 oris r4,r4,0x0002 /* DBUS_SIZ[2] (8 bit on RCS1) */
afd7f3d0
WD		 1055
1056/* ori r4,r4,0x8000 / Registered DIMMs */
8bde7f77 1057 ori r4,r4,0x2000 /*CAS Latency (CL=3) (see RDLAT) */
afd7f3d0
WD		 1058/* ori r4,r4,0x2000 / CAS Latency (CL=2) (see RDLAT) */
1059/* ori r4,r4,0x0300 / Sequential wrap/8-beat burst */
8bde7f77
WD		 1060 ori r4,r4,0x0200 /* Sequential wrap/4-beat burst */
1061 ori r4,r4,0x0030 /* ACTORW = 3 clocks */
1062 ori r4,r4,0x0009 /* BSTOPRE_L = 9 (see A/N) */
afd7f3d0 1063
8bde7f77
WD		 1064 ori r3, r10, MCCR4@l
1065 bl __pci_config_write_32
afd7f3d0
WD		 1066
1067 /* MSAR1 */
8bde7f77
WD		 1068 lis r4, 0xc0804000@h
1069 ori r4, r4, 0xc0804000@l
1070 ori r3, r10, MSAR1@l
1071 bl __pci_config_write_32
afd7f3d0
WD		 1072
1073 /* MSAR2 */
8bde7f77
WD		 1074 lis r4, 0xc0804000@h
1075 ori r4, r4, 0xc0804000@l
1076 ori r3, r10, MSAR2@l
1077 bl __pci_config_write_32
afd7f3d0
WD		 1078
1079 /* MESAR1 */
8bde7f77
WD		 1080 lis r4, 0x00000000@h
1081 ori r4, r4, 0x00000000@l
1082 ori r3, r10, EMSAR1@l
1083 bl __pci_config_write_32
afd7f3d0
WD		 1084
1085 /* MESAR2 */
8bde7f77
WD		 1086 lis r4, 0x01010101@h
1087 ori r4, r4, 0x01010101@l
1088 ori r3, r10, EMSAR2@l
1089 bl __pci_config_write_32
afd7f3d0
WD		 1090
1091 /* MEAR1 */
8bde7f77
WD		 1092 lis r4, 0xffbf7f3f@h
1093 ori r4, r4, 0xffbf7f3f@l
1094 ori r3, r10, MEAR1@l
1095 bl __pci_config_write_32
afd7f3d0
WD		 1096
1097 /* MEAR2 */
8bde7f77
WD		 1098 lis r4, 0xffbf7f3f@h
1099 ori r4, r4, 0xffbf7f3f@l
1100 ori r3, r10, MEAR2@l
1101 bl __pci_config_write_32
afd7f3d0
WD		 1102
1103 /* MEEAR1 */
8bde7f77
WD		 1104 lis r4, 0x00000000@h
1105 ori r4, r4, 0x00000000@l
1106 ori r3, r10, EMEAR1@l
1107 bl __pci_config_write_32
afd7f3d0
WD		 1108
1109 /* MEEAR2 */
8bde7f77
WD		 1110 lis r4, 0x01010101@h
1111 ori r4, r4, 0x01010101@l
1112 ori r3, r10, EMEAR2@l
1113 bl __pci_config_write_32
afd7f3d0
WD		 1114
1115 /* ODCR */
8bde7f77
WD		 1116 li r4, 0x7f
1117 ori r3, r10, ODCR@l
1118 bl __pci_config_write_8
afd7f3d0
WD		 1119
1120 /* MBER */
8bde7f77
WD		 1121 li r4, 0x01
1122 ori r3, r10, MBER@l
1123 bl __pci_config_write_8
afd7f3d0 1124
8bde7f77
WD		 1125 /* Page CTR aka PGMAX */
1126 li r4, 0x32
1127 ori r3, r10, 0x70
1128 bl __pci_config_write_8
afd7f3d0
WD		 1129
1130#if 0
1131 /* CLK Drive */
8bde7f77
WD		 1132 ori r4, r10, 0xfc01 /* Top bit will be ignored */
1133 ori r3, r10, 0x74
1134 bl __pci_config_write_16
afd7f3d0
WD		 1135#endif
1136
1137 /* delay */
8bde7f77
WD		 1138 lis r7, 1
1139 mtctr r7
afd7f3d0
WD		 1140label1: bdnz label1
1141
8bde7f77
WD		 1142 /* Set memgo bit */
1143 /* MCCR1 */
1144 ori r3, r10, MCCR1@l
1145 bl __pci_config_read_32
1146 lis r7, 0x0008
1147 or r4, r3, r7
1148 ori r3, r10, MCCR1@l
1149 bl __pci_config_write_32
afd7f3d0
WD		 1150
1151 /* delay again */
8bde7f77
WD		 1152 lis r7, 1
1153 mtctr r7
afd7f3d0
WD		 1154label2: bdnz label2
1155#if 0
1156/* DEBUG: Infinite loop, write then read */
1157loop:
8bde7f77
WD		 1158 lis r7, 0xffff
1159 mtctr r7
1160 li r3, 0x5004
1161 lis r4, 0xa0a0
1162 ori r4, r4, 0x5050
afd7f3d0 1163 bl write_32_ne
8bde7f77 1164 li r3, 0x5004
afd7f3d0 1165 bl read_32_ne
8bde7f77 1166 bdnz loop
afd7f3d0 1167#endif
8bde7f77
WD		 1168 mtlr r11
1169 blr
afd7f3d0 1170#endif
"Das U-Boot" Source Tree