[people/ms/u-boot.git] / board / broadcom / bcmns2 / northstar2.c

/*
 * (C) Copyright 2016 Broadcom Ltd.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>

static struct mm_region ns2_mem_map[] = {
	{
		.virt = 0x0UL,
		.phys = 0x0UL,
		.size = 0x80000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE |
			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
	}, {
		.virt = 0x80000000UL,
		.phys = 0x80000000UL,
		.size = 0xff80000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
			 PTE_BLOCK_INNER_SHARE
	}, {
		/* List terminator */
		0,
	}
};

struct mm_region *mem_map = ns2_mem_map;

DECLARE_GLOBAL_DATA_PTR;

int board_init(void)
{
	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
				    PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE);
	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;

	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;

	return 0;
}

void reset_cpu(ulong addr)
{
	psci_system_reset();
}
Commit	Line	Data
274bced8 JM	1	/*
	2	* (C) Copyright 2016 Broadcom Ltd.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6	#include <common.h>
	7	#include <asm/system.h>
	8	#include <asm/armv8/mmu.h>
	9
	10	static struct mm_region ns2_mem_map[] = {
	11	{
	12	.virt = 0x0UL,
	13	.phys = 0x0UL,
	14	.size = 0x80000000UL,
	15	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	16	PTE_BLOCK_NON_SHARE \|
	17	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	18	}, {
	19	.virt = 0x80000000UL,
	20	.phys = 0x80000000UL,
	21	.size = 0xff80000000UL,
	22	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	23	PTE_BLOCK_INNER_SHARE
	24	}, {
	25	/* List terminator */
	26	0,
	27	}
	28	};
	29
	30	struct mm_region *mem_map = ns2_mem_map;
	31
	32	DECLARE_GLOBAL_DATA_PTR;
	33
	34	int board_init(void)
	35	{
	36	return 0;
	37	}
	38
	39	int dram_init(void)
	40	{
	41	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
	42	PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE);
	43	return 0;
	44	}
	45
76b00aca	46	int dram_init_banksize(void)
274bced8 JM	47	{
	48	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	49	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	50
	51	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
	52	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
76b00aca SG	53
76b00aca SG	54	return 0;
274bced8 JM	55	}
	56
	57	void reset_cpu(ulong addr)
	58	{
	59	psci_system_reset();
	60	}