[people/ms/u-boot.git] / board / cadence / xtfpga / xtfpga.c

/*
 * (C) Copyright 2007 - 2013 Tensilica Inc.
 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <dm/platdata.h>
#include <dm/platform_data/net_ethoc.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/stringify.h>
#include <asm/global_data.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * Check board idendity.
 * (Print information about the board to stdout.)
 */


#if defined(CONFIG_XTFPGA_LX60)
const char *board = "XT_AV60";
const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
#elif defined(CONFIG_XTFPGA_LX110)
const char *board = "XT_AV110";
const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / ";
#elif defined(CONFIG_XTFPGA_LX200)
const char *board = "XT_AV200";
const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / ";
#elif defined(CONFIG_XTFPGA_ML605)
const char *board = "XT_ML605";
const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / ";
#elif defined(CONFIG_XTFPGA_KC705)
const char *board = "XT_KC705";
const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / ";
#else
const char *board = "<unknown>";
const char *description = "";
#endif

int checkboard(void)
{
	printf("Board: %s: %sTensilica bitstream\n", board, description);
	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;

	return 0;
}

int board_postclk_init(void)
{
	/*
	 * Obtain CPU clock frequency from board and cache in global
	 * data structure (Hz). Return 0 on success (OK to continue),
	 * else non-zero (hang).
	 */

#ifdef CONFIG_SYS_FPGAREG_FREQ
	gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
#else
	/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
	gd->cpu_clk = 50000000UL;
#endif
	return 0;
}

/*
 *  Miscellaneous late initializations.
 *  The environment has been set up, so we can set the Ethernet address.
 */

int misc_init_r(void)
{
#ifdef CONFIG_CMD_NET
	/*
	 * Initialize ethernet environment variables and board info.
	 * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6.
	 */

	char *s = getenv("ethaddr");
	if (s == 0) {
		unsigned int x;
		char s[] = __stringify(CONFIG_ETHBASE);
		x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW)
			& FPGAREG_MAC_MASK;
		sprintf(&s[15], "%02x", x);
		setenv("ethaddr", s);
	}
#endif /* CONFIG_CMD_NET */

	return 0;
}

U_BOOT_DEVICE(sysreset) = {
	.name = "xtfpga_sysreset",
};

static struct ethoc_eth_pdata ethoc_pdata = {
	.eth_pdata = {
		.iobase = CONFIG_SYS_ETHOC_BASE,
	},
	.packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
};

U_BOOT_DEVICE(ethoc) = {
	.name = "ethoc",
	.platdata = &ethoc_pdata,
};
Commit	Line	Data
7e270ec3 CZ	1	/*
	2	* (C) Copyright 2007 - 2013 Tensilica Inc.
	3	* (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <command.h>
	10	#include <dm/platdata.h>
	11	#include <dm/platform_data/net_ethoc.h>
	12	#include <linux/ctype.h>
	13	#include <linux/string.h>
	14	#include <linux/stringify.h>
	15	#include <asm/global_data.h>
	16
	17	DECLARE_GLOBAL_DATA_PTR;
	18
	19	/*
	20	* Check board idendity.
	21	* (Print information about the board to stdout.)
	22	*/
	23
	24
	25	#if defined(CONFIG_XTFPGA_LX60)
	26	const char *board = "XT_AV60";
	27	const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
	28	#elif defined(CONFIG_XTFPGA_LX110)
	29	const char *board = "XT_AV110";
	30	const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / ";
	31	#elif defined(CONFIG_XTFPGA_LX200)
	32	const char *board = "XT_AV200";
	33	const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / ";
	34	#elif defined(CONFIG_XTFPGA_ML605)
	35	const char *board = "XT_ML605";
	36	const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / ";
	37	#elif defined(CONFIG_XTFPGA_KC705)
	38	const char *board = "XT_KC705";
	39	const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / ";
	40	#else
	41	const char *board = "<unknown>";
	42	const char *description = "";
	43	#endif
	44
	45	int checkboard(void)
	46	{
	47	printf("Board: %s: %sTensilica bitstream\n", board, description);
	48	return 0;
	49	}
	50
76b00aca	51	int dram_init_banksize(void)
7e270ec3 CZ	52	{
	53	gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
	54	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
76b00aca SG	55
76b00aca SG	56	return 0;
7e270ec3 CZ	57	}
	58
	59	int board_postclk_init(void)
	60	{
	61	/*
	62	* Obtain CPU clock frequency from board and cache in global
	63	* data structure (Hz). Return 0 on success (OK to continue),
	64	* else non-zero (hang).
	65	*/
	66
	67	#ifdef CONFIG_SYS_FPGAREG_FREQ
	68	gd->cpu_clk = ((volatile unsigned long )CONFIG_SYS_FPGAREG_FREQ);
	69	#else
	70	/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
	71	gd->cpu_clk = 50000000UL;
	72	#endif
	73	return 0;
	74	}
	75
	76	/*
	77	* Miscellaneous late initializations.
	78	* The environment has been set up, so we can set the Ethernet address.
	79	*/
	80
	81	int misc_init_r(void)
	82	{
	83	#ifdef CONFIG_CMD_NET
	84	/*
	85	* Initialize ethernet environment variables and board info.
	86	* Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6.
	87	*/
	88
	89	char *s = getenv("ethaddr");
	90	if (s == 0) {
	91	unsigned int x;
	92	char s[] = __stringify(CONFIG_ETHBASE);
	93	x = ((volatile u32 )CONFIG_SYS_FPGAREG_DIPSW)
	94	& FPGAREG_MAC_MASK;
	95	sprintf(&s[15], "%02x", x);
	96	setenv("ethaddr", s);
	97	}
	98	#endif /* CONFIG_CMD_NET */
	99
	100	return 0;
	101	}
	102
	103	U_BOOT_DEVICE(sysreset) = {
	104	.name = "xtfpga_sysreset",
	105	};
	106
	107	static struct ethoc_eth_pdata ethoc_pdata = {
	108	.eth_pdata = {
	109	.iobase = CONFIG_SYS_ETHOC_BASE,
	110	},
	111	.packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
	112	};
	113
	114	U_BOOT_DEVICE(ethoc) = {
	115	.name = "ethoc",
	116	.platdata = &ethoc_pdata,
	117	};