[people/ms/u-boot.git] / board / chromebook-x86 / dts / link.dts

/dts-v1/;

/include/ ARCH_CPU_DTS

/ {
        #address-cells = <1>;
        #size-cells = <1>;
	model = "Google Link";
	compatible = "google,link", "intel,celeron-ivybridge";

	config {
	       silent_console = <0>;
	};

        gpio: gpio {};

	serial {
		reg = <0x3f8 8>;
		clock-frequency = <115200>;
	};

        chosen { };
        memory { device_type = "memory"; reg = <0 0>; };

	spi {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "intel,ich9";
		spi-flash@0 {
			reg = <0>;
			compatible = "winbond,w25q64", "spi-flash";
			memory-map = <0xff800000 0x00800000>;
		};
	};
};
Commit	Line	Data
2712f088 SG	1	/dts-v1/;
2712f088 SG	2
26f7621d	3	/include/ ARCH_CPU_DTS
2712f088 SG	4
	5	/ {
	6	#address-cells = <1>;
	7	#size-cells = <1>;
	8	model = "Google Link";
	9	compatible = "google,link", "intel,celeron-ivybridge";
	10
	11	config {
	12	silent_console = <0>;
	13	};
	14
	15	gpio: gpio {};
	16
	17	serial {
	18	reg = <0x3f8 8>;
	19	clock-frequency = <115200>;
	20	};
	21
	22	chosen { };
	23	memory { device_type = "memory"; reg = <0 0>; };
7ea01d18 SG	24
	25	spi {
	26	#address-cells = <1>;
	27	#size-cells = <0>;
	28	compatible = "intel,ich9";
	29	spi-flash@0 {
	30	reg = <0>;
	31	compatible = "winbond,w25q64", "spi-flash";
	32	memory-map = <0xff800000 0x00800000>;
	33	};
	34	};
2712f088	35	};