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1/*
2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
5b8031cc 7 * SPDX-License-Identifier: GPL-2.0
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8 */
9
10#include <common.h>
11#include <asm/io.h>
150c2493 12#include <asm/arch/tegra.h>
2996e2dc 13#include <asm/arch/pinmux.h>
2996e2dc 14#include <asm/gpio.h>
2996e2dc 15
1e2d7859 16#ifdef CONFIG_TEGRA_MMC
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17/*
18 * Routine: pin_mux_mmc
19 * Description: setup the pin muxes/tristate values for the SDMMC(s)
20 */
c9aa831e 21void pin_mux_mmc(void)
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22{
23 /* SDMMC4: config 3, x8 on 2nd set of pins */
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24 pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
25 pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
26 pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
2996e2dc 27
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28 pinmux_tristate_disable(PMUX_PINGRP_ATB);
29 pinmux_tristate_disable(PMUX_PINGRP_GMA);
30 pinmux_tristate_disable(PMUX_PINGRP_GME);
2996e2dc 31
ffec1eb9 32 /* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
70ad375e 33 pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
2996e2dc 34
70ad375e 35 pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
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36
37 /* For power GPIO PV1 */
70ad375e 38 pinmux_tristate_disable(PMUX_PINGRP_UAC);
aa53c7f5 39 /* For CD GPIO PV5 */
70ad375e 40 pinmux_tristate_disable(PMUX_PINGRP_GPV);
2996e2dc 41}
2996e2dc 42#endif
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43
44#ifdef CONFIG_LCD
45/* this is a weak define that we are overriding */
46void pin_mux_display(void)
47{
48 debug("init display pinmux\n");
49
50 /* EN_VDD_PANEL GPIO A4 */
70ad375e 51 pinmux_tristate_disable(PMUX_PINGRP_DAP2);
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52}
53#endif