[people/ms/u-boot.git] / board / compulab / cm_t43 / cm_t43.c

/*
 * Copyright (C) 2015 Compulab, Ltd.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/emif.h>
#include <power/pmic.h>
#include <power/tps65218.h>
#include "board.h"
#include <usb.h>
#include <asm/omap_common.h>

DECLARE_GLOBAL_DATA_PTR;

static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

/* setup board specific PMIC */
int power_init_board(void)
{
	struct pmic *p;
	uchar tps_status = 0;

	power_tps65218_init(I2C_PMIC);
	p = pmic_get("TPS65218_PMIC");
	if (p && !pmic_probe(p)) {
		puts("PMIC:  TPS65218\n");
		/* We don't care if fseal is locked, but we do need it set */
		tps65218_lock_fseal();
		tps65218_reg_read(TPS65218_STATUS, &tps_status);
		if (!(tps_status & TPS65218_FSEAL))
			printf("WARNING: RTC not backed by battery!\n");
	}

	return 0;
}

int board_init(void)
{
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	gpmc_init();
	set_i2c_pin_mux();
	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
	i2c_probe(TPS65218_CHIP_PM);

	return 0;
}

int board_usb_init(int index, enum usb_init_type init)
{
	enable_usb_clocks(index);
	return 0;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	disable_usb_clocks(index);
	return 0;
}

#ifdef CONFIG_DRIVER_TI_CPSW

static void cpsw_control(int enabled)
{
	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 0,
		.phy_if		= PHY_INTERFACE_MODE_RGMII,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs	= 0xdc0,
		.phy_addr	= 1,
		.phy_if		= PHY_INTERFACE_MODE_RGMII,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 2,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};

#define GPIO_PHY1_RST		170
#define GPIO_PHY2_RST		168

int board_phy_config(struct phy_device *phydev)
{
	unsigned short val;

	/* introduce tx clock delay */
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	val |= 0x0100;
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);

	if (phydev->drv->config)
		return phydev->drv->config(phydev);

	return 0;
}

static void board_phy_init(void)
{
	set_mdio_pin_mux();
	writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
	writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
	writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */

	/* For revision A */
	writel(0x2000009, 0x44df2e6c);
	writel(0x38a, 0x44df2e70);

	mdelay(10);

	gpio_request(GPIO_PHY1_RST, "phy1_rst");
	gpio_request(GPIO_PHY2_RST, "phy2_rst");
	gpio_direction_output(GPIO_PHY1_RST, 0);
	gpio_direction_output(GPIO_PHY2_RST, 0);
	mdelay(2);

	gpio_set_value(GPIO_PHY1_RST, 1);
	gpio_set_value(GPIO_PHY2_RST, 1);
	mdelay(2);
}

int board_eth_init(bd_t *bis)
{
	int rv;

	set_rgmii_pin_mux();
	writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
	board_phy_init();

	rv = cpsw_register(&cpsw_data);
	if (rv < 0)
		printf("Error %d registering CPSW switch\n", rv);

	return rv;
}
#endif
Commit	Line	Data
5dc5a8ca NK	1	/*
	2	* Copyright (C) 2015 Compulab, Ltd.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <i2c.h>
	9	#include <miiphy.h>
	10	#include <cpsw.h>
	11	#include <asm/gpio.h>
	12	#include <asm/arch/sys_proto.h>
	13	#include <asm/emif.h>
	14	#include <power/pmic.h>
	15	#include <power/tps65218.h>
	16	#include "board.h"
b16c129c FA	17	#include <usb.h>
b16c129c FA	18	#include <asm/omap_common.h>
5dc5a8ca NK	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
	22	static struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
	23
	24	/* setup board specific PMIC */
	25	int power_init_board(void)
	26	{
	27	struct pmic *p;
dccaaaeb	28	uchar tps_status = 0;
5dc5a8ca NK	29
	30	power_tps65218_init(I2C_PMIC);
	31	p = pmic_get("TPS65218_PMIC");
dccaaaeb	32	if (p && !pmic_probe(p)) {
5dc5a8ca	33	puts("PMIC: TPS65218\n");
dccaaaeb NK	34	/* We don't care if fseal is locked, but we do need it set */
	35	tps65218_lock_fseal();
	36	tps65218_reg_read(TPS65218_STATUS, &tps_status);
	37	if (!(tps_status & TPS65218_FSEAL))
	38	printf("WARNING: RTC not backed by battery!\n");
	39	}
5dc5a8ca NK	40
	41	return 0;
	42	}
	43
	44	int board_init(void)
	45	{
	46	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	47	gpmc_init();
	48	set_i2c_pin_mux();
	49	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
	50	i2c_probe(TPS65218_CHIP_PM);
	51
	52	return 0;
	53	}
	54
b16c129c FA	55	int board_usb_init(int index, enum usb_init_type init)
	56	{
	57	enable_usb_clocks(index);
	58	return 0;
	59	}
	60
	61	int board_usb_cleanup(int index, enum usb_init_type init)
	62	{
	63	disable_usb_clocks(index);
	64	return 0;
	65	}
	66
5dc5a8ca NK	67	#ifdef CONFIG_DRIVER_TI_CPSW
	68
	69	static void cpsw_control(int enabled)
	70	{
	71	return;
	72	}
	73
	74	static struct cpsw_slave_data cpsw_slaves[] = {
	75	{
	76	.slave_reg_ofs = 0x208,
	77	.sliver_reg_ofs = 0xd80,
	78	.phy_addr = 0,
	79	.phy_if = PHY_INTERFACE_MODE_RGMII,
	80	},
	81	{
	82	.slave_reg_ofs = 0x308,
	83	.sliver_reg_ofs = 0xdc0,
	84	.phy_addr = 1,
	85	.phy_if = PHY_INTERFACE_MODE_RGMII,
	86	},
	87	};
	88
	89	static struct cpsw_platform_data cpsw_data = {
	90	.mdio_base = CPSW_MDIO_BASE,
	91	.cpsw_base = CPSW_BASE,
	92	.mdio_div = 0xff,
	93	.channels = 8,
	94	.cpdma_reg_ofs = 0x800,
	95	.slaves = 2,
	96	.slave_data = cpsw_slaves,
	97	.ale_reg_ofs = 0xd00,
	98	.ale_entries = 1024,
	99	.host_port_reg_ofs = 0x108,
	100	.hw_stats_reg_ofs = 0x900,
	101	.bd_ram_ofs = 0x2000,
	102	.mac_control = (1 << 5),
	103	.control = cpsw_control,
	104	.host_port_num = 0,
	105	.version = CPSW_CTRL_VERSION_2,
	106	};
	107
	108	#define GPIO_PHY1_RST 170
	109	#define GPIO_PHY2_RST 168
	110
	111	int board_phy_config(struct phy_device *phydev)
	112	{
	113	unsigned short val;
	114
	115	/* introduce tx clock delay */
	116	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	117	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	118	val \|= 0x0100;
	119	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
	120
	121	if (phydev->drv->config)
	122	return phydev->drv->config(phydev);
	123
	124	return 0;
	125	}
	126
	127	static void board_phy_init(void)
	128	{
	129	set_mdio_pin_mux();
	130	writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
131	writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
132	writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
133
134	/* For revision A */
135	writel(0x2000009, 0x44df2e6c);
136	writel(0x38a, 0x44df2e70);
137
138	mdelay(10);
139
140	gpio_request(GPIO_PHY1_RST, "phy1_rst");
141	gpio_request(GPIO_PHY2_RST, "phy2_rst");
142	gpio_direction_output(GPIO_PHY1_RST, 0);
143	gpio_direction_output(GPIO_PHY2_RST, 0);
144	mdelay(2);
145
146	gpio_set_value(GPIO_PHY1_RST, 1);
147	gpio_set_value(GPIO_PHY2_RST, 1);
148	mdelay(2);
149	}
150
151	int board_eth_init(bd_t *bis)
152	{
153	int rv;
154
155	set_rgmii_pin_mux();
156	writel(RGMII_MODE_ENABLE \| RGMII_INT_DELAY, &cdev->miisel);
157	board_phy_init();
158
159	rv = cpsw_register(&cpsw_data);
160	if (rv < 0)
161	printf("Error %d registering CPSW switch\n", rv);
162
163	return rv;
164	}
165	#endif