[people/ms/u-boot.git] / board / compulab / common / omap3_display.c

/*
 * (C) Copyright 2012 - 2013 CompuLab, Ltd. <www.compulab.co.il>
 *
 * Authors: Nikita Kiryanov <nikita@compulab.co.il>
 *
 * Parsing code based on linux/drivers/video/pxafb.c
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <stdio_dev.h>
#include <asm/arch/dss.h>
#include <lcd.h>
#include <scf0403_lcd.h>
#include <asm/arch-omap3/dss.h>

DECLARE_GLOBAL_DATA_PTR;

enum display_type {
	NONE,
	DVI,
	DVI_CUSTOM,
	DATA_IMAGE, /* #define CONFIG_SCF0403_LCD to use */
};

#define CMAP_ADDR	0x80100000

/*
 * The frame buffer is allocated before we have the chance to parse user input.
 * To make sure enough memory is allocated for all resolutions, we define
 * vl_{col | row} to the maximal resolution supported by OMAP3.
 */
vidinfo_t panel_info = {
	.vl_col  = 1400,
	.vl_row  = 1050,
	.vl_bpix = LCD_BPP,
	.cmap = (ushort *)CMAP_ADDR,
};

static struct panel_config panel_cfg;
static enum display_type lcd_def;

/*
 * A note on DVI presets;
 * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can
 * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to
 * support two BMP types with one setting.
 */
static const struct panel_config preset_dvi_640X480 = {
	.lcd_size	= PANEL_LCD_SIZE(640, 480),
	.timing_h	= DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96),
	.timing_v	= DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2),
	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
	.divisor	= 12 | (1 << 16),
	.data_lines	= LCD_INTERFACE_24_BIT,
	.panel_type	= ACTIVE_DISPLAY,
	.load_mode	= 2,
	.gfx_format	= GFXFORMAT_RGB16,
};

static const struct panel_config preset_dvi_800X600 = {
	.lcd_size	= PANEL_LCD_SIZE(800, 600),
	.timing_h	= DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128),
	.timing_v	= DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4),
	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
	.divisor	= 8 | (1 << 16),
	.data_lines	= LCD_INTERFACE_24_BIT,
	.panel_type	= ACTIVE_DISPLAY,
	.load_mode	= 2,
	.gfx_format	= GFXFORMAT_RGB16,
};

static const struct panel_config preset_dvi_1024X768 = {
	.lcd_size	= PANEL_LCD_SIZE(1024, 768),
	.timing_h	= DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136),
	.timing_v	= DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6),
	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
	.divisor	= 5 | (1 << 16),
	.data_lines	= LCD_INTERFACE_24_BIT,
	.panel_type	= ACTIVE_DISPLAY,
	.load_mode	= 2,
	.gfx_format	= GFXFORMAT_RGB16,
};

static const struct panel_config preset_dvi_1152X864 = {
	.lcd_size	= PANEL_LCD_SIZE(1152, 864),
	.timing_h	= DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128),
	.timing_v	= DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3),
	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
	.divisor	= 4 | (1 << 16),
	.data_lines	= LCD_INTERFACE_24_BIT,
	.panel_type	= ACTIVE_DISPLAY,
	.load_mode	= 2,
	.gfx_format	= GFXFORMAT_RGB16,
};

static const struct panel_config preset_dvi_1280X960 = {
	.lcd_size	= PANEL_LCD_SIZE(1280, 960),
	.timing_h	= DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112),
	.timing_v	= DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3),
	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
	.divisor	= 3 | (1 << 16),
	.data_lines	= LCD_INTERFACE_24_BIT,
	.panel_type	= ACTIVE_DISPLAY,
	.load_mode	= 2,
	.gfx_format	= GFXFORMAT_RGB16,
};

static const struct panel_config preset_dvi_1280X1024 = {
	.lcd_size	= PANEL_LCD_SIZE(1280, 1024),
	.timing_h	= DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112),
	.timing_v	= DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3),
	.pol_freq	= DSS_IHS | DSS_IVS | DSS_IPC,
	.divisor	= 3 | (1 << 16),
	.data_lines	= LCD_INTERFACE_24_BIT,
	.panel_type	= ACTIVE_DISPLAY,
	.load_mode	= 2,
	.gfx_format	= GFXFORMAT_RGB16,
};

static const struct panel_config preset_dataimage_480X800 = {
	.lcd_size	= PANEL_LCD_SIZE(480, 800),
	.timing_h	= DSS_HBP(2) | DSS_HFP(2) | DSS_HSW(2),
	.timing_v	= DSS_VBP(17) | DSS_VFP(20) | DSS_VSW(3),
	.pol_freq	= DSS_IVS | DSS_IHS | DSS_IPC | DSS_ONOFF,
	.divisor	= 10 | (1 << 10),
	.data_lines	= LCD_INTERFACE_18_BIT,
	.panel_type	= ACTIVE_DISPLAY,
	.load_mode	= 2,
	.gfx_format	= GFXFORMAT_RGB16,
};

/*
 * set_resolution_params()
 *
 * Due to usage of multiple display related APIs resolution data is located in
 * more than one place. This function updates them all.
 */
static void set_resolution_params(int x, int y)
{
	panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y);
	panel_info.vl_col = x;
	panel_info.vl_row = y;
	lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
}

static void set_preset(const struct panel_config preset, int x_res, int y_res)
{
	panel_cfg = preset;
	set_resolution_params(x_res, y_res);
}

static enum display_type set_dvi_preset(const struct panel_config preset,
					int x_res, int y_res)
{
	set_preset(preset, x_res, y_res);
	return DVI;
}

static enum display_type set_dataimage_preset(const struct panel_config preset,
		int x_res, int y_res)
{
	set_preset(preset, x_res, y_res);
	return DATA_IMAGE;
}

/*
 * parse_mode() - parse the mode parameter of custom lcd settings
 *
 * @mode:	<res_x>x<res_y>
 *
 * Returns -1 on error, 0 on success.
 */
static int parse_mode(const char *mode)
{
	unsigned int modelen = strlen(mode);
	int res_specified = 0;
	unsigned int xres = 0, yres = 0;
	int yres_specified = 0;
	int i;

	for (i = modelen - 1; i >= 0; i--) {
		switch (mode[i]) {
		case 'x':
			if (!yres_specified) {
				yres = simple_strtoul(&mode[i + 1], NULL, 0);
				yres_specified = 1;
			} else {
				goto done_parsing;
			}

			break;
		case '0' ... '9':
			break;
		default:
			goto done_parsing;
		}
	}

	if (i < 0 && yres_specified) {
		xres = simple_strtoul(mode, NULL, 0);
		res_specified = 1;
	}

done_parsing:
	if (res_specified) {
		set_resolution_params(xres, yres);
	} else {
		printf("LCD: invalid mode: %s\n", mode);
		return -1;
	}

	return 0;
}

#define PIXEL_CLK_NUMERATOR (26 * 432 / 39)
/*
 * parse_pixclock() - Parse the pixclock parameter of custom lcd settings
 *
 * @pixclock:	the desired pixel clock
 *
 * Returns -1 on error, 0 on success.
 *
 * Handling the pixel_clock:
 *
 * Pixel clock is defined in the OMAP35x TRM as follows:
 * pixel_clock =
 * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) /
 * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] *
 * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1))
 *
 * In practice, this means that in order to set the
 * divisor for the desired pixel clock one needs to
 * solve the following equation:
 *
 * 26 * 432 / (39 * <pixel_clock>) = DSS.DISPC_DIVISOR[6:0]
 *
 * NOTE: the explicit equation above is reduced. Do not
 * try to infer anything from these numbers.
 */
static int parse_pixclock(char *pixclock)
{
	int divisor, pixclock_val;
	char *pixclk_start = pixclock;

	pixclock_val = simple_strtoul(pixclock, &pixclock, 10);
	divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val);
	/* 0 and 1 are illegal values for PCD */
	if (divisor <= 1)
		divisor = 2;

	panel_cfg.divisor = divisor | (1 << 16);
	if (pixclock[0] != '\0') {
		printf("LCD: invalid value for pixclock:%s\n", pixclk_start);
		return -1;
	}

	return 0;
}

/*
 * parse_setting() - parse a single setting of custom lcd parameters
 *
 * @setting:	The custom lcd setting <name>:<value>
 *
 * Returns -1 on failure, 0 on success.
 */
static int parse_setting(char *setting)
{
	int num_val;
	char *setting_start = setting;

	if (!strncmp(setting, "mode:", 5)) {
		return parse_mode(setting + 5);
	} else if (!strncmp(setting, "pixclock:", 9)) {
		return parse_pixclock(setting + 9);
	} else if (!strncmp(setting, "left:", 5)) {
		num_val = simple_strtoul(setting + 5, &setting, 0);
		panel_cfg.timing_h |= DSS_HBP(num_val);
	} else if (!strncmp(setting, "right:", 6)) {
		num_val = simple_strtoul(setting + 6, &setting, 0);
		panel_cfg.timing_h |= DSS_HFP(num_val);
	} else if (!strncmp(setting, "upper:", 6)) {
		num_val = simple_strtoul(setting + 6, &setting, 0);
		panel_cfg.timing_v |= DSS_VBP(num_val);
	} else if (!strncmp(setting, "lower:", 6)) {
		num_val = simple_strtoul(setting + 6, &setting, 0);
		panel_cfg.timing_v |= DSS_VFP(num_val);
	} else if (!strncmp(setting, "hsynclen:", 9)) {
		num_val = simple_strtoul(setting + 9, &setting, 0);
		panel_cfg.timing_h |= DSS_HSW(num_val);
	} else if (!strncmp(setting, "vsynclen:", 9)) {
		num_val = simple_strtoul(setting + 9, &setting, 0);
		panel_cfg.timing_v |= DSS_VSW(num_val);
	} else if (!strncmp(setting, "hsync:", 6)) {
		if (simple_strtoul(setting + 6, &setting, 0) == 0)
			panel_cfg.pol_freq |= DSS_IHS;
		else
			panel_cfg.pol_freq &= ~DSS_IHS;
	} else if (!strncmp(setting, "vsync:", 6)) {
		if (simple_strtoul(setting + 6, &setting, 0) == 0)
			panel_cfg.pol_freq |= DSS_IVS;
		else
			panel_cfg.pol_freq &= ~DSS_IVS;
	} else if (!strncmp(setting, "outputen:", 9)) {
		if (simple_strtoul(setting + 9, &setting, 0) == 0)
			panel_cfg.pol_freq |= DSS_IEO;
		else
			panel_cfg.pol_freq &= ~DSS_IEO;
	} else if (!strncmp(setting, "pixclockpol:", 12)) {
		if (simple_strtoul(setting + 12, &setting, 0) == 0)
			panel_cfg.pol_freq |= DSS_IPC;
		else
			panel_cfg.pol_freq &= ~DSS_IPC;
	} else if (!strncmp(setting, "active", 6)) {
		panel_cfg.panel_type = ACTIVE_DISPLAY;
		return 0; /* Avoid sanity check below */
	} else if (!strncmp(setting, "passive", 7)) {
		panel_cfg.panel_type = PASSIVE_DISPLAY;
		return 0; /* Avoid sanity check below */
	} else if (!strncmp(setting, "display:", 8)) {
		if (!strncmp(setting + 8, "dvi", 3)) {
			lcd_def = DVI_CUSTOM;
			return 0; /* Avoid sanity check below */
		}
	} else {
		printf("LCD: unknown option %s\n", setting_start);
		return -1;
	}

	if (setting[0] != '\0') {
		printf("LCD: invalid value for %s\n", setting_start);
		return -1;
	}

	return 0;
}

/*
 * env_parse_customlcd() - parse custom lcd params from an environment variable.
 *
 * @custom_lcd_params:	The environment variable containing the lcd params.
 *
 * Returns -1 on failure, 0 on success.
 */
static int parse_customlcd(char *custom_lcd_params)
{
	char params_cpy[160];
	char *setting;

	strncpy(params_cpy, custom_lcd_params, 160);
	setting = strtok(params_cpy, ",");
	while (setting) {
		if (parse_setting(setting) < 0)
			return -1;

		setting = strtok(NULL, ",");
	}

	/* Currently we don't support changing this via custom lcd params */
	panel_cfg.data_lines = LCD_INTERFACE_24_BIT;
	panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */

	return 0;
}

/*
 * env_parse_displaytype() - parse display type.
 *
 * Parses the environment variable "displaytype", which contains the
 * name of the display type or preset, in which case it applies its
 * configurations.
 *
 * Returns the type of display that was specified.
 */
static enum display_type env_parse_displaytype(char *displaytype)
{
	if (!strncmp(displaytype, "dvi640x480", 10))
		return set_dvi_preset(preset_dvi_640X480, 640, 480);
	else if (!strncmp(displaytype, "dvi800x600", 10))
		return set_dvi_preset(preset_dvi_800X600, 800, 600);
	else if (!strncmp(displaytype, "dvi1024x768", 11))
		return set_dvi_preset(preset_dvi_1024X768, 1024, 768);
	else if (!strncmp(displaytype, "dvi1152x864", 11))
		return set_dvi_preset(preset_dvi_1152X864, 1152, 864);
	else if (!strncmp(displaytype, "dvi1280x960", 11))
		return set_dvi_preset(preset_dvi_1280X960, 1280, 960);
	else if (!strncmp(displaytype, "dvi1280x1024", 12))
		return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024);
	else if (!strncmp(displaytype, "dataimage480x800", 16))
		return set_dataimage_preset(preset_dataimage_480X800, 480, 800);

	return NONE;
}

void lcd_ctrl_init(void *lcdbase)
{
	struct prcm *prcm = (struct prcm *)PRCM_BASE;
	char *custom_lcd;
	char *displaytype = env_get("displaytype");

	if (displaytype == NULL)
		return;

	lcd_def = env_parse_displaytype(displaytype);
	/* If we did not recognize the preset, check if it's an env variable */
	if (lcd_def == NONE) {
		custom_lcd = env_get(displaytype);
		if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0)
			return;
	}

	panel_cfg.frame_buffer = lcdbase;
	omap3_dss_panel_config(&panel_cfg);
	/*
	 * Pixel clock is defined with many divisions and only few
	 * multiplications of the system clock. Since DSS FCLK divisor is set
	 * to 16 by default, we need to set it to a smaller value, like 3
	 * (chosen via trial and error).
	 */
	clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
}

#ifdef CONFIG_SCF0403_LCD
static void scf0403_enable(void)
{
	gpio_direction_output(58, 1);
	scf0403_init(157);
}
#else
static inline void scf0403_enable(void) {}
#endif

void lcd_enable(void)
{
	switch (lcd_def) {
	case NONE:
		return;
	case DVI:
	case DVI_CUSTOM:
		gpio_direction_output(54, 0); /* Turn on DVI */
		break;
	case DATA_IMAGE:
		scf0403_enable();
		break;
	}

	omap3_dss_enable();
}

void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {}
Commit	Line	Data
7878ca51	1	/*
811acf92	2	* (C) Copyright 2012 - 2013 CompuLab, Ltd. <www.compulab.co.il>
7878ca51 NK	3	*
	4	* Authors: Nikita Kiryanov <nikita@compulab.co.il>
	5	*
4fc4afa9 NK	6	* Parsing code based on linux/drivers/video/pxafb.c
4fc4afa9 NK	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
7878ca51	9	*/
1a459660	10
7878ca51 NK	11	#include <common.h>
	12	#include <asm/gpio.h>
	13	#include <asm/io.h>
	14	#include <stdio_dev.h>
	15	#include <asm/arch/dss.h>
	16	#include <lcd.h>
63c4f17b	17	#include <scf0403_lcd.h>
7878ca51 NK	18	#include <asm/arch-omap3/dss.h>
	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
	22	enum display_type {
	23	NONE,
	24	DVI,
4fc4afa9	25	DVI_CUSTOM,
63c4f17b	26	DATA_IMAGE, /* #define CONFIG_SCF0403_LCD to use */
7878ca51 NK	27	};
	28
	29	#define CMAP_ADDR 0x80100000
	30
	31	/*
	32	* The frame buffer is allocated before we have the chance to parse user input.
	33	* To make sure enough memory is allocated for all resolutions, we define
	34	* vl_{col \| row} to the maximal resolution supported by OMAP3.
	35	*/
	36	vidinfo_t panel_info = {
	37	.vl_col = 1400,
	38	.vl_row = 1050,
	39	.vl_bpix = LCD_BPP,
	40	.cmap = (ushort *)CMAP_ADDR,
	41	};
	42
	43	static struct panel_config panel_cfg;
	44	static enum display_type lcd_def;
	45
	46	/*
	47	* A note on DVI presets;
	48	* U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can
	49	* convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to
	50	* support two BMP types with one setting.
	51	*/
	52	static const struct panel_config preset_dvi_640X480 = {
	53	.lcd_size = PANEL_LCD_SIZE(640, 480),
	54	.timing_h = DSS_HBP(48) \| DSS_HFP(16) \| DSS_HSW(96),
	55	.timing_v = DSS_VBP(33) \| DSS_VFP(10) \| DSS_VSW(2),
f9f6686f	56	.pol_freq = DSS_IHS \| DSS_IVS \| DSS_IPC,
7878ca51 NK	57	.divisor = 12 \| (1 << 16),
	58	.data_lines = LCD_INTERFACE_24_BIT,
	59	.panel_type = ACTIVE_DISPLAY,
	60	.load_mode = 2,
	61	.gfx_format = GFXFORMAT_RGB16,
	62	};
	63
	64	static const struct panel_config preset_dvi_800X600 = {
	65	.lcd_size = PANEL_LCD_SIZE(800, 600),
	66	.timing_h = DSS_HBP(88) \| DSS_HFP(40) \| DSS_HSW(128),
	67	.timing_v = DSS_VBP(23) \| DSS_VFP(1) \| DSS_VSW(4),
f9f6686f	68	.pol_freq = DSS_IHS \| DSS_IVS \| DSS_IPC,
7878ca51 NK	69	.divisor = 8 \| (1 << 16),
	70	.data_lines = LCD_INTERFACE_24_BIT,
	71	.panel_type = ACTIVE_DISPLAY,
	72	.load_mode = 2,
	73	.gfx_format = GFXFORMAT_RGB16,
	74	};
	75
	76	static const struct panel_config preset_dvi_1024X768 = {
	77	.lcd_size = PANEL_LCD_SIZE(1024, 768),
	78	.timing_h = DSS_HBP(160) \| DSS_HFP(24) \| DSS_HSW(136),
	79	.timing_v = DSS_VBP(29) \| DSS_VFP(3) \| DSS_VSW(6),
f9f6686f	80	.pol_freq = DSS_IHS \| DSS_IVS \| DSS_IPC,
7878ca51 NK	81	.divisor = 5 \| (1 << 16),
	82	.data_lines = LCD_INTERFACE_24_BIT,
	83	.panel_type = ACTIVE_DISPLAY,
	84	.load_mode = 2,
	85	.gfx_format = GFXFORMAT_RGB16,
	86	};
	87
	88	static const struct panel_config preset_dvi_1152X864 = {
	89	.lcd_size = PANEL_LCD_SIZE(1152, 864),
	90	.timing_h = DSS_HBP(256) \| DSS_HFP(64) \| DSS_HSW(128),
	91	.timing_v = DSS_VBP(32) \| DSS_VFP(1) \| DSS_VSW(3),
f9f6686f NK	92	.pol_freq = DSS_IHS \| DSS_IVS \| DSS_IPC,
f9f6686f NK	93	.divisor = 4 \| (1 << 16),
7878ca51 NK	94	.data_lines = LCD_INTERFACE_24_BIT,
	95	.panel_type = ACTIVE_DISPLAY,
	96	.load_mode = 2,
	97	.gfx_format = GFXFORMAT_RGB16,
	98	};
	99
	100	static const struct panel_config preset_dvi_1280X960 = {
	101	.lcd_size = PANEL_LCD_SIZE(1280, 960),
	102	.timing_h = DSS_HBP(312) \| DSS_HFP(96) \| DSS_HSW(112),
	103	.timing_v = DSS_VBP(36) \| DSS_VFP(1) \| DSS_VSW(3),
f9f6686f	104	.pol_freq = DSS_IHS \| DSS_IVS \| DSS_IPC,
7878ca51 NK	105	.divisor = 3 \| (1 << 16),
	106	.data_lines = LCD_INTERFACE_24_BIT,
	107	.panel_type = ACTIVE_DISPLAY,
	108	.load_mode = 2,
	109	.gfx_format = GFXFORMAT_RGB16,
	110	};
	111
	112	static const struct panel_config preset_dvi_1280X1024 = {
	113	.lcd_size = PANEL_LCD_SIZE(1280, 1024),
	114	.timing_h = DSS_HBP(248) \| DSS_HFP(48) \| DSS_HSW(112),
	115	.timing_v = DSS_VBP(38) \| DSS_VFP(1) \| DSS_VSW(3),
f9f6686f	116	.pol_freq = DSS_IHS \| DSS_IVS \| DSS_IPC,
7878ca51 NK	117	.divisor = 3 \| (1 << 16),
	118	.data_lines = LCD_INTERFACE_24_BIT,
	119	.panel_type = ACTIVE_DISPLAY,
	120	.load_mode = 2,
	121	.gfx_format = GFXFORMAT_RGB16,
	122	};
	123
63c4f17b NK	124	static const struct panel_config preset_dataimage_480X800 = {
	125	.lcd_size = PANEL_LCD_SIZE(480, 800),
	126	.timing_h = DSS_HBP(2) \| DSS_HFP(2) \| DSS_HSW(2),
	127	.timing_v = DSS_VBP(17) \| DSS_VFP(20) \| DSS_VSW(3),
	128	.pol_freq = DSS_IVS \| DSS_IHS \| DSS_IPC \| DSS_ONOFF,
	129	.divisor = 10 \| (1 << 10),
	130	.data_lines = LCD_INTERFACE_18_BIT,
	131	.panel_type = ACTIVE_DISPLAY,
	132	.load_mode = 2,
	133	.gfx_format = GFXFORMAT_RGB16,
	134	};
	135
7878ca51 NK	136	/*
	137	* set_resolution_params()
	138	*
	139	* Due to usage of multiple display related APIs resolution data is located in
	140	* more than one place. This function updates them all.
	141	*/
	142	static void set_resolution_params(int x, int y)
	143	{
	144	panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y);
	145	panel_info.vl_col = x;
	146	panel_info.vl_row = y;
	147	lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
	148	}
	149
	150	static void set_preset(const struct panel_config preset, int x_res, int y_res)
	151	{
	152	panel_cfg = preset;
	153	set_resolution_params(x_res, y_res);
	154	}
	155
	156	static enum display_type set_dvi_preset(const struct panel_config preset,
	157	int x_res, int y_res)
	158	{
	159	set_preset(preset, x_res, y_res);
	160	return DVI;
	161	}
	162
63c4f17b NK	163	static enum display_type set_dataimage_preset(const struct panel_config preset,
	164	int x_res, int y_res)
	165	{
	166	set_preset(preset, x_res, y_res);
	167	return DATA_IMAGE;
	168	}
	169
4fc4afa9 NK	170	/*
	171	* parse_mode() - parse the mode parameter of custom lcd settings
	172	*
	173	* @mode: <res_x>x<res_y>
	174	*
	175	* Returns -1 on error, 0 on success.
	176	*/
	177	static int parse_mode(const char *mode)
	178	{
	179	unsigned int modelen = strlen(mode);
	180	int res_specified = 0;
	181	unsigned int xres = 0, yres = 0;
	182	int yres_specified = 0;
	183	int i;
	184
	185	for (i = modelen - 1; i >= 0; i--) {
	186	switch (mode[i]) {
	187	case 'x':
	188	if (!yres_specified) {
	189	yres = simple_strtoul(&mode[i + 1], NULL, 0);
	190	yres_specified = 1;
	191	} else {
	192	goto done_parsing;
	193	}
	194
	195	break;
	196	case '0' ... '9':
	197	break;
	198	default:
	199	goto done_parsing;
	200	}
	201	}
	202
	203	if (i < 0 && yres_specified) {
	204	xres = simple_strtoul(mode, NULL, 0);
	205	res_specified = 1;
	206	}
	207
	208	done_parsing:
	209	if (res_specified) {
	210	set_resolution_params(xres, yres);
	211	} else {
	212	printf("LCD: invalid mode: %s\n", mode);
	213	return -1;
	214	}
	215
	216	return 0;
	217	}
	218
	219	#define PIXEL_CLK_NUMERATOR (26 * 432 / 39)
	220	/*
	221	* parse_pixclock() - Parse the pixclock parameter of custom lcd settings
	222	*
	223	* @pixclock: the desired pixel clock
	224	*
	225	* Returns -1 on error, 0 on success.
	226	*
	227	* Handling the pixel_clock:
	228	*
	229	* Pixel clock is defined in the OMAP35x TRM as follows:
	230	* pixel_clock =
	231	* (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) /
	232	* (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] *
	233	* PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1))
234	*
235	* In practice, this means that in order to set the
236	* divisor for the desired pixel clock one needs to
237	* solve the following equation:
238	*
239	* 26 * 432 / (39 * <pixel_clock>) = DSS.DISPC_DIVISOR[6:0]
240	*
241	* NOTE: the explicit equation above is reduced. Do not
242	* try to infer anything from these numbers.
243	*/
244	static int parse_pixclock(char *pixclock)
245	{
246	int divisor, pixclock_val;
247	char *pixclk_start = pixclock;
248
249	pixclock_val = simple_strtoul(pixclock, &pixclock, 10);
250	divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val);
251	/* 0 and 1 are illegal values for PCD */
252	if (divisor <= 1)
253	divisor = 2;
254
255	panel_cfg.divisor = divisor \| (1 << 16);
256	if (pixclock[0] != '\0') {
257	printf("LCD: invalid value for pixclock:%s\n", pixclk_start);
258	return -1;
259	}
260
261	return 0;
262	}
263
264	/*
265	* parse_setting() - parse a single setting of custom lcd parameters
266	*
267	* @setting: The custom lcd setting <name>:<value>
268	*
269	* Returns -1 on failure, 0 on success.
270	*/
271	static int parse_setting(char *setting)
272	{
273	int num_val;
274	char *setting_start = setting;
275
276	if (!strncmp(setting, "mode:", 5)) {
277	return parse_mode(setting + 5);
278	} else if (!strncmp(setting, "pixclock:", 9)) {
279	return parse_pixclock(setting + 9);
280	} else if (!strncmp(setting, "left:", 5)) {
281	num_val = simple_strtoul(setting + 5, &setting, 0);
282	panel_cfg.timing_h \|= DSS_HBP(num_val);
283	} else if (!strncmp(setting, "right:", 6)) {
284	num_val = simple_strtoul(setting + 6, &setting, 0);
285	panel_cfg.timing_h \|= DSS_HFP(num_val);
286	} else if (!strncmp(setting, "upper:", 6)) {
287	num_val = simple_strtoul(setting + 6, &setting, 0);
288	panel_cfg.timing_v \|= DSS_VBP(num_val);
289	} else if (!strncmp(setting, "lower:", 6)) {
290	num_val = simple_strtoul(setting + 6, &setting, 0);
291	panel_cfg.timing_v \|= DSS_VFP(num_val);
292	} else if (!strncmp(setting, "hsynclen:", 9)) {
293	num_val = simple_strtoul(setting + 9, &setting, 0);
294	panel_cfg.timing_h \|= DSS_HSW(num_val);
295	} else if (!strncmp(setting, "vsynclen:", 9)) {
296	num_val = simple_strtoul(setting + 9, &setting, 0);
297	panel_cfg.timing_v \|= DSS_VSW(num_val);
298	} else if (!strncmp(setting, "hsync:", 6)) {
299	if (simple_strtoul(setting + 6, &setting, 0) == 0)
300	panel_cfg.pol_freq \|= DSS_IHS;
301	else
302	panel_cfg.pol_freq &= ~DSS_IHS;
303	} else if (!strncmp(setting, "vsync:", 6)) {
304	if (simple_strtoul(setting + 6, &setting, 0) == 0)
305	panel_cfg.pol_freq \|= DSS_IVS;
306	else
307	panel_cfg.pol_freq &= ~DSS_IVS;
308	} else if (!strncmp(setting, "outputen:", 9)) {
309	if (simple_strtoul(setting + 9, &setting, 0) == 0)
310	panel_cfg.pol_freq \|= DSS_IEO;
311	else
312	panel_cfg.pol_freq &= ~DSS_IEO;
313	} else if (!strncmp(setting, "pixclockpol:", 12)) {
314	if (simple_strtoul(setting + 12, &setting, 0) == 0)
315	panel_cfg.pol_freq \|= DSS_IPC;
316	else
317	panel_cfg.pol_freq &= ~DSS_IPC;
318	} else if (!strncmp(setting, "active", 6)) {
319	panel_cfg.panel_type = ACTIVE_DISPLAY;
320	return 0; /* Avoid sanity check below */
321	} else if (!strncmp(setting, "passive", 7)) {
322	panel_cfg.panel_type = PASSIVE_DISPLAY;
323	return 0; /* Avoid sanity check below */
324	} else if (!strncmp(setting, "display:", 8)) {
325	if (!strncmp(setting + 8, "dvi", 3)) {
326	lcd_def = DVI_CUSTOM;
327	return 0; /* Avoid sanity check below */
328	}
329	} else {
330	printf("LCD: unknown option %s\n", setting_start);
331	return -1;
332	}
333
334	if (setting[0] != '\0') {
335	printf("LCD: invalid value for %s\n", setting_start);
336	return -1;
337	}
338
339	return 0;
340	}
341
342	/*
343	* env_parse_customlcd() - parse custom lcd params from an environment variable.
344	*
345	* @custom_lcd_params: The environment variable containing the lcd params.
346	*
347	* Returns -1 on failure, 0 on success.
348	*/
349	static int parse_customlcd(char *custom_lcd_params)
350	{
351	char params_cpy[160];
352	char *setting;
353
354	strncpy(params_cpy, custom_lcd_params, 160);
355	setting = strtok(params_cpy, ",");
356	while (setting) {
357	if (parse_setting(setting) < 0)
358	return -1;
359
360	setting = strtok(NULL, ",");
361	}
362
363	/* Currently we don't support changing this via custom lcd params */
364	panel_cfg.data_lines = LCD_INTERFACE_24_BIT;
365	panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */
366
367	return 0;
368	}
369
7878ca51 NK	370	/*
	371	* env_parse_displaytype() - parse display type.
	372	*
	373	* Parses the environment variable "displaytype", which contains the
	374	* name of the display type or preset, in which case it applies its
	375	* configurations.
	376	*
	377	* Returns the type of display that was specified.
	378	*/
	379	static enum display_type env_parse_displaytype(char *displaytype)
	380	{
	381	if (!strncmp(displaytype, "dvi640x480", 10))
	382	return set_dvi_preset(preset_dvi_640X480, 640, 480);
	383	else if (!strncmp(displaytype, "dvi800x600", 10))
	384	return set_dvi_preset(preset_dvi_800X600, 800, 600);
	385	else if (!strncmp(displaytype, "dvi1024x768", 11))
	386	return set_dvi_preset(preset_dvi_1024X768, 1024, 768);
	387	else if (!strncmp(displaytype, "dvi1152x864", 11))
	388	return set_dvi_preset(preset_dvi_1152X864, 1152, 864);
	389	else if (!strncmp(displaytype, "dvi1280x960", 11))
	390	return set_dvi_preset(preset_dvi_1280X960, 1280, 960);
	391	else if (!strncmp(displaytype, "dvi1280x1024", 12))
	392	return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024);
63c4f17b NK	393	else if (!strncmp(displaytype, "dataimage480x800", 16))
63c4f17b NK	394	return set_dataimage_preset(preset_dataimage_480X800, 480, 800);
7878ca51 NK	395
	396	return NONE;
	397	}
	398
7878ca51 NK	399	void lcd_ctrl_init(void *lcdbase)
	400	{
	401	struct prcm prcm = (struct prcm )PRCM_BASE;
4fc4afa9	402	char *custom_lcd;
00caae6d	403	char *displaytype = env_get("displaytype");
7878ca51 NK	404
	405	if (displaytype == NULL)
	406	return;
	407
	408	lcd_def = env_parse_displaytype(displaytype);
4fc4afa9 NK	409	/* If we did not recognize the preset, check if it's an env variable */
4fc4afa9 NK	410	if (lcd_def == NONE) {
00caae6d	411	custom_lcd = env_get(displaytype);
4fc4afa9 NK	412	if (custom_lcd == NULL \|\| parse_customlcd(custom_lcd) < 0)
	413	return;
	414	}
7878ca51 NK	415
	416	panel_cfg.frame_buffer = lcdbase;
	417	omap3_dss_panel_config(&panel_cfg);
	418	/*
	419	* Pixel clock is defined with many divisions and only few
	420	* multiplications of the system clock. Since DSS FCLK divisor is set
	421	* to 16 by default, we need to set it to a smaller value, like 3
	422	* (chosen via trial and error).
	423	*/
	424	clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
	425	}
	426
63c4f17b NK	427	#ifdef CONFIG_SCF0403_LCD
	428	static void scf0403_enable(void)
	429	{
	430	gpio_direction_output(58, 1);
	431	scf0403_init(157);
	432	}
	433	#else
	434	static inline void scf0403_enable(void) {}
	435	#endif
	436
7878ca51 NK	437	void lcd_enable(void)
7878ca51 NK	438	{
63c4f17b NK	439	switch (lcd_def) {
	440	case NONE:
	441	return;
	442	case DVI:
	443	case DVI_CUSTOM:
7878ca51	444	gpio_direction_output(54, 0); /* Turn on DVI */
63c4f17b NK	445	break;
	446	case DATA_IMAGE:
	447	scf0403_enable();
	448	break;
7878ca51	449	}
63c4f17b NK	450
63c4f17b NK	451	omap3_dss_enable();
7878ca51 NK	452	}
	453
	454	void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {}