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cgtqmx6eval: Add SPI NOR flash support
[people/ms/u-boot.git] / board / congatec / cgtqmx6eval / cgtqmx6eval.c
CommitLineData
9b75bad0
SL		 1/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 * Based on mx6qsabrelite.c file
4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
5 * Leo Sartre, <lsartre@adeneo-embedded.com>
6 *
3765b3e7 7 * SPDX-License-Identifier: GPL-2.0+
9b75bad0
SL		 8 */
9
10#include <common.h>
11#include <asm/io.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/iomux.h>
15#include <asm/arch/mx6-pins.h>
16#include <asm/gpio.h>
17#include <asm/imx-common/iomux-v3.h>
6731bc8d 18#include <asm/imx-common/sata.h>
9b75bad0 19#include <asm/imx-common/boot_mode.h>
4c9929d6 20#include <asm/imx-common/mxc_i2c.h>
6d551f27
OS		 21#include <asm/arch/mxc_hdmi.h>
22#include <asm/arch/crm_regs.h>
9b75bad0
SL		 23#include <mmc.h>
24#include <fsl_esdhc.h>
4c9929d6
OS		 25#include <i2c.h>
26#include <power/pmic.h>
27#include <power/pfuze100_pmic.h>
6d551f27
OS		 28#include <linux/fb.h>
29#include <ipu_pixfmt.h>
f0222902
OS		 30#include <malloc.h>
31#include <miiphy.h>
32#include <netdev.h>
33#include <micrel.h>
9b75bad0
SL		 34
35DECLARE_GLOBAL_DATA_PTR;
36
37#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
38 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39
40#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
41 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
4c9929d6
OS		 43#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
44 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
45 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
46 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
47
71bcdafe
OS		 48#define SPI_PAD_CTRL (PAD_CTL_HYS | \
49 PAD_CTL_SPEED_MED | \
50 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
51
4c9929d6
OS		 52#define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9)
53
f0222902
OS		 54
55#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
56 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
57 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
58
9b75bad0
SL		 59int dram_init(void)
60{
61 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
62
63 return 0;
64}
65
6b3496f7 66static iomux_v3_cfg_t const uart2_pads[] = {
10fda487
EN		 67 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
68 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
9b75bad0
SL		 69};
70
6b3496f7 71static iomux_v3_cfg_t const usdhc2_pads[] = {
10fda487
EN		 72 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
9b75bad0
SL		 79};
80
45e4d350
OS		 81static iomux_v3_cfg_t const usdhc3_pads[] = {
82 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93};
94
6b3496f7 95static iomux_v3_cfg_t const usdhc4_pads[] = {
10fda487
EN		 96 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
9b75bad0
SL		 107};
108
95246ac7
OS		 109static iomux_v3_cfg_t const usb_otg_pads[] = {
110 MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
111 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
112};
113
f0222902
OS		 114static iomux_v3_cfg_t enet_pads_ksz9031[] = {
115 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
119 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
120 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
121 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
122 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
124 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
125 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
126 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
127 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
128 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
129 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
130};
131
132static iomux_v3_cfg_t enet_pads_final_ksz9031[] = {
133 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
134 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
135 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
136 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
137 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
138 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
139};
140
141static iomux_v3_cfg_t enet_pads_ar8035[] = {
142 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
143 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
144 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
145 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
146 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
147 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
148 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
149 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
150 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
151 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
152 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
153 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
154 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
155 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
156 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
157};
158
71bcdafe
OS		 159static iomux_v3_cfg_t const ecspi1_pads[] = {
160 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
161 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
162 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
163 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
164};
165
4c9929d6
OS		 166#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
167struct i2c_pads_info i2c_pad_info1 = {
168 .scl = {
169 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
170 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
171 .gp = IMX_GPIO_NR(4, 12)
172 },
173 .sda = {
174 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
175 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
176 .gp = IMX_GPIO_NR(4, 13)
177 }
178};
179
180#define I2C_PMIC 1 /* I2C2 port is used to connect to the PMIC */
181
182struct interface_level {
183 char *name;
184 uchar value;
185};
186
187static struct interface_level mipi_levels[] = {
188 {"0V0", 0x00},
189 {"2V5", 0x17},
190};
191
192/* setup board specific PMIC */
193int power_init_board(void)
194{
195 struct pmic *p;
196 u32 id1, id2, i;
197 int ret;
198 char const *lv_mipi;
199
200 /* configure I2C multiplexer */
201 gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
202
203 power_pfuze100_init(I2C_PMIC);
204 p = pmic_get("PFUZE100");
205 if (!p)
206 return -EINVAL;
207
208 ret = pmic_probe(p);
209 if (ret)
210 return ret;
211
212 pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
213 pmic_reg_read(p, PFUZE100_REVID, &id2);
214 printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
215
216 if (id2 >= 0x20)
217 return 0;
218
219 /* set level of MIPI if specified */
220 lv_mipi = getenv("lv_mipi");
221 if (lv_mipi)
222 return 0;
223
224 for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
225 if (!strcmp(mipi_levels[i].name, lv_mipi)) {
f5cf9e65 226 printf("set MIPI level %s\n", mipi_levels[i].name);
4c9929d6
OS		 227 ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
228 mipi_levels[i].value);
229 if (ret)
230 return ret;
231 }
232 }
233
234 return 0;
235}
f0222902
OS		 236
237int board_eth_init(bd_t *bis)
238{
239 struct phy_device *phydev;
240 struct mii_dev *bus;
241 unsigned short id1, id2;
242 int ret;
243
244 iomux_v3_cfg_t enet_reset = MX6_PAD_EIM_D23__GPIO3_IO23 |
245 MUX_PAD_CTRL(NO_PAD_CTRL);
246
247 /* check whether KSZ9031 or AR8035 has to be configured */
248 imx_iomux_v3_setup_multiple_pads(enet_pads_ar8035,
249 ARRAY_SIZE(enet_pads_ar8035));
250 imx_iomux_v3_setup_pad(enet_reset);
251
252 /* phy reset */
253 gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
254 udelay(2000);
255 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
256 udelay(500);
257
258 bus = fec_get_miibus(IMX_FEC_BASE, -1);
259 if (!bus)
260 return -EINVAL;
261 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
262 if (!phydev) {
263 printf("Error: phy device not found.\n");
264 ret = -ENODEV;
265 goto free_bus;
266 }
267
268 /* get the PHY id */
269 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
270 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
271
272 if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
273 /* re-configure for Micrel KSZ9031 */
274 printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n",
275 phydev->addr);
276
277 /* phy reset: gpio3-23 */
278 gpio_set_value(IMX_GPIO_NR(3, 23), 0);
279 gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2));
280 gpio_set_value(IMX_GPIO_NR(6, 25), 1);
281 gpio_set_value(IMX_GPIO_NR(6, 27), 1);
282 gpio_set_value(IMX_GPIO_NR(6, 28), 1);
283 gpio_set_value(IMX_GPIO_NR(6, 29), 1);
284 imx_iomux_v3_setup_multiple_pads(enet_pads_ksz9031,
285 ARRAY_SIZE(enet_pads_ksz9031));
286 gpio_set_value(IMX_GPIO_NR(6, 24), 1);
287 udelay(500);
288 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
289 imx_iomux_v3_setup_multiple_pads(enet_pads_final_ksz9031,
290 ARRAY_SIZE(enet_pads_final_ksz9031));
291 } else if ((id1 == 0x004d) && (id2 == 0xd072)) {
292 /* configure Atheros AR8035 - actually nothing to do */
293 printf("configure Atheros AR8035 Ethernet Phy at address %d\n",
294 phydev->addr);
295 } else {
296 printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2);
297 ret = -EINVAL;
298 goto free_phydev;
299 }
300
301 ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
302 if (ret)
303 goto free_phydev;
304
305 return 0;
306
307free_phydev:
308 free(phydev);
309free_bus:
310 free(bus);
311 return ret;
312}
313
314int mx6_rgmii_rework(struct phy_device *phydev)
315{
316 unsigned short id1, id2;
317 unsigned short val;
318
319 /* check whether KSZ9031 or AR8035 has to be configured */
320 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
321 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
322
323 if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
324 /* finalize phy configuration for Micrel KSZ9031 */
325 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
326 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4);
327 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
328 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000);
329
330 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
331 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5);
332 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
333 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG);
334
335 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
336 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6);
337 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
338 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF);
339
340 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
341 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8);
342 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
343 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF);
344
345 /* fix KSZ9031 link up issue */
346 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0);
347 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4);
348 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
349 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6);
350 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG);
351 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3);
352 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
353 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80);
354 }
355
356 if ((id1 == 0x004d) && (id2 == 0xd072)) {
357 /* enable AR8035 ouput a 125MHz clk from CLK_25M */
358 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7);
359 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16);
360 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7);
361 val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA);
362 val &= 0xfe63;
363 val |= 0x18;
364 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val);
365
366 /* introduce tx clock delay */
367 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
368 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
369 val |= 0x0100;
370 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
371
372 /* disable hibernation */
373 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb);
374 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
375 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40);
376 }
377 return 0;
378}
379
380int board_phy_config(struct phy_device *phydev)
381{
382 mx6_rgmii_rework(phydev);
383
384 if (phydev->drv->config)
385 phydev->drv->config(phydev);
386
387 return 0;
388}
4c9929d6 389
9b75bad0
SL		 390static void setup_iomux_uart(void)
391{
392 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
393}
394
71bcdafe
OS		 395#ifdef CONFIG_MXC_SPI
396static void setup_spi(void)
397{
398 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
399 gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
400}
401#endif
402
9b75bad0 403#ifdef CONFIG_FSL_ESDHC
6b3496f7 404static struct fsl_esdhc_cfg usdhc_cfg[] = {
9b75bad0 405 {USDHC2_BASE_ADDR},
45e4d350 406 {USDHC3_BASE_ADDR},
9b75bad0
SL		 407 {USDHC4_BASE_ADDR},
408};
409
410int board_mmc_getcd(struct mmc *mmc)
411{
412 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
413 int ret = 0;
414
415 switch (cfg->esdhc_base) {
416 case USDHC2_BASE_ADDR:
417 gpio_direction_input(IMX_GPIO_NR(1, 4));
418 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
419 break;
45e4d350
OS		 420 case USDHC3_BASE_ADDR:
421 ret = 1; /* eMMC is always present */
422 break;
9b75bad0
SL		 423 case USDHC4_BASE_ADDR:
424 gpio_direction_input(IMX_GPIO_NR(2, 6));
425 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
426 break;
427 default:
428 printf("Bad USDHC interface\n");
429 }
430
431 return ret;
432}
433
434int board_mmc_init(bd_t *bis)
435{
436 s32 status = 0;
516a863e 437 int i;
9b75bad0
SL		 438
439 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
45e4d350
OS		 440 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
441 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
9b75bad0 442
dbcb6ffb 443 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
45e4d350 444 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
dbcb6ffb 445 imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
9b75bad0 446
516a863e
OS		 447 for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
448 status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
449 if (status)
450 return status;
451 }
9b75bad0 452
516a863e 453 return 0;
9b75bad0
SL		 454}
455#endif
456
95246ac7
OS		 457int board_ehci_hcd_init(int port)
458{
459 switch (port) {
460 case 0:
461 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
462 ARRAY_SIZE(usb_otg_pads));
463 /*
464 * set daisy chain for otg_pin_id on 6q.
465 * for 6dl, this bit is reserved
466 */
467 imx_iomux_set_gpr_register(1, 13, 1, 1);
468 break;
469 case 1:
470 /* nothing to do */
471 break;
472 default:
473 printf("Invalid USB port: %d\n", port);
474 return -EINVAL;
475 }
476
477 return 0;
478}
479
480int board_ehci_power(int port, int on)
481{
482 switch (port) {
483 case 0:
484 break;
485 case 1:
486 gpio_direction_output(IMX_GPIO_NR(5, 5), on);
487 break;
488 default:
489 printf("Invalid USB port: %d\n", port);
490 return -EINVAL;
491 }
492
493 return 0;
494}
495
6d551f27
OS		 496struct display_info_t {
497 int bus;
498 int addr;
499 int pixfmt;
500 int (*detect)(struct display_info_t const *dev);
501 void (*enable)(struct display_info_t const *dev);
502 struct fb_videomode mode;
503};
504
505static void disable_lvds(struct display_info_t const *dev)
506{
507 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
508
509 clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
510 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
511}
512
513static void do_enable_hdmi(struct display_info_t const *dev)
514{
515 disable_lvds(dev);
516 imx_enable_hdmi_phy();
517}
518
519static struct display_info_t const displays[] = {
520{
521 .bus = -1,
522 .addr = 0,
523 .pixfmt = IPU_PIX_FMT_RGB666,
524 .detect = NULL,
525 .enable = NULL,
526 .mode = {
527 .name =
528 "Hannstar-XGA",
529 .refresh = 60,
530 .xres = 1024,
531 .yres = 768,
532 .pixclock = 15385,
533 .left_margin = 220,
534 .right_margin = 40,
535 .upper_margin = 21,
536 .lower_margin = 7,
537 .hsync_len = 60,
538 .vsync_len = 10,
539 .sync = FB_SYNC_EXT,
540 .vmode = FB_VMODE_NONINTERLACED } },
541{
542 .bus = -1,
543 .addr = 0,
544 .pixfmt = IPU_PIX_FMT_RGB24,
545 .detect = NULL,
546 .enable = do_enable_hdmi,
547 .mode = {
548 .name = "HDMI",
549 .refresh = 60,
550 .xres = 1024,
551 .yres = 768,
552 .pixclock = 15385,
553 .left_margin = 220,
554 .right_margin = 40,
555 .upper_margin = 21,
556 .lower_margin = 7,
557 .hsync_len = 60,
558 .vsync_len = 10,
559 .sync = FB_SYNC_EXT,
560 .vmode = FB_VMODE_NONINTERLACED } }
561};
562
563int board_video_skip(void)
564{
565 int i;
566 int ret;
567 char const *panel = getenv("panel");
568 if (!panel) {
569 for (i = 0; i < ARRAY_SIZE(displays); i++) {
570 struct display_info_t const *dev = displays + i;
571 if (dev->detect && dev->detect(dev)) {
572 panel = dev->mode.name;
573 printf("auto-detected panel %s\n", panel);
574 break;
575 }
576 }
577 if (!panel) {
578 panel = displays[0].mode.name;
579 printf("No panel detected: default to %s\n", panel);
580 i = 0;
581 }
582 } else {
583 for (i = 0; i < ARRAY_SIZE(displays); i++) {
584 if (!strcmp(panel, displays[i].mode.name))
585 break;
586 }
587 }
588 if (i < ARRAY_SIZE(displays)) {
589 ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt);
590 if (!ret) {
591 if (displays[i].enable)
592 displays[i].enable(displays + i);
593 printf("Display: %s (%ux%u)\n",
594 displays[i].mode.name, displays[i].mode.xres,
595 displays[i].mode.yres);
596 } else
597 printf("LCD %s cannot be configured: %d\n",
598 displays[i].mode.name, ret);
599 } else {
600 printf("unsupported panel %s\n", panel);
601 return -EINVAL;
602 }
603
604 return 0;
605}
606
607static void setup_display(void)
608{
609 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
610 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
611 int reg;
612
613 enable_ipu_clock();
614 imx_setup_hdmi();
615
616 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
617 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK |
618 MXC_CCM_CCGR3_LDB_DI1_MASK);
619
620 /* set LDB0, LDB1 clk select to 011/011 */
621 reg = readl(&mxc_ccm->cs2cdr);
622 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
623 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
624 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
625 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
626 writel(reg, &mxc_ccm->cs2cdr);
627
628 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV |
629 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV);
630
631 setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
632 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET |
633 CHSCCDR_CLK_SEL_LDB_DI0 <<
634 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
635
636 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
637 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
638 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
639 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
640 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
641 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
642 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
643 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
644 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
645 writel(reg, &iomux->gpr[2]);
646
647 reg = readl(&iomux->gpr[3]);
648 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
649 IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
650 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
651 IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
652 writel(reg, &iomux->gpr[3]);
653}
654
655/*
656 * Do not overwrite the console
657 * Use always serial for U-Boot console
658 */
659int overwrite_console(void)
660{
661 return 1;
662}
663
9b75bad0
SL		 664int board_early_init_f(void)
665{
666 setup_iomux_uart();
6d551f27 667 setup_display();
9b75bad0 668
71bcdafe
OS		 669#ifdef CONFIG_MXC_SPI
670 setup_spi();
671#endif
9b75bad0
SL		 672 return 0;
673}
674
675int board_init(void)
676{
677 /* address of boot parameters */
678 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
679
4c9929d6
OS		 680 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
681
6731bc8d
OS		 682#ifdef CONFIG_CMD_SATA
683 setup_sata();
684#endif
685
9b75bad0
SL		 686 return 0;
687}
688
689int checkboard(void)
690{
691 puts("Board: Conga-QEVAL QMX6 Quad\n");
692
693 return 0;
694}
695
71bcdafe
OS		 696#ifdef CONFIG_MXC_SPI
697int board_spi_cs_gpio(unsigned bus, unsigned cs)
698{
699 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL;
700}
701#endif
702
9b75bad0
SL		 703#ifdef CONFIG_CMD_BMODE
704static const struct boot_mode board_boot_modes[] = {
705 /* 4 bit bus width */
706 {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
707 {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
708 {NULL, 0},
709};
710#endif
711
712int misc_init_r(void)
713{
714#ifdef CONFIG_CMD_BMODE
715 add_board_boot_modes(board_boot_modes);
716#endif
717 return 0;
718}
"Das U-Boot" Source Tree