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mx6: ddr: Allow changing REFSEL and REFR fields
[people/ms/u-boot.git] / board / congatec / cgtqmx6eval / cgtqmx6eval.c
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9b75bad0
SL		 1/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 * Based on mx6qsabrelite.c file
4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
5 * Leo Sartre, <lsartre@adeneo-embedded.com>
6 *
3765b3e7 7 * SPDX-License-Identifier: GPL-2.0+
9b75bad0
SL		 8 */
9
10#include <common.h>
11#include <asm/io.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/imx-regs.h>
14#include <asm/arch/iomux.h>
15#include <asm/arch/mx6-pins.h>
16#include <asm/gpio.h>
17#include <asm/imx-common/iomux-v3.h>
6731bc8d 18#include <asm/imx-common/sata.h>
9b75bad0 19#include <asm/imx-common/boot_mode.h>
4c9929d6 20#include <asm/imx-common/mxc_i2c.h>
d7140351 21#include <asm/arch/sys_proto.h>
6d551f27
OS		 22#include <asm/arch/mxc_hdmi.h>
23#include <asm/arch/crm_regs.h>
9b75bad0
SL		 24#include <mmc.h>
25#include <fsl_esdhc.h>
4c9929d6
OS		 26#include <i2c.h>
27#include <power/pmic.h>
28#include <power/pfuze100_pmic.h>
6d551f27
OS		 29#include <linux/fb.h>
30#include <ipu_pixfmt.h>
f0222902
OS		 31#include <malloc.h>
32#include <miiphy.h>
33#include <netdev.h>
34#include <micrel.h>
d7140351
OS		 35#include <spi_flash.h>
36#include <spi.h>
9b75bad0
SL		 37
38DECLARE_GLOBAL_DATA_PTR;
39
40#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
41 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
43#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
44 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45
4c9929d6
OS		 46#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
49 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
50
71bcdafe
OS		 51#define SPI_PAD_CTRL (PAD_CTL_HYS | \
52 PAD_CTL_SPEED_MED | \
53 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
54
4c9929d6
OS		 55#define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9)
56
f0222902
OS		 57
58#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
59 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
60 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
61
9b75bad0
SL		 62int dram_init(void)
63{
d7140351 64 gd->ram_size = imx_ddr_size();
9b75bad0
SL		 65
66 return 0;
67}
68
6b3496f7 69static iomux_v3_cfg_t const uart2_pads[] = {
d7140351
OS		 70 IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
71 IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
9b75bad0
SL		 72};
73
6b3496f7 74static iomux_v3_cfg_t const usdhc2_pads[] = {
d7140351
OS		 75 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
76 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
78 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
79 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
80 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
81 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
9b75bad0
SL		 82};
83
45e4d350 84static iomux_v3_cfg_t const usdhc3_pads[] = {
d7140351
OS		 85 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
86 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
87 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
88 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
89 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
90 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
91 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
92 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
93 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
94 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
95 IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
45e4d350
OS		 96};
97
6b3496f7 98static iomux_v3_cfg_t const usdhc4_pads[] = {
d7140351
OS		 99 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
100 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
101 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
102 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
103 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
104 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
105 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
106 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
107 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
108 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
109 IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
9b75bad0
SL		 110};
111
95246ac7 112static iomux_v3_cfg_t const usb_otg_pads[] = {
d7140351
OS		 113 IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
114 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
95246ac7
OS		 115};
116
f0222902 117static iomux_v3_cfg_t enet_pads_ksz9031[] = {
d7140351
OS		 118 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
119 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
120 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
121 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
122 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
123 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
124 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
125 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
126 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
127 IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
128 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
129 IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
130 IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
131 IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
132 IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
f0222902
OS		 133};
134
135static iomux_v3_cfg_t enet_pads_final_ksz9031[] = {
d7140351
OS		 136 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
137 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
138 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
139 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
140 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
141 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
f0222902
OS		 142};
143
144static iomux_v3_cfg_t enet_pads_ar8035[] = {
d7140351
OS		 145 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
146 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
147 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
148 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
149 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
150 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
151 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
152 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
153 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
154 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
155 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
156 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
157 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
158 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
159 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
f0222902
OS		 160};
161
71bcdafe 162static iomux_v3_cfg_t const ecspi1_pads[] = {
d7140351
OS		 163 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
164 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
165 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
166 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
71bcdafe
OS		 167};
168
4c9929d6 169#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
d7140351 170struct i2c_pads_info mx6q_i2c_pad_info1 = {
4c9929d6 171 .scl = {
d7140351
OS		 172 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
173 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
4c9929d6
OS		 174 .gp = IMX_GPIO_NR(4, 12)
175 },
176 .sda = {
d7140351
OS		 177 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
178 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
179 .gp = IMX_GPIO_NR(4, 13)
180 }
181};
182
183struct i2c_pads_info mx6dl_i2c_pad_info1 = {
184 .scl = {
185 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
186 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
187 .gp = IMX_GPIO_NR(4, 12)
188 },
189 .sda = {
190 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
191 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
4c9929d6
OS		 192 .gp = IMX_GPIO_NR(4, 13)
193 }
194};
195
196#define I2C_PMIC 1 /* I2C2 port is used to connect to the PMIC */
197
198struct interface_level {
199 char *name;
200 uchar value;
201};
202
203static struct interface_level mipi_levels[] = {
204 {"0V0", 0x00},
205 {"2V5", 0x17},
206};
207
208/* setup board specific PMIC */
209int power_init_board(void)
210{
211 struct pmic *p;
212 u32 id1, id2, i;
213 int ret;
214 char const *lv_mipi;
215
216 /* configure I2C multiplexer */
217 gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
218
219 power_pfuze100_init(I2C_PMIC);
220 p = pmic_get("PFUZE100");
221 if (!p)
222 return -EINVAL;
223
224 ret = pmic_probe(p);
225 if (ret)
226 return ret;
227
228 pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
229 pmic_reg_read(p, PFUZE100_REVID, &id2);
230 printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
231
232 if (id2 >= 0x20)
233 return 0;
234
235 /* set level of MIPI if specified */
236 lv_mipi = getenv("lv_mipi");
237 if (lv_mipi)
238 return 0;
239
240 for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
241 if (!strcmp(mipi_levels[i].name, lv_mipi)) {
f5cf9e65 242 printf("set MIPI level %s\n", mipi_levels[i].name);
4c9929d6
OS		 243 ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
244 mipi_levels[i].value);
245 if (ret)
246 return ret;
247 }
248 }
249
250 return 0;
251}
f0222902
OS		 252
253int board_eth_init(bd_t *bis)
254{
255 struct phy_device *phydev;
256 struct mii_dev *bus;
257 unsigned short id1, id2;
258 int ret;
259
f0222902 260 /* check whether KSZ9031 or AR8035 has to be configured */
d7140351 261 SETUP_IOMUX_PADS(enet_pads_ar8035);
f0222902
OS		 262
263 /* phy reset */
264 gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
265 udelay(2000);
266 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
267 udelay(500);
268
269 bus = fec_get_miibus(IMX_FEC_BASE, -1);
270 if (!bus)
271 return -EINVAL;
272 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
273 if (!phydev) {
274 printf("Error: phy device not found.\n");
275 ret = -ENODEV;
276 goto free_bus;
277 }
278
279 /* get the PHY id */
280 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
281 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
282
283 if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
284 /* re-configure for Micrel KSZ9031 */
285 printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n",
286 phydev->addr);
287
288 /* phy reset: gpio3-23 */
289 gpio_set_value(IMX_GPIO_NR(3, 23), 0);
290 gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2));
291 gpio_set_value(IMX_GPIO_NR(6, 25), 1);
292 gpio_set_value(IMX_GPIO_NR(6, 27), 1);
293 gpio_set_value(IMX_GPIO_NR(6, 28), 1);
294 gpio_set_value(IMX_GPIO_NR(6, 29), 1);
d7140351 295 SETUP_IOMUX_PADS(enet_pads_ksz9031);
f0222902
OS		 296 gpio_set_value(IMX_GPIO_NR(6, 24), 1);
297 udelay(500);
298 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
d7140351 299 SETUP_IOMUX_PADS(enet_pads_final_ksz9031);
f0222902
OS		 300 } else if ((id1 == 0x004d) && (id2 == 0xd072)) {
301 /* configure Atheros AR8035 - actually nothing to do */
302 printf("configure Atheros AR8035 Ethernet Phy at address %d\n",
303 phydev->addr);
304 } else {
305 printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2);
306 ret = -EINVAL;
307 goto free_phydev;
308 }
309
310 ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
311 if (ret)
312 goto free_phydev;
313
314 return 0;
315
316free_phydev:
317 free(phydev);
318free_bus:
319 free(bus);
320 return ret;
321}
322
323int mx6_rgmii_rework(struct phy_device *phydev)
324{
325 unsigned short id1, id2;
326 unsigned short val;
327
328 /* check whether KSZ9031 or AR8035 has to be configured */
329 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
330 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
331
332 if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
333 /* finalize phy configuration for Micrel KSZ9031 */
334 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
335 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4);
336 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
337 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000);
338
339 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
340 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5);
341 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
342 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG);
343
344 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
345 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6);
346 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
347 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF);
348
349 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
350 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8);
351 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
352 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF);
353
354 /* fix KSZ9031 link up issue */
355 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0);
356 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4);
357 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
358 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6);
359 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG);
360 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3);
361 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
362 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80);
363 }
364
365 if ((id1 == 0x004d) && (id2 == 0xd072)) {
366 /* enable AR8035 ouput a 125MHz clk from CLK_25M */
367 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7);
368 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16);
369 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7);
370 val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA);
371 val &= 0xfe63;
372 val |= 0x18;
373 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val);
374
375 /* introduce tx clock delay */
376 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
377 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
378 val |= 0x0100;
379 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
380
381 /* disable hibernation */
382 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb);
383 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
384 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40);
385 }
386 return 0;
387}
388
389int board_phy_config(struct phy_device *phydev)
390{
391 mx6_rgmii_rework(phydev);
392
393 if (phydev->drv->config)
394 phydev->drv->config(phydev);
395
396 return 0;
397}
4c9929d6 398
9b75bad0
SL		 399static void setup_iomux_uart(void)
400{
d7140351 401 SETUP_IOMUX_PADS(uart2_pads);
9b75bad0
SL		 402}
403
71bcdafe
OS		 404#ifdef CONFIG_MXC_SPI
405static void setup_spi(void)
406{
a1ed1552 407 SETUP_IOMUX_PADS(ecspi1_pads);
71bcdafe
OS		 408 gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
409}
410#endif
411
9b75bad0 412#ifdef CONFIG_FSL_ESDHC
6b3496f7 413static struct fsl_esdhc_cfg usdhc_cfg[] = {
9b75bad0 414 {USDHC2_BASE_ADDR},
45e4d350 415 {USDHC3_BASE_ADDR},
9b75bad0
SL		 416 {USDHC4_BASE_ADDR},
417};
418
419int board_mmc_getcd(struct mmc *mmc)
420{
421 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
422 int ret = 0;
423
424 switch (cfg->esdhc_base) {
425 case USDHC2_BASE_ADDR:
426 gpio_direction_input(IMX_GPIO_NR(1, 4));
427 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
428 break;
45e4d350
OS		 429 case USDHC3_BASE_ADDR:
430 ret = 1; /* eMMC is always present */
431 break;
9b75bad0
SL		 432 case USDHC4_BASE_ADDR:
433 gpio_direction_input(IMX_GPIO_NR(2, 6));
434 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
435 break;
436 default:
437 printf("Bad USDHC interface\n");
438 }
439
440 return ret;
441}
442
443int board_mmc_init(bd_t *bis)
444{
d7140351 445#ifndef CONFIG_SPL_BUILD
9b75bad0 446 s32 status = 0;
516a863e 447 int i;
9b75bad0
SL		 448
449 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
45e4d350
OS		 450 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
451 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
9b75bad0 452
d7140351
OS		 453 SETUP_IOMUX_PADS(usdhc2_pads);
454 SETUP_IOMUX_PADS(usdhc3_pads);
455 SETUP_IOMUX_PADS(usdhc4_pads);
9b75bad0 456
516a863e
OS		 457 for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
458 status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
459 if (status)
460 return status;
461 }
9b75bad0 462
516a863e 463 return 0;
d7140351
OS		 464#else
465 SETUP_IOMUX_PADS(usdhc4_pads);
466 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
467 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
468 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
469
470 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
471#endif
9b75bad0
SL		 472}
473#endif
474
95246ac7
OS		 475int board_ehci_hcd_init(int port)
476{
477 switch (port) {
478 case 0:
d7140351 479 SETUP_IOMUX_PADS(usb_otg_pads);
95246ac7
OS		 480 /*
481 * set daisy chain for otg_pin_id on 6q.
482 * for 6dl, this bit is reserved
483 */
484 imx_iomux_set_gpr_register(1, 13, 1, 1);
485 break;
486 case 1:
487 /* nothing to do */
488 break;
489 default:
490 printf("Invalid USB port: %d\n", port);
491 return -EINVAL;
492 }
493
494 return 0;
495}
496
497int board_ehci_power(int port, int on)
498{
499 switch (port) {
500 case 0:
501 break;
502 case 1:
503 gpio_direction_output(IMX_GPIO_NR(5, 5), on);
504 break;
505 default:
506 printf("Invalid USB port: %d\n", port);
507 return -EINVAL;
508 }
509
510 return 0;
511}
512
6d551f27
OS		 513struct display_info_t {
514 int bus;
515 int addr;
516 int pixfmt;
517 int (*detect)(struct display_info_t const *dev);
518 void (*enable)(struct display_info_t const *dev);
519 struct fb_videomode mode;
520};
521
522static void disable_lvds(struct display_info_t const *dev)
523{
524 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
525
526 clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
527 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
528}
529
530static void do_enable_hdmi(struct display_info_t const *dev)
531{
532 disable_lvds(dev);
533 imx_enable_hdmi_phy();
534}
535
536static struct display_info_t const displays[] = {
537{
538 .bus = -1,
539 .addr = 0,
540 .pixfmt = IPU_PIX_FMT_RGB666,
541 .detect = NULL,
542 .enable = NULL,
543 .mode = {
544 .name =
545 "Hannstar-XGA",
546 .refresh = 60,
547 .xres = 1024,
548 .yres = 768,
549 .pixclock = 15385,
550 .left_margin = 220,
551 .right_margin = 40,
552 .upper_margin = 21,
553 .lower_margin = 7,
554 .hsync_len = 60,
555 .vsync_len = 10,
556 .sync = FB_SYNC_EXT,
557 .vmode = FB_VMODE_NONINTERLACED } },
558{
559 .bus = -1,
560 .addr = 0,
561 .pixfmt = IPU_PIX_FMT_RGB24,
562 .detect = NULL,
563 .enable = do_enable_hdmi,
564 .mode = {
565 .name = "HDMI",
566 .refresh = 60,
567 .xres = 1024,
568 .yres = 768,
569 .pixclock = 15385,
570 .left_margin = 220,
571 .right_margin = 40,
572 .upper_margin = 21,
573 .lower_margin = 7,
574 .hsync_len = 60,
575 .vsync_len = 10,
576 .sync = FB_SYNC_EXT,
577 .vmode = FB_VMODE_NONINTERLACED } }
578};
579
580int board_video_skip(void)
581{
582 int i;
583 int ret;
584 char const *panel = getenv("panel");
585 if (!panel) {
586 for (i = 0; i < ARRAY_SIZE(displays); i++) {
587 struct display_info_t const *dev = displays + i;
588 if (dev->detect && dev->detect(dev)) {
589 panel = dev->mode.name;
590 printf("auto-detected panel %s\n", panel);
591 break;
592 }
593 }
594 if (!panel) {
595 panel = displays[0].mode.name;
596 printf("No panel detected: default to %s\n", panel);
597 i = 0;
598 }
599 } else {
600 for (i = 0; i < ARRAY_SIZE(displays); i++) {
601 if (!strcmp(panel, displays[i].mode.name))
602 break;
603 }
604 }
605 if (i < ARRAY_SIZE(displays)) {
606 ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt);
607 if (!ret) {
608 if (displays[i].enable)
609 displays[i].enable(displays + i);
610 printf("Display: %s (%ux%u)\n",
611 displays[i].mode.name, displays[i].mode.xres,
612 displays[i].mode.yres);
613 } else
614 printf("LCD %s cannot be configured: %d\n",
615 displays[i].mode.name, ret);
616 } else {
617 printf("unsupported panel %s\n", panel);
618 return -EINVAL;
619 }
620
621 return 0;
622}
623
624static void setup_display(void)
625{
626 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
627 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
628 int reg;
629
630 enable_ipu_clock();
631 imx_setup_hdmi();
632
633 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
634 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK |
635 MXC_CCM_CCGR3_LDB_DI1_MASK);
636
637 /* set LDB0, LDB1 clk select to 011/011 */
638 reg = readl(&mxc_ccm->cs2cdr);
639 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
640 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
641 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
642 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
643 writel(reg, &mxc_ccm->cs2cdr);
644
645 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV |
646 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV);
647
648 setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
649 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET |
650 CHSCCDR_CLK_SEL_LDB_DI0 <<
651 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
652
653 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
654 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
655 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
656 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
657 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
658 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
659 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
660 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
661 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
662 writel(reg, &iomux->gpr[2]);
663
664 reg = readl(&iomux->gpr[3]);
665 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
666 IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
667 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
668 IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
669 writel(reg, &iomux->gpr[3]);
670}
671
672/*
673 * Do not overwrite the console
674 * Use always serial for U-Boot console
675 */
676int overwrite_console(void)
677{
678 return 1;
679}
680
9b75bad0
SL		 681int board_early_init_f(void)
682{
683 setup_iomux_uart();
6d551f27 684 setup_display();
9b75bad0 685
71bcdafe
OS		 686#ifdef CONFIG_MXC_SPI
687 setup_spi();
688#endif
9b75bad0
SL		 689 return 0;
690}
691
692int board_init(void)
693{
694 /* address of boot parameters */
695 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
696
d7140351 697
68c27601 698 if (is_mx6dq())
d7140351
OS		 699 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
700 else
701 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
4c9929d6 702
6731bc8d
OS		 703#ifdef CONFIG_CMD_SATA
704 setup_sata();
705#endif
706
9b75bad0
SL		 707 return 0;
708}
709
710int checkboard(void)
711{
d7140351
OS		 712 char *type = "unknown";
713
714 if (is_cpu_type(MXC_CPU_MX6Q))
715 type = "Quad";
716 else if (is_cpu_type(MXC_CPU_MX6D))
717 type = "Dual";
718 else if (is_cpu_type(MXC_CPU_MX6DL))
719 type = "Dual-Lite";
720 else if (is_cpu_type(MXC_CPU_MX6SOLO))
721 type = "Solo";
722
723 printf("Board: conga-QMX6 %s\n", type);
9b75bad0
SL		 724
725 return 0;
726}
727
71bcdafe
OS		 728#ifdef CONFIG_MXC_SPI
729int board_spi_cs_gpio(unsigned bus, unsigned cs)
730{
731 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL;
732}
733#endif
734
9b75bad0
SL		 735#ifdef CONFIG_CMD_BMODE
736static const struct boot_mode board_boot_modes[] = {
737 /* 4 bit bus width */
738 {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
739 {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
740 {NULL, 0},
741};
742#endif
743
744int misc_init_r(void)
745{
746#ifdef CONFIG_CMD_BMODE
747 add_board_boot_modes(board_boot_modes);
748#endif
749 return 0;
750}
d7140351
OS		 751
752int board_late_init(void)
753{
754#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
68c27601 755 if (is_mx6dq())
d7140351
OS		 756 setenv("board_rev", "MX6Q");
757 else
758 setenv("board_rev", "MX6DL");
759#endif
760
761 return 0;
762}
763
764#ifdef CONFIG_SPL_BUILD
765#include <asm/arch/mx6-ddr.h>
766#include <spl.h>
767#include <libfdt.h>
768#include <spi_flash.h>
769#include <spi.h>
770
771const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
772 .dram_sdclk_0 = 0x00000030,
773 .dram_sdclk_1 = 0x00000030,
774 .dram_cas = 0x00000030,
775 .dram_ras = 0x00000030,
776 .dram_reset = 0x00000030,
777 .dram_sdcke0 = 0x00003000,
778 .dram_sdcke1 = 0x00003000,
779 .dram_sdba2 = 0x00000000,
780 .dram_sdodt0 = 0x00000030,
781 .dram_sdodt1 = 0x00000030,
782 .dram_sdqs0 = 0x00000030,
783 .dram_sdqs1 = 0x00000030,
784 .dram_sdqs2 = 0x00000030,
785 .dram_sdqs3 = 0x00000030,
786 .dram_sdqs4 = 0x00000030,
787 .dram_sdqs5 = 0x00000030,
788 .dram_sdqs6 = 0x00000030,
789 .dram_sdqs7 = 0x00000030,
790 .dram_dqm0 = 0x00000030,
791 .dram_dqm1 = 0x00000030,
792 .dram_dqm2 = 0x00000030,
793 .dram_dqm3 = 0x00000030,
794 .dram_dqm4 = 0x00000030,
795 .dram_dqm5 = 0x00000030,
796 .dram_dqm6 = 0x00000030,
797 .dram_dqm7 = 0x00000030,
798};
799
800static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
801 .dram_sdclk_0 = 0x00000030,
802 .dram_sdclk_1 = 0x00000030,
803 .dram_cas = 0x00000030,
804 .dram_ras = 0x00000030,
805 .dram_reset = 0x00000030,
806 .dram_sdcke0 = 0x00003000,
807 .dram_sdcke1 = 0x00003000,
808 .dram_sdba2 = 0x00000000,
809 .dram_sdodt0 = 0x00000030,
810 .dram_sdodt1 = 0x00000030,
811 .dram_sdqs0 = 0x00000030,
812 .dram_sdqs1 = 0x00000030,
813 .dram_sdqs2 = 0x00000030,
814 .dram_sdqs3 = 0x00000030,
815 .dram_sdqs4 = 0x00000030,
816 .dram_sdqs5 = 0x00000030,
817 .dram_sdqs6 = 0x00000030,
818 .dram_sdqs7 = 0x00000030,
819 .dram_dqm0 = 0x00000030,
820 .dram_dqm1 = 0x00000030,
821 .dram_dqm2 = 0x00000030,
822 .dram_dqm3 = 0x00000030,
823 .dram_dqm4 = 0x00000030,
824 .dram_dqm5 = 0x00000030,
825 .dram_dqm6 = 0x00000030,
826 .dram_dqm7 = 0x00000030,
827};
828
829const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
830 .grp_ddr_type = 0x000C0000,
831 .grp_ddrmode_ctl = 0x00020000,
832 .grp_ddrpke = 0x00000000,
833 .grp_addds = 0x00000030,
834 .grp_ctlds = 0x00000030,
835 .grp_ddrmode = 0x00020000,
836 .grp_b0ds = 0x00000030,
837 .grp_b1ds = 0x00000030,
838 .grp_b2ds = 0x00000030,
839 .grp_b3ds = 0x00000030,
840 .grp_b4ds = 0x00000030,
841 .grp_b5ds = 0x00000030,
842 .grp_b6ds = 0x00000030,
843 .grp_b7ds = 0x00000030,
844};
845
846static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
847 .grp_ddr_type = 0x000c0000,
848 .grp_ddrmode_ctl = 0x00020000,
849 .grp_ddrpke = 0x00000000,
850 .grp_addds = 0x00000030,
851 .grp_ctlds = 0x00000030,
852 .grp_ddrmode = 0x00020000,
853 .grp_b0ds = 0x00000030,
854 .grp_b1ds = 0x00000030,
855 .grp_b2ds = 0x00000030,
856 .grp_b3ds = 0x00000030,
857 .grp_b4ds = 0x00000030,
858 .grp_b5ds = 0x00000030,
859 .grp_b6ds = 0x00000030,
860 .grp_b7ds = 0x00000030,
861};
862
863const struct mx6_mmdc_calibration mx6q_mmcd_calib = {
864 .p0_mpwldectrl0 = 0x0016001A,
865 .p0_mpwldectrl1 = 0x0023001C,
866 .p1_mpwldectrl0 = 0x0028003A,
867 .p1_mpwldectrl1 = 0x001F002C,
868 .p0_mpdgctrl0 = 0x43440354,
869 .p0_mpdgctrl1 = 0x033C033C,
870 .p1_mpdgctrl0 = 0x43300368,
871 .p1_mpdgctrl1 = 0x03500330,
872 .p0_mprddlctl = 0x3228242E,
873 .p1_mprddlctl = 0x2C2C2636,
874 .p0_mpwrdlctl = 0x36323A38,
875 .p1_mpwrdlctl = 0x42324440,
876};
877
878const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
879 .p0_mpwldectrl0 = 0x00080016,
880 .p0_mpwldectrl1 = 0x001D0016,
881 .p1_mpwldectrl0 = 0x0018002C,
882 .p1_mpwldectrl1 = 0x000D001D,
883 .p0_mpdgctrl0 = 0x43200334,
884 .p0_mpdgctrl1 = 0x0320031C,
885 .p1_mpdgctrl0 = 0x0344034C,
886 .p1_mpdgctrl1 = 0x03380314,
887 .p0_mprddlctl = 0x3E36383A,
888 .p1_mprddlctl = 0x38363240,
889 .p0_mpwrdlctl = 0x36364238,
890 .p1_mpwrdlctl = 0x4230423E,
891};
892
893static const struct mx6_mmdc_calibration mx6s_mmcd_calib = {
894 .p0_mpwldectrl0 = 0x00480049,
895 .p0_mpwldectrl1 = 0x00410044,
896 .p0_mpdgctrl0 = 0x42480248,
897 .p0_mpdgctrl1 = 0x023C023C,
898 .p0_mprddlctl = 0x40424644,
899 .p0_mpwrdlctl = 0x34323034,
900};
901
902const struct mx6_mmdc_calibration mx6dl_mmcd_calib = {
903 .p0_mpwldectrl0 = 0x0043004B,
904 .p0_mpwldectrl1 = 0x003A003E,
905 .p1_mpwldectrl0 = 0x0047004F,
906 .p1_mpwldectrl1 = 0x004E0061,
907 .p0_mpdgctrl0 = 0x42500250,
908 .p0_mpdgctrl1 = 0x0238023C,
909 .p1_mpdgctrl0 = 0x42640264,
910 .p1_mpdgctrl1 = 0x02500258,
911 .p0_mprddlctl = 0x40424846,
912 .p1_mprddlctl = 0x46484842,
913 .p0_mpwrdlctl = 0x38382C30,
914 .p1_mpwrdlctl = 0x34343430,
915};
916
917static struct mx6_ddr3_cfg mem_ddr_2g = {
918 .mem_speed = 1600,
919 .density = 2,
920 .width = 16,
921 .banks = 8,
922 .rowaddr = 14,
923 .coladdr = 10,
924 .pagesz = 2,
925 .trcd = 1310,
926 .trcmin = 4875,
927 .trasmin = 3500,
928};
929
930static struct mx6_ddr3_cfg mem_ddr_4g = {
931 .mem_speed = 1600,
932 .density = 4,
933 .width = 16,
934 .banks = 8,
935 .rowaddr = 15,
936 .coladdr = 10,
937 .pagesz = 2,
938 .trcd = 1310,
939 .trcmin = 4875,
940 .trasmin = 3500,
941};
942
943static void ccgr_init(void)
944{
945 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
946
947 writel(0x00C03F3F, &ccm->CCGR0);
948 writel(0x0030FC03, &ccm->CCGR1);
949 writel(0x0FFFC000, &ccm->CCGR2);
950 writel(0x3FF00000, &ccm->CCGR3);
951 writel(0x00FFF300, &ccm->CCGR4);
952 writel(0x0F0000C3, &ccm->CCGR5);
953 writel(0x000003FF, &ccm->CCGR6);
954}
955
956static void gpr_init(void)
957{
958 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
959
960 /* enable AXI cache for VDOA/VPU/IPU */
961 writel(0xF00000CF, &iomux->gpr[4]);
962 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
963 writel(0x007F007F, &iomux->gpr[6]);
964 writel(0x007F007F, &iomux->gpr[7]);
965}
966
967/* Define a minimal structure so that the part number can be read via SPL */
968struct mfgdata {
969 unsigned char tsize;
970 /* size of checksummed part in bytes */
971 unsigned char ckcnt;
972 /* checksum corrected byte */
973 unsigned char cksum;
974 /* decimal serial number, packed BCD */
975 unsigned char serial[6];
976 /* part number, right justified, ASCII */
977 unsigned char pn[16];
978};
979
980static void conv_ascii(unsigned char *dst, unsigned char *src, int len)
981{
982 int remain = len;
983 unsigned char *sptr = src;
984 unsigned char *dptr = dst;
985
986 while (remain) {
987 if (*sptr) {
988 *dptr = *sptr;
989 dptr++;
990 }
991 sptr++;
992 remain--;
993 }
994 *dptr = 0x0;
995}
996
997#define CFG_MFG_ADDR_OFFSET (spi->size - SZ_16K)
998static bool is_2gb(void)
999{
1000 struct spi_flash *spi;
1001 int ret;
1002 char buf[sizeof(struct mfgdata)];
1003 struct mfgdata *data = (struct mfgdata *)buf;
1004 unsigned char outbuf[32];
1005
1006 spi = spi_flash_probe(CONFIG_ENV_SPI_BUS,
1007 CONFIG_ENV_SPI_CS,
1008 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
1009 ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata),
1010 buf);
1011 if (ret)
1012 return false;
1013
1014 /* Congatec Part Numbers 104 and 105 have 2GiB of RAM */
1015 conv_ascii(outbuf, data->pn, sizeof(data->pn));
1016 if (!memcmp(outbuf, "016104", 6) || !memcmp(outbuf, "016105", 6))
1017 return true;
1018 else
1019 return false;
1020}
1021
1022static void spl_dram_init(int width)
1023{
1024 struct mx6_ddr_sysinfo sysinfo = {
1025 /* width of data bus:0=16,1=32,2=64 */
1026 .dsize = width / 32,
1027 /* config for full 4GB range so that get_mem_size() works */
1028 .cs_density = 32, /* 32Gb per CS */
1029 /* single chip select */
1030 .ncs = 1,
1031 .cs1_mirror = 0,
1032 .rtt_wr = 2,
1033 .rtt_nom = 2,
1034 .walat = 0,
1035 .ralat = 5,
1036 .mif3_mode = 3,
1037 .bi_on = 1,
1038 .sde_to_rst = 0x0d,
1039 .rst_to_cke = 0x20,
edf00937
FE		 1040 .refsel = 1, /* Refresh cycles at 32KHz */
1041 .refr = 7, /* 8 refresh commands per refresh cycle */
d7140351
OS		 1042 };
1043
1044 if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) {
1045 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
1046 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
1047 return;
1048 }
1049
68c27601 1050 if (is_mx6dq()) {
d7140351
OS		 1051 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
1052 mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
1053 } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
1054 sysinfo.walat = 1;
1055 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
1056 mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g);
1057 } else if (is_cpu_type(MXC_CPU_MX6DL)) {
1058 sysinfo.walat = 1;
1059 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
1060 mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g);
1061 }
1062}
1063
1064void board_init_f(ulong dummy)
1065{
1066 /* setup AIPS and disable watchdog */
1067 arch_cpu_init();
1068
1069 ccgr_init();
1070 gpr_init();
1071
1072 /* iomux and setup of i2c */
1073 board_early_init_f();
1074
1075 /* setup GP timer */
1076 timer_init();
1077
1078 /* UART clocks enabled and gd valid - init serial console */
1079 preloader_console_init();
1080
1081 /* Needed for malloc() to work in SPL prior to board_init_r() */
1082 spl_init();
1083
1084 /* DDR initialization */
1085 if (is_cpu_type(MXC_CPU_MX6SOLO))
1086 spl_dram_init(32);
1087 else
1088 spl_dram_init(64);
1089
1090 /* Clear the BSS. */
1091 memset(__bss_start, 0, __bss_end - __bss_start);
1092
1093 /* load/boot image from boot device */
1094 board_init_r(NULL, 0);
1095}
1096#endif
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