[people/ms/u-boot.git] / board / cu824 / flash.c

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc824x.h>
#include <asm/processor.h>

#if defined(CONFIG_ENV_IS_IN_FLASH)
# ifndef  CONFIG_ENV_ADDR
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
# endif
# ifndef  CONFIG_ENV_SIZE
#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
# endif
# ifndef  CONFIG_ENV_SECT_SIZE
#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
# endif
#endif

#define FLASH_BANK_SIZE 0x800000
#define MAIN_SECT_SIZE  0x40000
#define PARAM_SECT_SIZE 0x8000

#define BOARD_CTRL_REG 0xFE800013

flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];

static int write_data (flash_info_t *info, ulong dest, ulong *data);
static void write_via_fpu(vu_long *addr, ulong *data);
static __inline__ unsigned long get_msr(void);
static __inline__ void set_msr(unsigned long msr);

/*---------------------------------------------------------------------*/
#undef	DEBUG_FLASH

/*---------------------------------------------------------------------*/
#ifdef DEBUG_FLASH
#define DEBUGF(fmt,args...) printf(fmt ,##args)
#else
#define DEBUGF(fmt,args...)
#endif
/*---------------------------------------------------------------------*/

/*-----------------------------------------------------------------------
 */

unsigned long flash_init(void)
{
    int i, j;
    ulong size = 0;
    volatile unsigned char *bcr = (volatile unsigned char *)(BOARD_CTRL_REG);

    DEBUGF("Write protect was: 0x%02X\n", *bcr);
    *bcr &= 0x1;	/* FWPT must be 0  */
    *bcr |= 0x6;	/* FWP0 = FWP1 = 1 */
    DEBUGF("Write protect is:  0x%02X\n", *bcr);

    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
	vu_long *addr = (vu_long *)(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE);

	addr[0] = 0x00900090;

	DEBUGF ("Flash bank # %d:\n"
		"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
		"\tDevice ID @ 0x%08lX: 0x%08lX\n",
		i,
		(ulong)(&addr[0]), addr[0],
		(ulong)(&addr[2]), addr[2]);

	if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
	    (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3B))
	{
	    flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) |
				     (INTEL_ID_28F160F3B & FLASH_TYPEMASK);
	} else {
	    flash_info[i].flash_id = FLASH_UNKNOWN;
	    addr[0] = 0xFFFFFFFF;
	    goto Done;
	}

	DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);

	addr[0] = 0xFFFFFFFF;

	flash_info[i].size = FLASH_BANK_SIZE;
	flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
	memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
	for (j = 0; j < flash_info[i].sector_count; j++) {
		if (j <= 7) {
			flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
						 i * FLASH_BANK_SIZE +
						 j * PARAM_SECT_SIZE;
		} else {
			flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
						 i * FLASH_BANK_SIZE +
						 (j - 7)*MAIN_SECT_SIZE;
		}
	}
	size += flash_info[i].size;
    }

    /* Protect monitor and environment sectors
     */
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
    flash_protect(FLAG_PROTECT_SET,
	      CONFIG_SYS_MONITOR_BASE,
	      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
	      &flash_info[1]);
#else
    flash_protect(FLAG_PROTECT_SET,
	      CONFIG_SYS_MONITOR_BASE,
	      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
	      &flash_info[0]);
#endif
#endif

#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
    flash_protect(FLAG_PROTECT_SET,
	      CONFIG_ENV_ADDR,
	      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
	      &flash_info[1]);
#else
    flash_protect(FLAG_PROTECT_SET,
	      CONFIG_ENV_ADDR,
	      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
	      &flash_info[0]);
#endif
#endif

Done:
    return size;
}

/*-----------------------------------------------------------------------
 */
void flash_print_info (flash_info_t * info)
{
	int i;

	switch ((i = info->flash_id & FLASH_VENDMASK)) {
	case (FLASH_MAN_INTEL & FLASH_VENDMASK):
		printf ("Intel: ");
		break;
	default:
		printf ("Unknown Vendor 0x%04x ", i);
		break;
	}

	switch ((i = info->flash_id & FLASH_TYPEMASK)) {
	case (INTEL_ID_28F160F3B & FLASH_TYPEMASK):
		printf ("28F160F3B (16Mbit)\n");
		break;
	default:
		printf ("Unknown Chip Type 0x%04x\n", i);
		goto Done;
		break;
	}

	printf ("  Size: %ld MB in %d Sectors\n",
			info->size >> 20, info->sector_count);

	printf ("  Sector Start Addresses:");
	for (i = 0; i < info->sector_count; i++) {
		if ((i % 5) == 0) {
			printf ("\n   ");
		}
		printf (" %08lX%s", info->start[i],
				info->protect[i] ? " (RO)" : "     ");
	}
	printf ("\n");

Done:
	return;
}

/*-----------------------------------------------------------------------
 */

int	flash_erase (flash_info_t *info, int s_first, int s_last)
{
	int flag, prot, sect;
	ulong start, now, last;

	DEBUGF ("Erase flash bank %d sect %d ... %d\n",
		info - &flash_info[0], s_first, s_last);

	if ((s_first < 0) || (s_first > s_last)) {
		if (info->flash_id == FLASH_UNKNOWN) {
			printf ("- missing\n");
		} else {
			printf ("- no sectors to erase\n");
		}
		return 1;
	}

	if ((info->flash_id & FLASH_VENDMASK) !=
	    (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
		printf ("Can erase only Intel flash types - aborted\n");
		return 1;
	}

	prot = 0;
	for (sect=s_first; sect<=s_last; ++sect) {
		if (info->protect[sect]) {
			prot++;
		}
	}

	if (prot) {
		printf ("- Warning: %d protected sectors will not be erased!\n",
			prot);
	} else {
		printf ("\n");
	}

	start = get_timer (0);
	last  = start;
	/* Start erase on unprotected sectors */
	for (sect = s_first; sect<=s_last; sect++) {
		if (info->protect[sect] == 0) {	/* not protected */
			vu_long *addr = (vu_long *)(info->start[sect]);

			DEBUGF ("Erase sect %d @ 0x%08lX\n",
				sect, (ulong)addr);

			/* Disable interrupts which might cause a timeout
			 * here.
			 */
			flag = disable_interrupts();

			addr[0] = 0x00500050;	/* clear status register */
			addr[0] = 0x00200020;	/* erase setup */
			addr[0] = 0x00D000D0;	/* erase confirm */

			addr[1] = 0x00500050;	/* clear status register */
			addr[1] = 0x00200020;	/* erase setup */
			addr[1] = 0x00D000D0;	/* erase confirm */

			/* re-enable interrupts if necessary */
			if (flag)
				enable_interrupts();

			/* wait at least 80us - let's wait 1 ms */
			udelay (1000);

			while (((addr[0] & 0x00800080) != 0x00800080) ||
			       ((addr[1] & 0x00800080) != 0x00800080) ) {
				if ((now=get_timer(start)) >
					   CONFIG_SYS_FLASH_ERASE_TOUT) {
					printf ("Timeout\n");
					addr[0] = 0x00B000B0; /* suspend erase */
					addr[0] = 0x00FF00FF; /* to read mode  */
					return 1;
				}

				/* show that we're waiting */
				if ((now - last) > 1000) {  /* every second  */
					putc ('.');
					last = now;
				}
			}

			addr[0] = 0x00FF00FF;
		}
	}
	printf (" done\n");
	return 0;
}

/*-----------------------------------------------------------------------
 * Copy memory to flash, returns:
 * 0 - OK
 * 1 - write timeout
 * 2 - Flash not erased
 * 4 - Flash not identified
 */

#define	FLASH_WIDTH	8	/* flash bus width in bytes */

int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
	ulong wp, cp, msr;
	int l, rc, i;
	ulong data[2];
	ulong *datah = &data[0];
	ulong *datal = &data[1];

	DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
		addr, (ulong)src, cnt);

	if (info->flash_id == FLASH_UNKNOWN) {
		return 4;
	}

	msr = get_msr();
	set_msr(msr | MSR_FP);

	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower aligned address */

	/*
	 * handle unaligned start bytes
	 */
	if ((l = addr - wp) != 0) {
		*datah = *datal = 0;

		for (i = 0, cp = wp; i < l; i++, cp++) {
			if (i >= 4) {
				*datah = (*datah << 8) |
						((*datal & 0xFF000000) >> 24);
			}

			*datal = (*datal << 8) | (*(uchar *)cp);
		}
		for (; i < FLASH_WIDTH && cnt > 0; ++i) {
			char tmp;

			tmp = *src;

			src++;

			if (i >= 4) {
				*datah = (*datah << 8) |
						((*datal & 0xFF000000) >> 24);
			}

			*datal = (*datal << 8) | tmp;

			--cnt; ++cp;
		}

		for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
			if (i >= 4) {
				*datah = (*datah << 8) |
						((*datal & 0xFF000000) >> 24);
			}

			*datal = (*datah << 8) | (*(uchar *)cp);
		}

		if ((rc = write_data(info, wp, data)) != 0) {
			set_msr(msr);
			return (rc);
		}

		wp += FLASH_WIDTH;
	}

	/*
	 * handle FLASH_WIDTH aligned part
	 */
	while (cnt >= FLASH_WIDTH) {
		*datah = *(ulong *)src;
		*datal = *(ulong *)(src + 4);
		if ((rc = write_data(info, wp, data)) != 0) {
			set_msr(msr);
			return (rc);
		}
		wp  += FLASH_WIDTH;
		cnt -= FLASH_WIDTH;
		src += FLASH_WIDTH;
	}

	if (cnt == 0) {
		set_msr(msr);
		return (0);
	}

	/*
	 * handle unaligned tail bytes
	 */
	*datah = *datal = 0;
	for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
		char tmp;

		tmp = *src;

		src++;

		if (i >= 4) {
			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
		}

		*datal = (*datal << 8) | tmp;

		--cnt;
	}

	for (; i < FLASH_WIDTH; ++i, ++cp) {
		if (i >= 4) {
			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
		}

		*datal = (*datal << 8) | (*(uchar *)cp);
	}

	rc = write_data(info, wp, data);
	set_msr(msr);

	return (rc);
}

/*-----------------------------------------------------------------------
 * Write a word to Flash, returns:
 * 0 - OK
 * 1 - write timeout
 * 2 - Flash not erased
 */
static int write_data (flash_info_t *info, ulong dest, ulong *data)
{
	vu_long *addr = (vu_long *)dest;
	ulong start;
	int flag;

	/* Check if Flash is (sufficiently) erased */
	if (((addr[0] & data[0]) != data[0]) ||
	    ((addr[1] & data[1]) != data[1]) ) {
		return (2);
	}
	/* Disable interrupts which might cause a timeout here */
	flag = disable_interrupts();

	addr[0] = 0x00400040;		/* write setup */
	write_via_fpu(addr, data);

	/* re-enable interrupts if necessary */
	if (flag)
		enable_interrupts();

	start = get_timer (0);

	while (((addr[0] & 0x00800080) != 0x00800080) ||
	       ((addr[1] & 0x00800080) != 0x00800080) ) {
		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
			addr[0] = 0x00FF00FF;	/* restore read mode */
			return (1);
		}
	}

	addr[0] = 0x00FF00FF;	/* restore read mode */

	return (0);
}

/*-----------------------------------------------------------------------
 */
static void write_via_fpu(vu_long *addr, ulong *data)
{
	__asm__ __volatile__ ("lfd  1, 0(%0)" : : "r" (data));
	__asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
}
/*-----------------------------------------------------------------------
 */
static __inline__ unsigned long get_msr(void)
{
    unsigned long msr;

    __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
    return msr;
}

static __inline__ void set_msr(unsigned long msr)
{
    __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
}
Commit	Line	Data
affae2bf WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
affae2bf WD	6	*/
	7
	8	#include <common.h>
	9	#include <mpc824x.h>
	10	#include <asm/processor.h>
	11
5a1aceb0	12	#if defined(CONFIG_ENV_IS_IN_FLASH)
0e8d1586	13	# ifndef CONFIG_ENV_ADDR
6d0f6bcf	14	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
affae2bf	15	# endif
0e8d1586 JCPV	16	# ifndef CONFIG_ENV_SIZE
0e8d1586 JCPV	17	# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
affae2bf	18	# endif
0e8d1586 JCPV	19	# ifndef CONFIG_ENV_SECT_SIZE
0e8d1586 JCPV	20	# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
affae2bf WD	21	# endif
	22	#endif
	23
	24	#define FLASH_BANK_SIZE 0x800000
	25	#define MAIN_SECT_SIZE 0x40000
	26	#define PARAM_SECT_SIZE 0x8000
	27
	28	#define BOARD_CTRL_REG 0xFE800013
	29
6d0f6bcf	30	flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
affae2bf WD	31
	32	static int write_data (flash_info_t info, ulong dest, ulong data);
	33	static void write_via_fpu(vu_long addr, ulong data);
	34	static __inline__ unsigned long get_msr(void);
	35	static __inline__ void set_msr(unsigned long msr);
	36
	37	/---------------------------------------------------------------------/
	38	#undef DEBUG_FLASH
	39
	40	/---------------------------------------------------------------------/
	41	#ifdef DEBUG_FLASH
	42	#define DEBUGF(fmt,args...) printf(fmt ,##args)
	43	#else
	44	#define DEBUGF(fmt,args...)
	45	#endif
	46	/---------------------------------------------------------------------/
	47
	48	/*-----------------------------------------------------------------------
	49	*/
	50
	51	unsigned long flash_init(void)
	52	{
	53	int i, j;
	54	ulong size = 0;
	55	volatile unsigned char bcr = (volatile unsigned char )(BOARD_CTRL_REG);
	56
	57	DEBUGF("Write protect was: 0x%02X\n", *bcr);
	58	bcr &= 0x1; / FWPT must be 0 */
	59	bcr \|= 0x6; / FWP0 = FWP1 = 1 */
	60	DEBUGF("Write protect is: 0x%02X\n", *bcr);
	61
6d0f6bcf JCPV	62	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
6d0f6bcf JCPV	63	vu_long addr = (vu_long )(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE);
affae2bf WD	64
	65	addr[0] = 0x00900090;
	66
	67	DEBUGF ("Flash bank # %d:\n"
	68	"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
	69	"\tDevice ID @ 0x%08lX: 0x%08lX\n",
	70	i,
	71	(ulong)(&addr[0]), addr[0],
	72	(ulong)(&addr[2]), addr[2]);
	73
	74	if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
	75	(addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3B))
	76	{
	77	flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) \|
8bde7f77	78	(INTEL_ID_28F160F3B & FLASH_TYPEMASK);
affae2bf WD	79	} else {
	80	flash_info[i].flash_id = FLASH_UNKNOWN;
	81	addr[0] = 0xFFFFFFFF;
	82	goto Done;
	83	}
	84
	85	DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
	86
	87	addr[0] = 0xFFFFFFFF;
	88
	89	flash_info[i].size = FLASH_BANK_SIZE;
6d0f6bcf JCPV	90	flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
6d0f6bcf JCPV	91	memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
affae2bf WD	92	for (j = 0; j < flash_info[i].sector_count; j++) {
affae2bf WD	93	if (j <= 7) {
6d0f6bcf	94	flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
8bde7f77 WD	95	i * FLASH_BANK_SIZE +
8bde7f77 WD	96	j * PARAM_SECT_SIZE;
affae2bf	97	} else {
6d0f6bcf	98	flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
8bde7f77 WD	99	i * FLASH_BANK_SIZE +
8bde7f77 WD	100	(j - 7)*MAIN_SECT_SIZE;
affae2bf WD	101	}
	102	}
	103	size += flash_info[i].size;
	104	}
	105
	106	/* Protect monitor and environment sectors
	107	*/
6d0f6bcf JCPV	108	#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	109	#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
affae2bf	110	flash_protect(FLAG_PROTECT_SET,
6d0f6bcf JCPV	111	CONFIG_SYS_MONITOR_BASE,
6d0f6bcf JCPV	112	CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
8bde7f77	113	&flash_info[1]);
affae2bf WD	114	#else
affae2bf WD	115	flash_protect(FLAG_PROTECT_SET,
6d0f6bcf JCPV	116	CONFIG_SYS_MONITOR_BASE,
6d0f6bcf JCPV	117	CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
8bde7f77	118	&flash_info[0]);
affae2bf WD	119	#endif
	120	#endif
	121
0e8d1586	122	#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
6d0f6bcf	123	#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
affae2bf	124	flash_protect(FLAG_PROTECT_SET,
0e8d1586 JCPV	125	CONFIG_ENV_ADDR,
0e8d1586 JCPV	126	CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
8bde7f77	127	&flash_info[1]);
affae2bf WD	128	#else
affae2bf WD	129	flash_protect(FLAG_PROTECT_SET,
0e8d1586 JCPV	130	CONFIG_ENV_ADDR,
0e8d1586 JCPV	131	CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
8bde7f77	132	&flash_info[0]);
affae2bf WD	133	#endif
	134	#endif
	135
	136	Done:
	137	return size;
	138	}
	139
	140	/*-----------------------------------------------------------------------
	141	*/
	142	void flash_print_info (flash_info_t * info)
	143	{
	144	int i;
	145
	146	switch ((i = info->flash_id & FLASH_VENDMASK)) {
	147	case (FLASH_MAN_INTEL & FLASH_VENDMASK):
	148	printf ("Intel: ");
	149	break;
	150	default:
	151	printf ("Unknown Vendor 0x%04x ", i);
	152	break;
	153	}
	154
	155	switch ((i = info->flash_id & FLASH_TYPEMASK)) {
	156	case (INTEL_ID_28F160F3B & FLASH_TYPEMASK):
	157	printf ("28F160F3B (16Mbit)\n");
	158	break;
	159	default:
	160	printf ("Unknown Chip Type 0x%04x\n", i);
	161	goto Done;
	162	break;
	163	}
	164
	165	printf (" Size: %ld MB in %d Sectors\n",
	166	info->size >> 20, info->sector_count);
	167
	168	printf (" Sector Start Addresses:");
	169	for (i = 0; i < info->sector_count; i++) {
	170	if ((i % 5) == 0) {
	171	printf ("\n ");
	172	}
	173	printf (" %08lX%s", info->start[i],
	174	info->protect[i] ? " (RO)" : " ");
	175	}
	176	printf ("\n");
	177
	178	Done:
	179	return;
	180	}
	181
	182	/*-----------------------------------------------------------------------
	183	*/
	184
	185	int flash_erase (flash_info_t *info, int s_first, int s_last)
	186	{
	187	int flag, prot, sect;
	188	ulong start, now, last;
	189
	190	DEBUGF ("Erase flash bank %d sect %d ... %d\n",
	191	info - &flash_info[0], s_first, s_last);
	192
	193	if ((s_first < 0) \|\| (s_first > s_last)) {
	194	if (info->flash_id == FLASH_UNKNOWN) {
	195	printf ("- missing\n");
	196	} else {
197	printf ("- no sectors to erase\n");
198	}
199	return 1;
200	}
201
202	if ((info->flash_id & FLASH_VENDMASK) !=
203	(FLASH_MAN_INTEL & FLASH_VENDMASK)) {
204	printf ("Can erase only Intel flash types - aborted\n");
205	return 1;
206	}
207
208	prot = 0;
209	for (sect=s_first; sect<=s_last; ++sect) {
210	if (info->protect[sect]) {
211	prot++;
212	}
213	}
214
215	if (prot) {
216	printf ("- Warning: %d protected sectors will not be erased!\n",
217	prot);
218	} else {
219	printf ("\n");
220	}
221
222	start = get_timer (0);
223	last = start;
224	/* Start erase on unprotected sectors */
225	for (sect = s_first; sect<=s_last; sect++) {
226	if (info->protect[sect] == 0) { /* not protected */
227	vu_long addr = (vu_long )(info->start[sect]);
228
229	DEBUGF ("Erase sect %d @ 0x%08lX\n",
230	sect, (ulong)addr);
231
232	/* Disable interrupts which might cause a timeout
233	* here.
234	*/
235	flag = disable_interrupts();
236
237	addr[0] = 0x00500050; /* clear status register */
238	addr[0] = 0x00200020; /* erase setup */
239	addr[0] = 0x00D000D0; /* erase confirm */
240
241	addr[1] = 0x00500050; /* clear status register */
242	addr[1] = 0x00200020; /* erase setup */
243	addr[1] = 0x00D000D0; /* erase confirm */
244
245	/* re-enable interrupts if necessary */
246	if (flag)
247	enable_interrupts();
248
249	/* wait at least 80us - let's wait 1 ms */
250	udelay (1000);
251
252	while (((addr[0] & 0x00800080) != 0x00800080) \|\|
253	((addr[1] & 0x00800080) != 0x00800080) ) {
254	if ((now=get_timer(start)) >
6d0f6bcf	255	CONFIG_SYS_FLASH_ERASE_TOUT) {
affae2bf WD	256	printf ("Timeout\n");
	257	addr[0] = 0x00B000B0; /* suspend erase */
	258	addr[0] = 0x00FF00FF; /* to read mode */
	259	return 1;
	260	}
	261
	262	/* show that we're waiting */
	263	if ((now - last) > 1000) { /* every second */
	264	putc ('.');
	265	last = now;
	266	}
	267	}
	268
	269	addr[0] = 0x00FF00FF;
	270	}
	271	}
	272	printf (" done\n");
	273	return 0;
	274	}
	275
	276	/*-----------------------------------------------------------------------
	277	* Copy memory to flash, returns:
	278	* 0 - OK
	279	* 1 - write timeout
	280	* 2 - Flash not erased
	281	* 4 - Flash not identified
	282	*/
	283
	284	#define FLASH_WIDTH 8 /* flash bus width in bytes */
	285
	286	int write_buff (flash_info_t info, uchar src, ulong addr, ulong cnt)
	287	{
	288	ulong wp, cp, msr;
	289	int l, rc, i;
	290	ulong data[2];
	291	ulong *datah = &data[0];
	292	ulong *datal = &data[1];
	293
	294	DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
	295	addr, (ulong)src, cnt);
	296
	297	if (info->flash_id == FLASH_UNKNOWN) {
	298	return 4;
	299	}
	300
	301	msr = get_msr();
	302	set_msr(msr \| MSR_FP);
	303
	304	wp = (addr & ~(FLASH_WIDTH-1)); /* get lower aligned address */
	305
	306	/*
	307	* handle unaligned start bytes
	308	*/
	309	if ((l = addr - wp) != 0) {
	310	datah = datal = 0;
	311
	312	for (i = 0, cp = wp; i < l; i++, cp++) {
	313	if (i >= 4) {
	314	datah = (datah << 8) \|
8bde7f77	315	((*datal & 0xFF000000) >> 24);
affae2bf WD	316	}
	317
	318	datal = (datal << 8) \| ((uchar )cp);
	319	}
	320	for (; i < FLASH_WIDTH && cnt > 0; ++i) {
	321	char tmp;
	322
	323	tmp = *src;
	324
	325	src++;
	326
	327	if (i >= 4) {
	328	datah = (datah << 8) \|
8bde7f77	329	((*datal & 0xFF000000) >> 24);
affae2bf WD	330	}
	331
	332	datal = (datal << 8) \| tmp;
	333
	334	--cnt; ++cp;
	335	}
	336
	337	for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
	338	if (i >= 4) {
	339	datah = (datah << 8) \|
8bde7f77	340	((*datal & 0xFF000000) >> 24);
affae2bf WD	341	}
	342
	343	datal = (datah << 8) \| ((uchar )cp);
	344	}
	345
	346	if ((rc = write_data(info, wp, data)) != 0) {
	347	set_msr(msr);
	348	return (rc);
	349	}
	350
	351	wp += FLASH_WIDTH;
	352	}
	353
	354	/*
	355	* handle FLASH_WIDTH aligned part
	356	*/
	357	while (cnt >= FLASH_WIDTH) {
	358	datah = (ulong *)src;
	359	datal = (ulong *)(src + 4);
	360	if ((rc = write_data(info, wp, data)) != 0) {
	361	set_msr(msr);
	362	return (rc);
	363	}
	364	wp += FLASH_WIDTH;
	365	cnt -= FLASH_WIDTH;
	366	src += FLASH_WIDTH;
	367	}
	368
	369	if (cnt == 0) {
	370	set_msr(msr);
	371	return (0);
	372	}
	373
	374	/*
	375	* handle unaligned tail bytes
	376	*/
	377	datah = datal = 0;
	378	for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
	379	char tmp;
	380
8bde7f77	381	tmp = *src;
affae2bf WD	382
	383	src++;
	384
	385	if (i >= 4) {
	386	datah = (datah << 8) \| ((*datal & 0xFF000000) >> 24);
	387	}
	388
	389	datal = (datal << 8) \| tmp;
	390
	391	--cnt;
	392	}
	393
	394	for (; i < FLASH_WIDTH; ++i, ++cp) {
	395	if (i >= 4) {
	396	datah = (datah << 8) \| ((*datal & 0xFF000000) >> 24);
	397	}
	398
	399	datal = (datal << 8) \| ((uchar )cp);
	400	}
	401
	402	rc = write_data(info, wp, data);
	403	set_msr(msr);
	404
	405	return (rc);
	406	}
	407
	408	/*-----------------------------------------------------------------------
	409	* Write a word to Flash, returns:
	410	* 0 - OK
	411	* 1 - write timeout
	412	* 2 - Flash not erased
	413	*/
	414	static int write_data (flash_info_t info, ulong dest, ulong data)
	415	{
	416	vu_long addr = (vu_long )dest;
	417	ulong start;
	418	int flag;
	419
	420	/* Check if Flash is (sufficiently) erased */
	421	if (((addr[0] & data[0]) != data[0]) \|\|
	422	((addr[1] & data[1]) != data[1]) ) {
	423	return (2);
	424	}
	425	/* Disable interrupts which might cause a timeout here */
	426	flag = disable_interrupts();
	427
	428	addr[0] = 0x00400040; /* write setup */
	429	write_via_fpu(addr, data);
	430
	431	/* re-enable interrupts if necessary */
	432	if (flag)
	433	enable_interrupts();
	434
	435	start = get_timer (0);
	436
	437	while (((addr[0] & 0x00800080) != 0x00800080) \|\|
	438	((addr[1] & 0x00800080) != 0x00800080) ) {
6d0f6bcf	439	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
affae2bf WD	440	addr[0] = 0x00FF00FF; /* restore read mode */
	441	return (1);
	442	}
	443	}
	444
	445	addr[0] = 0x00FF00FF; /* restore read mode */
	446
	447	return (0);
	448	}
	449
	450	/*-----------------------------------------------------------------------
	451	*/
	452	static void write_via_fpu(vu_long addr, ulong data)
	453	{
	454	__asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data));
	455	__asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
	456	}
	457	/*-----------------------------------------------------------------------
	458	*/
	459	static __inline__ unsigned long get_msr(void)
	460	{
	461	unsigned long msr;
	462
	463	__asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
	464	return msr;
	465	}
	466
	467	static __inline__ void set_msr(unsigned long msr)
	468	{
	469	__asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
	470	}