[people/ms/u-boot.git] / board / dave / PPChameleonEVB / PPChameleonEVB.c

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>

/* ------------------------------------------------------------------------- */

#if 0
#define FPGA_DEBUG
#endif

/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
{
#include "fpgadata.c"
};

/*
 * include common fpga code (for esd boards)
 */
#include "../common/fpga.c"


/* Prototypes */
int gunzip(void *, int, unsigned char *, int *);


int board_pre_init (void)
{
	out32(GPIO0_OR, CFG_NAND0_CE);                 /* set initial outputs     */
        out32(GPIO0_OR, CFG_NAND1_CE);                 /* set initial outputs     */

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	 */
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
	mtdcr(uicer, 0x00000000);       /* disable all ints */
	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */

	/*
	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	 */
#if 1 /* test-only */
	mtebc (epcr, 0xa8400000); /* ebc always driven */
#else
	mtebc (epcr, 0x28400000); /* ebc in high-z */
#endif

	return 0;
}


/* ------------------------------------------------------------------------- */

int misc_init_f (void)
{
	return 0;  /* dummy implementation */
}


int misc_init_r (void)
{
#if 0 /* test-only */
	DECLARE_GLOBAL_DATA_PTR;
#if 0
	volatile unsigned short *fpga_mode =
		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
	volatile unsigned char *duart0_mcr =
		(unsigned char *)((ulong)DUART0_BA + 4);
	volatile unsigned char *duart1_mcr =
		(unsigned char *)((ulong)DUART1_BA + 4);

	bd_t *bd = gd->bd;
	char *	tmp;                    /* Temporary char pointer      */
	unsigned char *dst;
	ulong len = sizeof(fpgadata);
	int status;
	int index;
	int i;
	unsigned long cntrl0Reg;

	dst = malloc(CFG_FPGA_MAX_SIZE);
	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
		printf ("GUNZIP ERROR - must RESET board to recover\n");
		do_reset (NULL, 0, 0, NULL);
	}

	status = fpga_boot(dst, len);
	if (status != 0) {
		printf("\nFPGA: Booting failed ");
		switch (status) {
		case ERROR_FPGA_PRG_INIT_LOW:
			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_INIT_HIGH:
			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_DONE:
			printf("(Timeout: DONE not high after programming FPGA)\n ");
			break;
		}

		/* display infos on fpgaimage */
		index = 15;
		for (i=0; i<4; i++) {
			len = dst[index];
			printf("FPGA: %s\n", &(dst[index+1]));
			index += len+3;
		}
		putc ('\n');
		/* delayed reboot */
		for (i=20; i>0; i--) {
			printf("Rebooting in %2d seconds \r",i);
			for (index=0;index<1000;index++)
				udelay(1000);
		}
		putc ('\n');
		do_reset(NULL, 0, 0, NULL);
	}

	puts("FPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i=0; i<4; i++) {
		len = dst[index];
		printf("%s ", &(dst[index+1]));
		index += len+3;
	}
	putc ('\n');

	free(dst);

	/*
	 * Reset FPGA via FPGA_DATA pin
	 */
	SET_FPGA(FPGA_PRG | FPGA_CLK);
	udelay(1000); /* wait 1ms */
	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
	udelay(1000); /* wait 1ms */

#endif

#if 0
	/*
	 * Enable power on PS/2 interface
	 */
	*fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;

	/*
	 * Enable interrupts in exar duart mcr[3]
	 */
	*duart0_mcr = 0x08;
	*duart1_mcr = 0x08;
#endif
#endif

	return (0);
}


/*
 * Check Board Identity:
 */

int checkboard (void)
{
	unsigned char str[64];
	int i = getenv_r ("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming PPChameleonEVB");
	} else {
		puts(str);
	}

	putc ('\n');

	return 0;
}

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
	unsigned long val;

	mtdcr(memcfga, mem_mb0cf);
	val = mfdcr(memcfgd);

#if 0 /* test-only */
	for (;;) {
		NAND_DISABLE_CE(1);
		udelay(100);
		NAND_ENABLE_CE(1);
		udelay(100);
	}
#endif
#if 0
	printf("\nmb0cf=%x\n", val); /* test-only */
	printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif

	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}

/* ------------------------------------------------------------------------- */

int testdram (void)
{
	/* TODO: XXX XXX XXX */
	printf ("test: 16 MB - ok\n");

	return (0);
}

/* ------------------------------------------------------------------------- */

#if (CONFIG_COMMANDS & CFG_CMD_NAND)
extern ulong
nand_probe(ulong physadr);

void
nand_init(void)
{
	ulong totlen;

	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
	totlen = nand_probe (CFG_NAND0_BASE);

	debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
	totlen += nand_probe (CFG_NAND1_BASE);

	printf ("%4lu MB\n", totlen >>20);
}
#endif
Commit	Line	Data
12f34241 WD	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <command.h>
	27	#include <malloc.h>
	28
	29	/* ------------------------------------------------------------------------- */
	30
	31	#if 0
	32	#define FPGA_DEBUG
	33	#endif
	34
	35	/* fpga configuration data - gzip compressed and generated by bin2c */
	36	const unsigned char fpgadata[] =
	37	{
	38	#include "fpgadata.c"
	39	};
	40
	41	/*
	42	* include common fpga code (for esd boards)
	43	*/
	44	#include "../common/fpga.c"
	45
	46
	47	/* Prototypes */
	48	int gunzip(void , int, unsigned char , int *);
	49
	50
	51	int board_pre_init (void)
	52	{
	53	out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */
	54	out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
	55
	56	/*
	57	* IRQ 0-15 405GP internally generated; active high; level sensitive
	58	* IRQ 16 405GP internally generated; active low; level sensitive
	59	* IRQ 17-24 RESERVED
	60	* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	61	* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	62	* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	63	* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	64	* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
65	* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
66	* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
67	*/
68	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
69	mtdcr(uicer, 0x00000000); /* disable all ints */
70	mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
71	mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
72	mtdcr(uictr, 0x10000000); /* set int trigger levels */
73	mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
74	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
75
76	/*
77	* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
78	*/
79	#if 1 /* test-only */
80	mtebc (epcr, 0xa8400000); /* ebc always driven */
81	#else
82	mtebc (epcr, 0x28400000); /* ebc in high-z */
83	#endif
84
85	return 0;
86	}
87
88
89	/* ------------------------------------------------------------------------- */
90
91	int misc_init_f (void)
92	{
93	return 0; /* dummy implementation */
94	}
95
96
97	int misc_init_r (void)
98	{
99	#if 0 /* test-only */
100	DECLARE_GLOBAL_DATA_PTR;
101	#if 0
102	volatile unsigned short *fpga_mode =
103	(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
104	volatile unsigned char *duart0_mcr =
105	(unsigned char *)((ulong)DUART0_BA + 4);
106	volatile unsigned char *duart1_mcr =
107	(unsigned char *)((ulong)DUART1_BA + 4);
108
109	bd_t *bd = gd->bd;
110	char * tmp; /* Temporary char pointer */
111	unsigned char *dst;
112	ulong len = sizeof(fpgadata);
113	int status;
114	int index;
115	int i;
116	unsigned long cntrl0Reg;
117
118	dst = malloc(CFG_FPGA_MAX_SIZE);
119	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar )fpgadata, (int )&len) != 0) {
120	printf ("GUNZIP ERROR - must RESET board to recover\n");
121	do_reset (NULL, 0, 0, NULL);
122	}
123
124	status = fpga_boot(dst, len);
125	if (status != 0) {
126	printf("\nFPGA: Booting failed ");
127	switch (status) {
128	case ERROR_FPGA_PRG_INIT_LOW:
129	printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
130	break;
131	case ERROR_FPGA_PRG_INIT_HIGH:
132	printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
133	break;
134	case ERROR_FPGA_PRG_DONE:
135	printf("(Timeout: DONE not high after programming FPGA)\n ");
136	break;
137	}
138
139	/* display infos on fpgaimage */
140	index = 15;
141	for (i=0; i<4; i++) {
142	len = dst[index];
143	printf("FPGA: %s\n", &(dst[index+1]));
144	index += len+3;
145	}
146	putc ('\n');
147	/* delayed reboot */
148	for (i=20; i>0; i--) {
149	printf("Rebooting in %2d seconds \r",i);
150	for (index=0;index<1000;index++)
151	udelay(1000);
152	}
153	putc ('\n');
154	do_reset(NULL, 0, 0, NULL);
155	}
156
157	puts("FPGA: ");
158
159	/* display infos on fpgaimage */
160	index = 15;
161	for (i=0; i<4; i++) {
162	len = dst[index];
163	printf("%s ", &(dst[index+1]));
164	index += len+3;
165	}
166	putc ('\n');
167
168	free(dst);
169
170	/*
171	* Reset FPGA via FPGA_DATA pin
172	*/
173	SET_FPGA(FPGA_PRG \| FPGA_CLK);
174	udelay(1000); /* wait 1ms */
175	SET_FPGA(FPGA_PRG \| FPGA_CLK \| FPGA_DATA);
176	udelay(1000); /* wait 1ms */
177
178	#endif
179
180	#if 0
181	/*
182	* Enable power on PS/2 interface
183	*/
184	*fpga_mode \|= CFG_FPGA_CTRL_PS2_RESET;
185
186	/*
187	* Enable interrupts in exar duart mcr[3]
188	*/
189	*duart0_mcr = 0x08;
190	*duart1_mcr = 0x08;
191	#endif
192	#endif
193
194	return (0);
195	}
196
197
198	/*
199	* Check Board Identity:
200	*/
201
202	int checkboard (void)
203	{
204	unsigned char str[64];
205	int i = getenv_r ("serial#", str, sizeof(str));
206
207	puts ("Board: ");
208
209	if (i == -1) {
210	puts ("### No HW ID - assuming PPChameleonEVB");
211	} else {
212	puts(str);
213	}
214
215	putc ('\n');
216
217	return 0;
218	}
219
220	/* ------------------------------------------------------------------------- */
221
222	long int initdram (int board_type)
223	{
224	unsigned long val;
225
226	mtdcr(memcfga, mem_mb0cf);
227	val = mfdcr(memcfgd);
228
229	#if 0 /* test-only */
230	for (;;) {
231	NAND_DISABLE_CE(1);
232	udelay(100);
233	NAND_ENABLE_CE(1);
234	udelay(100);
235	}
236	#endif
237	#if 0
238	printf("\nmb0cf=%x\n", val); /* test-only */
239	printf("strap=%x\n", mfdcr(strap)); /* test-only */
240	#endif
241
242	return (410241024 << ((val & 0x000e0000) >> 17));
243	}
244
245	/* ------------------------------------------------------------------------- */
246
247	int testdram (void)
248	{
249	/* TODO: XXX XXX XXX */
250	printf ("test: 16 MB - ok\n");
251
252	return (0);
253	}
254
255	/* ------------------------------------------------------------------------- */
256
257	#if (CONFIG_COMMANDS & CFG_CMD_NAND)
a43278a4	258	extern ulong
12f34241 WD	259	nand_probe(ulong physadr);
	260
	261	void
	262	nand_init(void)
	263	{
a43278a4 WD	264	ulong totlen;
a43278a4 WD	265
4d816774	266	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
a43278a4	267	totlen = nand_probe (CFG_NAND0_BASE);
4d816774 WD	268
4d816774 WD	269	debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
a43278a4 WD	270	totlen += nand_probe (CFG_NAND1_BASE);
	271
	272	printf ("%4lu MB\n", totlen >>20);
12f34241 WD	273	}
12f34241 WD	274	#endif