[people/ms/u-boot.git] / board / davedenx / qong / qong.c

/*
 *
 * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <nand.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <asm/gpio.h>
#include "qong_fpga.h"
#include <watchdog.h>
#include <errno.h>

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				PHYS_SDRAM_1_SIZE);
	return 0;
}

static void qong_fpga_reset(void)
{
	gpio_set_value(QONG_FPGA_RST_PIN, 0);
	udelay(30);
	gpio_set_value(QONG_FPGA_RST_PIN, 1);

	udelay(300);
}

int board_early_init_f(void)
{
#ifdef CONFIG_QONG_FPGA
	/* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
	static const struct mxc_weimcs cs1 = {
		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  0, 10, 0,  0,  1),
		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
		CSCR_L(2,  0,   0,   4,  0,  0,  5,  0,  0,  0,   0,   1),
		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
		CSCR_A(0,   4,  0,  2,  0,  0,  3,  0,  0,  0,  0,  0,   0,  0)
	};

	mxc_setup_weimcs(1, &cs1);

	/* setup pins for FPGA */
	mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
	mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
	mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
	mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
	mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));

	/* FPGA reset  Pin */
	/* rstn = 0 */
	gpio_direction_output(QONG_FPGA_RST_PIN, 0);

	/* set interrupt pin as input */
	gpio_direction_input(QONG_FPGA_IRQ_PIN);

	/* FPGA JTAG Interface */
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
	gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
	gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
	gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
	gpio_direction_input(QONG_FPGA_TDO_PIN);
#endif

	/* setup pins for UART1 */
	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);

	/* setup pins for SPI (pmic) */
	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);

	/* Setup pins for USB2 Host */
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));

#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
			PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)

	mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
	mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
	mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
	mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
	mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
	mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
	mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);	/* USBH2_DATA2 */
	mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);	/* USBH2_DATA3 */
	mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);	/* USBH2_DATA4 */
	mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);	/* USBH2_DATA5 */
	mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);	/* USBH2_DATA6 */
	mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);	/* USBH2_DATA7 */

	mx31_set_gpr(MUX_PGP_UH2, 1);

	return 0;

}

int board_init(void)
{
	/* Chip selects */
	/* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
	/* Assumptions: HCLK = 133 MHz, tACC = 130ns */
	static const struct mxc_weimcs cs0 = {
		/*     sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 21, 0,  0,  6),
		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
		CSCR_L(0,  1,   3,   3,  1,  1,  5,  1,  0,  0,   0,  1),
		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
		CSCR_A(0,   1,  2,  2,  0,  0,  2,  0,  0,  0,  0,  0,   0,  0)
	};

	mxc_setup_weimcs(0, &cs0);

	/* board id for linux */
	gd->bd->bi_arch_number = MACH_TYPE_QONG;
	gd->bd->bi_boot_params = (0x80000100);	/* adress of boot parameters */

	qong_fpga_init();

	return 0;
}

int board_late_init(void)
{
	u32 val;
	struct pmic *p;
	int ret;

	ret = pmic_init(I2C_PMIC);
	if (ret)
		return ret;

	p = pmic_get("FSL_PMIC");
	if (!p)
		return -ENODEV;
	/* Enable RTC battery */
	pmic_reg_read(p, REG_POWER_CTL0, &val);
	pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
	pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);

#ifdef CONFIG_HW_WATCHDOG
	hw_watchdog_init();
#endif

	return 0;
}

int checkboard(void)
{
	printf("Board: DAVE/DENX Qong\n");
	return 0;
}

int misc_init_r(void)
{
#ifdef CONFIG_QONG_FPGA
	u32 tmp;

	tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
	printf("FPGA:  ");
	printf("version register = %u.%u.%u\n",
		(tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
#endif
	return 0;
}

int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
	return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
#else
	return 0;
#endif
}

#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
static void board_nand_setup(void)
{
	/* CS3: NAND 8-bit */
	static const struct mxc_weimcs cs3 = {
		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  1, 15, 0,  0,  0),
		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
		CSCR_L(2,  0,   0,   1,  3,  1,  3,  3,  0,  0,   0,   1),
		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
		CSCR_A(0,   0,  0,  2,  0,  0,  2,  0,  0,  0,  0,  0,  0,   0)
	};

	mxc_setup_weimcs(3, &cs3);

	mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);

	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));

	/* Make sure to reset the fpga else you cannot access NAND */
	qong_fpga_reset();

	/* Enable NAND flash */
	gpio_set_value(15, 1);
	gpio_set_value(14, 1);
	gpio_direction_output(15, 0);
	gpio_direction_input(16);
	gpio_direction_input(14);

}

int qong_nand_rdy(void *chip)
{
	udelay(1);
	return gpio_get_value(16);
}

void qong_nand_select_chip(struct mtd_info *mtd, int chip)
{
	if (chip >= 0)
		gpio_set_value(15, 0);
	else
		gpio_set_value(15, 1);

}

void qong_nand_plat_init(void *chip)
{
	struct nand_chip *nand = (struct nand_chip *)chip;
	nand->chip_delay = 20;
	nand->select_chip = qong_nand_select_chip;
	nand->options &= ~NAND_BUSWIDTH_16;
	board_nand_setup();
}

#endif
Commit	Line	Data
0d19f6c8 IY	1	/*
	2	*
	3	* (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
0d19f6c8 IY	6	*/
0d19f6c8 IY	7
0d19f6c8 IY	8	#include <common.h>
0d19f6c8 IY	9	#include <netdev.h>
86271115 SB	10	#include <asm/arch/clock.h>
86271115 SB	11	#include <asm/arch/imx-regs.h>
47c5455a	12	#include <asm/arch/sys_proto.h>
d7dc464b	13	#include <asm/io.h>
45997e0a	14	#include <nand.h>
c7336815	15	#include <power/pmic.h>
e98ecd71	16	#include <fsl_pmic.h>
9400f592	17	#include <asm/gpio.h>
0d19f6c8	18	#include "qong_fpga.h"
8640c984	19	#include <watchdog.h>
c7336815	20	#include <errno.h>
0d19f6c8 IY	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
77f11a99	24	int dram_init(void)
0d19f6c8	25	{
e48b7c0a	26	/* dram_init must store complete ramsize in gd->ram_size */
a55d23cc	27	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
e48b7c0a	28	PHYS_SDRAM_1_SIZE);
0d19f6c8 IY	29	return 0;
	30	}
	31
45997e0a SB	32	static void qong_fpga_reset(void)
45997e0a SB	33	{
9400f592	34	gpio_set_value(QONG_FPGA_RST_PIN, 0);
45997e0a	35	udelay(30);
9400f592	36	gpio_set_value(QONG_FPGA_RST_PIN, 1);
45997e0a SB	37
	38	udelay(300);
	39	}
	40
77f11a99	41	int board_early_init_f(void)
e48b7c0a HS	42	{
e48b7c0a HS	43	#ifdef CONFIG_QONG_FPGA
47c5455a HR	44	/* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
	45	static const struct mxc_weimcs cs1 = {
	46	/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
	47	CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1),
	48	/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
	49	CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1),
	50	/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
	51	CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0)
	52	};
	53
	54	mxc_setup_weimcs(1, &cs1);
e48b7c0a HS	55
	56	/* setup pins for FPGA */
	57	mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
	58	mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
	59	mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC \| MUX_CTL_IN_GPIO));
	60	mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
	61	mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
	62
	63	/* FPGA reset Pin */
	64	/* rstn = 0 */
9400f592	65	gpio_direction_output(QONG_FPGA_RST_PIN, 0);
e48b7c0a HS	66
e48b7c0a HS	67	/* set interrupt pin as input */
9400f592	68	gpio_direction_input(QONG_FPGA_IRQ_PIN);
e48b7c0a	69
b9eb3fdf SB	70	/* FPGA JTAG Interface */
	71	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
	72	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
	73	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
	74	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
9400f592 SB	75	gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
	76	gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
	77	gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
	78	gpio_direction_input(QONG_FPGA_TDO_PIN);
e48b7c0a HS	79	#endif
	80
	81	/* setup pins for UART1 */
	82	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
	83	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
	84	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
	85	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
	86
	87	/* setup pins for SPI (pmic) */
	88	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
	89	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
	90	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
	91	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
	92	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
	93
d7dc464b SB	94	/* Setup pins for USB2 Host */
	95	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
	96	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
	97	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
	98	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
	99	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
	100	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
d7dc464b SB	101
	102	#define H2_PAD_CFG (PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS_CMOS \| \
	103	PAD_CTL_ODE_CMOS \| PAD_CTL_100K_PU)
	104
	105	mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
	106	mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
	107	mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
	108	mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
	109	mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
	110	mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
	111	mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
	112	mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
	113	mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
	114	mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
	115	mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
	116	mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
	117
842d853a	118	mx31_set_gpr(MUX_PGP_UH2, 1);
d7dc464b	119
e48b7c0a HS	120	return 0;
	121
	122	}
	123
77f11a99	124	int board_init(void)
0d19f6c8 IY	125	{
	126	/* Chip selects */
	127	/* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
	128	/* Assumptions: HCLK = 133 MHz, tACC = 130ns */
47c5455a HR	129	static const struct mxc_weimcs cs0 = {
	130	/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
	131	CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6),
	132	/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
	133	CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1),
	134	/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
	135	CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
	136	};
	137
	138	mxc_setup_weimcs(0, &cs0);
0d19f6c8	139
0d19f6c8 IY	140	/* board id for linux */
	141	gd->bd->bi_arch_number = MACH_TYPE_QONG;
	142	gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
	143
b9eb3fdf SB	144	qong_fpga_init();
b9eb3fdf SB	145
0d19f6c8 IY	146	return 0;
	147	}
	148
e98ecd71 SB	149	int board_late_init(void)
	150	{
	151	u32 val;
f33bd087	152	struct pmic *p;
c7336815	153	int ret;
f33bd087	154
c7336815 ŁM	155	ret = pmic_init(I2C_PMIC);
	156	if (ret)
	157	return ret;
e98ecd71	158
c7336815 ŁM	159	p = pmic_get("FSL_PMIC");
	160	if (!p)
	161	return -ENODEV;
e98ecd71	162	/* Enable RTC battery */
f33bd087 SB	163	pmic_reg_read(p, REG_POWER_CTL0, &val);
	164	pmic_reg_write(p, REG_POWER_CTL0, val \| COINCHEN);
	165	pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
e98ecd71	166
8640c984	167	#ifdef CONFIG_HW_WATCHDOG
abbab703	168	hw_watchdog_init();
8640c984 SB	169	#endif
8640c984 SB	170
e98ecd71 SB	171	return 0;
	172	}
	173
77f11a99	174	int checkboard(void)
0d19f6c8	175	{
eeb50ce1	176	printf("Board: DAVE/DENX Qong\n");
0d19f6c8 IY	177	return 0;
	178	}
	179
77f11a99	180	int misc_init_r(void)
0d19f6c8 IY	181	{
	182	#ifdef CONFIG_QONG_FPGA
	183	u32 tmp;
	184
0d19f6c8 IY	185	tmp = (volatile u32)QONG_FPGA_CTRL_VERSION;
	186	printf("FPGA: ");
	187	printf("version register = %u.%u.%u\n",
	188	(tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
	189	#endif
0d19f6c8 IY	190	return 0;
	191	}
	192
	193	int board_eth_init(bd_t *bis)
	194	{
	195	#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
	196	return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
	197	#else
	198	return 0;
	199	#endif
	200	}
45997e0a SB	201
	202	#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
	203	static void board_nand_setup(void)
	204	{
45997e0a	205	/* CS3: NAND 8-bit */
47c5455a HR	206	static const struct mxc_weimcs cs3 = {
	207	/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
	208	CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0),
	209	/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
	210	CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1),
	211	/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
	212	CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
	213	};
	214
	215	mxc_setup_weimcs(3, &cs3);
	216
f631172e	217	mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
45997e0a SB	218
	219	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
	220	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
	221	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
	222
	223	/* Make sure to reset the fpga else you cannot access NAND */
	224	qong_fpga_reset();
	225
	226	/* Enable NAND flash */
9400f592 SB	227	gpio_set_value(15, 1);
	228	gpio_set_value(14, 1);
	229	gpio_direction_output(15, 0);
	230	gpio_direction_input(16);
	231	gpio_direction_input(14);
45997e0a SB	232
	233	}
	234
	235	int qong_nand_rdy(void *chip)
	236	{
	237	udelay(1);
9400f592	238	return gpio_get_value(16);
45997e0a SB	239	}
	240
	241	void qong_nand_select_chip(struct mtd_info *mtd, int chip)
	242	{
	243	if (chip >= 0)
9400f592	244	gpio_set_value(15, 0);
45997e0a	245	else
9400f592	246	gpio_set_value(15, 1);
45997e0a SB	247
	248	}
	249
	250	void qong_nand_plat_init(void *chip)
	251	{
	252	struct nand_chip nand = (struct nand_chip )chip;
	253	nand->chip_delay = 20;
	254	nand->select_chip = qong_nand_select_chip;
	255	nand->options &= ~NAND_BUSWIDTH_16;
	256	board_nand_setup();
	257	}
	258
	259	#endif