[people/ms/u-boot.git] / board / dbau1x00 / lowlevel_init.S

/* Memory sub-system initialization code */

#include <config.h>
#include <asm/regdef.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>

#define AU1500_SYS_ADDR		0xB1900000
#define sys_endian		0x0038
#define CP0_Config0		$16
#define CPU_SCALE		((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
#define MEM_1MS			((CONFIG_SYS_MHZ) * 1000)

	.text
	.set noreorder
	.set mips32

	.globl	lowlevel_init
lowlevel_init:
	/*
	 * Step 1) Establish CPU endian mode.
	 * Db1500-specific:
	 * Switch S1.1 Off(bit7 reads 1) is Little Endian
	 * Switch S1.1 On (bit7 reads 0) is Big Endian
	 */
#ifdef CONFIG_DBAU1550
	li	t0, MEM_STCFG2
	li	t1, 0x00000040
	sw	t1, 0(t0)

	li	t0, MEM_STTIME2
	li	t1, 0x22080a20
	sw	t1, 0(t0)

	li	t0, MEM_STADDR2
	li	t1, 0x10c03f00
	sw	t1, 0(t0)
#else
	li	t0, MEM_STCFG1
	li	t1, 0x00000080
	sw	t1, 0(t0)

	li	t0, MEM_STTIME1
	li	t1, 0x22080a20
	sw	t1, 0(t0)

	li	t0, MEM_STADDR1
	li	t1, 0x10c03f00
	sw	t1, 0(t0)
#endif

	li	t0, DB1XX0_BCSR_ADDR
	lw	t1,8(t0)
	andi	t1,t1,0x80
	beq	zero,t1,big_endian
	nop
little_endian:

	/* Change Au1 core to little endian */
	li	t0, AU1500_SYS_ADDR
	li	t1, 1
	sw	t1, sys_endian(t0)
	mfc0	t2, CP0_CONFIG
	mtc0	t2, CP0_CONFIG
	nop
	nop

	/* Big Endian is default so nothing to do but fall through */

big_endian:

	/*
	 * Step 2) Establish Status Register
	 * (set BEV, clear ERL, clear EXL, clear IE)
	 */
	li	t1, 0x00400000
	mtc0	t1, CP0_STATUS

	/*
	 * Step 3) Establish CP0 Config0
	 * (set OD, set K0=3)
	 */
	li	t1, 0x00080003
	mtc0	t1, CP0_CONFIG

	/*
	 * Step 4) Disable Watchpoint facilities
	 */
	li t1, 0x00000000
	mtc0	t1, CP0_WATCHLO
	mtc0	t1, CP0_IWATCHLO
	/*
	 * Step 5) Disable the performance counters
	 */
	mtc0	zero, CP0_PERFORMANCE
	nop

	/*
	 * Step 6) Establish EJTAG Debug register
	 */
	mtc0	zero, CP0_DEBUG
	nop

	/*
	 * Step 7) Establish Cause
	 * (set IV bit)
	 */
	li	t1, 0x00800000
	mtc0	t1, CP0_CAUSE

	/* Establish Wired (and Random) */
	mtc0	zero, CP0_WIRED
	nop

#ifdef CONFIG_DBAU1550
	/* No workaround if running from ram */
	lui	t0, 0xffc0
	lui	t3, 0xbfc0
	and	t1, ra, t0
	bne	t1, t3, noCacheJump
	nop

	/*** From AMD YAMON ***/
	/*
	 * Step 8) Initialize the caches
	 */
	li		t0, (16*1024)
	li		t1, 32
	li		t2, 0x80000000
	addu	t3, t0, t2
cacheloop:
	cache	0, 0(t2)
	cache	1, 0(t2)
	addu	t2, t1
	bne		t2, t3, cacheloop
	nop

	/* Save return address */
	move		t3, ra

	/* Run from cacheable space now */
	bal		cachehere
	nop
cachehere:
	li		t1, ~0x20000000 /* convert to KSEG0 */
	and		t0, ra, t1
	addi	t0, 5*4			/* 5 insns beyond cachehere */
	jr		t0
	nop

	/* Restore return address */
	move		ra, t3

	/*
	 * Step 9) Initialize the TLB
	 */
	li		t0, 0			# index value
	li		t1, 0x00000000		# entryhi value
	li		t2, 32			# 32 entries

tlbloop:
	/* Probe TLB for matching EntryHi */
	mtc0	t1, CP0_ENTRYHI
	tlbp
	nop

	/* Examine Index[P], 1=no matching entry */
	mfc0	t3, CP0_INDEX
	li	t4, 0x80000000
	and	t3, t4, t3
	addiu	t1, t1, 1		# increment t1 (asid)
	beq	zero, t3, tlbloop
	nop

	/* Initialize the TLB entry */
	mtc0	t0, CP0_INDEX
	mtc0	zero, CP0_ENTRYLO0
	mtc0	zero, CP0_ENTRYLO1
	mtc0	zero, CP0_PAGEMASK
	tlbwi

	/* Do it again */
	addiu	t0, t0, 1
	bne	t0, t2, tlbloop
	nop

#endif /* CONFIG_DBAU1550 */

	/* First setup pll:s to make serial work ok */
	/* We have a 12 MHz crystal */
	li	t0, SYS_CPUPLL
	li	t1, CPU_SCALE  /* CPU clock */
	sw	t1, 0(t0)
	sync
	nop
	nop

	/* wait 1mS for clocks to settle */
	li	t1, MEM_1MS
1:	add	t1, -1
	bne	t1, zero, 1b
	nop
	/* Setup AUX PLL */
	li	t0, SYS_AUXPLL
	li	t1, 0x20 /* 96 MHz */
	sw	t1, 0(t0) /* aux pll */
	sync

#ifdef CONFIG_DBAU1550
	/*  Static memory controller */
	/* RCE0 - can not change while fetching, do so from icache */
	move		t2, ra /* Store return address */
	bal		getAddr
	nop

getAddr:
	move		t1, ra
	move		ra, t2 /* Move return addess back */

	cache	0x14,0(t1)
	cache	0x14,32(t1)
	/*** /From YAMON ***/

noCacheJump:
#endif /* CONFIG_DBAU1550 */

#ifdef CONFIG_DBAU1550
	li	t0, MEM_STTIME0
	li	t1, 0x040181D7
	sw	t1, 0(t0)

	/* RCE0 AMD MirrorBit Flash (?) */
	li	t0, MEM_STCFG0
	li	t1, 0x00000003
	sw	t1, 0(t0)

	li	t0, MEM_STADDR0
	li	t1, 0x11803E00
	sw	t1, 0(t0)
#else /* CONFIG_DBAU1550 */
	li	t0, MEM_STTIME0
	li	t1, 0x040181D7
	sw	t1, 0(t0)

	/* RCE0 AMD 29LV640M MirrorBit Flash */
	li	t0, MEM_STCFG0
	li	t1, 0x00000013
	sw	t1, 0(t0)

	li	t0, MEM_STADDR0
	li	t1, 0x11E03F80
	sw	t1, 0(t0)
#endif /* CONFIG_DBAU1550 */

	/* RCE1 CPLD Board Logic */
	li	t0, MEM_STCFG1
	li	t1, 0x00000080
	sw	t1, 0(t0)

	li	t0, MEM_STTIME1
	li	t1, 0x22080a20
	sw	t1, 0(t0)

	li	t0, MEM_STADDR1
	li	t1, 0x10c03f00
	sw	t1, 0(t0)

#ifdef CONFIG_DBAU1550
	/* RCE2 CPLD Board Logic */
	li	t0, MEM_STCFG2
	li	t1, 0x00000040
	sw	t1, 0(t0)

	li	t0, MEM_STTIME2
	li	t1, 0x22080a20
	sw	t1, 0(t0)

	li	t0, MEM_STADDR2
	li	t1, 0x10c03f00
	sw	t1, 0(t0)
#else
	li	t0, MEM_STCFG2
	li	t1, 0x00000000
	sw	t1, 0(t0)

	li	t0, MEM_STTIME2
	li	t1, 0x00000000
	sw	t1, 0(t0)

	li	t0, MEM_STADDR2
	li	t1, 0x00000000
	sw	t1, 0(t0)
#endif

	/* RCE3 PCMCIA 250ns */
	li	t0, MEM_STCFG3
	li	t1, 0x00000002
	sw	t1, 0(t0)

	li	t0, MEM_STTIME3
	li	t1, 0x280E3E07
	sw	t1, 0(t0)

	li	t0, MEM_STADDR3
	li	t1, 0x10000000
	sw	t1, 0(t0)

	sync

	/* Set peripherals to a known state */
	li	t0, IC0_CFG0CLR
	li	t1, 0xFFFFFFFF
	sw	t1, 0(t0)

	li	t0, IC0_CFG0CLR
	sw	t1, 0(t0)

	li	t0, IC0_CFG1CLR
	sw	t1, 0(t0)

	li	t0, IC0_CFG2CLR
	sw	t1, 0(t0)

	li	t0, IC0_SRCSET
	sw	t1, 0(t0)

	li	t0, IC0_ASSIGNSET
	sw	t1, 0(t0)

	li	t0, IC0_WAKECLR
	sw	t1, 0(t0)

	li	t0, IC0_RISINGCLR
	sw	t1, 0(t0)

	li	t0, IC0_FALLINGCLR
	sw	t1, 0(t0)

	li	t0, IC0_TESTBIT
	li	t1, 0x00000000
	sw	t1, 0(t0)
	sync

	li	t0, IC1_CFG0CLR
	li	t1, 0xFFFFFFFF
	sw	t1, 0(t0)

	li	t0, IC1_CFG0CLR
	sw	t1, 0(t0)

	li	t0, IC1_CFG1CLR
	sw	t1, 0(t0)

	li	t0, IC1_CFG2CLR
	sw	t1, 0(t0)

	li	t0, IC1_SRCSET
	sw	t1, 0(t0)

	li	t0, IC1_ASSIGNSET
	sw	t1, 0(t0)

	li	t0, IC1_WAKECLR
	sw	t1, 0(t0)

	li	t0, IC1_RISINGCLR
	sw	t1, 0(t0)

	li	t0, IC1_FALLINGCLR
	sw	t1, 0(t0)

	li	t0, IC1_TESTBIT
	li	t1, 0x00000000
	sw	t1, 0(t0)
	sync

	li	t0, SYS_FREQCTRL0
	li	t1, 0x00000000
	sw	t1, 0(t0)

	li	t0, SYS_FREQCTRL1
	li	t1, 0x00000000
	sw	t1, 0(t0)

	li	t0, SYS_CLKSRC
	li	t1, 0x00000000
	sw	t1, 0(t0)

	li	t0, SYS_PININPUTEN
	li	t1, 0x00000000
	sw	t1, 0(t0)
	sync

	li	t0, 0xB1100100
	li	t1, 0x00000000
	sw	t1, 0(t0)

	li	t0, 0xB1400100
	li	t1, 0x00000000
	sw	t1, 0(t0)


	li	t0, SYS_WAKEMSK
	li	t1, 0x00000000
	sw	t1, 0(t0)

	li	t0, SYS_WAKESRC
	li	t1, 0x00000000
	sw	t1, 0(t0)

	/* wait 1mS before setup */
	li	t1, MEM_1MS
1:	add	t1, -1
	bne	t1, zero, 1b
	nop

#ifdef CONFIG_DBAU1550
/* SDCS 0,1,2 DDR SDRAM */
	li	t0, MEM_SDMODE0
	li	t1, 0x04276221
	sw	t1, 0(t0)

	li	t0, MEM_SDMODE1
	li	t1, 0x04276221
	sw	t1, 0(t0)

	li	t0, MEM_SDMODE2
	li	t1, 0x04276221
	sw	t1, 0(t0)

	li	t0, MEM_SDADDR0
	li	t1, 0xe21003f0
	sw	t1, 0(t0)

	li	t0, MEM_SDADDR1
	li	t1, 0xe21043f0
	sw	t1, 0(t0)

	li	t0, MEM_SDADDR2
	li	t1, 0xe21083f0
	sw	t1, 0(t0)

	sync

	li	t0, MEM_SDCONFIGA
	li	t1, 0x9030060a /* Program refresh - disabled */
	sw	t1, 0(t0)
	sync

	li	t0, MEM_SDCONFIGB
	li	t1, 0x00028000
	sw	t1, 0(t0)
	sync

	li	t0, MEM_SDPRECMD /* Precharge all */
	li	t1, 0
	sw	t1, 0(t0)
	sync

	li	t0, MEM_SDWRMD0
	li	t1, 0x40000000
	sw	t1, 0(t0)
	sync

	li	t0, MEM_SDWRMD1
	li	t1, 0x40000000
	sw	t1, 0(t0)
	sync

	li	t0, MEM_SDWRMD2
	li	t1, 0x40000000
	sw	t1, 0(t0)
	sync

	li	t0, MEM_SDWRMD0
	li	t1, 0x00000063
	sw	t1, 0(t0)
	sync

	li	t0, MEM_SDWRMD1
	li	t1, 0x00000063
	sw	t1, 0(t0)
	sync

	li	t0, MEM_SDWRMD2
	li	t1, 0x00000063
	sw	t1, 0(t0)
	sync

	li	t0, MEM_SDPRECMD /* Precharge all */
	sw	zero, 0(t0)
	sync

	/* Issue 2 autoref */
	li	t0, MEM_SDAUTOREF
	sw	zero, 0(t0)
	sync

	li	t0, MEM_SDAUTOREF
	sw	zero, 0(t0)
	sync

	/* Enable refresh */
	li	t0, MEM_SDCONFIGA
	li	t1, 0x9830060a /* Program refresh - enabled */
	sw	t1, 0(t0)
	sync

#else /* CONFIG_DBAU1550 */
/* SDCS 0,1 SDRAM */
	li	t0, MEM_SDMODE0
	li	t1, 0x005522AA
	sw	t1, 0(t0)

	li	t0, MEM_SDMODE1
	li	t1, 0x005522AA
	sw	t1, 0(t0)

	li	t0, MEM_SDMODE2
	li	t1, 0x00000000
	sw	t1, 0(t0)

	li	t0, MEM_SDADDR0
	li	t1, 0x001003F8
	sw	t1, 0(t0)


	li	t0, MEM_SDADDR1
	li	t1, 0x001023F8
	sw	t1, 0(t0)

	li	t0, MEM_SDADDR2
	li	t1, 0x00000000
	sw	t1, 0(t0)

	sync

	li	t0, MEM_SDREFCFG
	li	t1, 0x64000C24 /* Disable */
	sw	t1, 0(t0)
	sync

	li	t0, MEM_SDPRECMD
	sw	zero, 0(t0)
	sync

	li	t0, MEM_SDAUTOREF
	sw	zero, 0(t0)
	sync
	sw	zero, 0(t0)
	sync

	li	t0, MEM_SDREFCFG
	li	t1, 0x66000C24 /* Enable */
	sw	t1, 0(t0)
	sync

	li	t0, MEM_SDWRMD0
	li	t1, 0x00000033
	sw	t1, 0(t0)
	sync

	li	t0, MEM_SDWRMD1
	li	t1, 0x00000033
	sw	t1, 0(t0)
	sync

#endif /* CONFIG_DBAU1550 */
	/* wait 1mS after setup */
	li	t1, MEM_1MS
1:	add	t1, -1
	bne	t1, zero, 1b
	nop

	li	t0, SYS_PINFUNC
	li	t1, 0x00008080
	sw	t1, 0(t0)

	li	t0, SYS_TRIOUTCLR
	li	t1, 0x00001FFF
	sw	t1, 0(t0)

	li	t0, SYS_OUTPUTCLR
	li	t1, 0x00008000
	sw	t1, 0(t0)
	sync

	jr	ra
	nop
Commit	Line	Data
5da627a4 WD	1	/* Memory sub-system initialization code */
	2
	3	#include <config.h>
5da627a4 WD	4	#include <asm/regdef.h>
5da627a4 WD	5	#include <asm/au1x00.h>
63f34912 WD	6	#include <asm/mipsregs.h>
	7
	8	#define AU1500_SYS_ADDR 0xB1900000
	9	#define sys_endian 0x0038
	10	#define CP0_Config0 $16
6d0f6bcf JCPV	11	#define CPU_SCALE ((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
6d0f6bcf JCPV	12	#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000)
63f34912 WD	13
	14	.text
	15	.set noreorder
	16	.set mips32
5da627a4	17
400558b5 WD	18	.globl lowlevel_init
400558b5 WD	19	lowlevel_init:
63f34912 WD	20	/*
	21	* Step 1) Establish CPU endian mode.
	22	* Db1500-specific:
	23	* Switch S1.1 Off(bit7 reads 1) is Little Endian
	24	* Switch S1.1 On (bit7 reads 0) is Big Endian
	25	*/
ff36fd85 WD	26	#ifdef CONFIG_DBAU1550
	27	li t0, MEM_STCFG2
	28	li t1, 0x00000040
	29	sw t1, 0(t0)
	30
	31	li t0, MEM_STTIME2
	32	li t1, 0x22080a20
	33	sw t1, 0(t0)
	34
	35	li t0, MEM_STADDR2
	36	li t1, 0x10c03f00
	37	sw t1, 0(t0)
	38	#else
63f34912 WD	39	li t0, MEM_STCFG1
	40	li t1, 0x00000080
	41	sw t1, 0(t0)
	42
	43	li t0, MEM_STTIME1
	44	li t1, 0x22080a20
	45	sw t1, 0(t0)
	46
	47	li t0, MEM_STADDR1
	48	li t1, 0x10c03f00
	49	sw t1, 0(t0)
ff36fd85	50	#endif
63f34912	51
ff36fd85 WD	52	li t0, DB1XX0_BCSR_ADDR
ff36fd85 WD	53	lw t1,8(t0)
63f34912 WD	54	andi t1,t1,0x80
	55	beq zero,t1,big_endian
	56	nop
	57	little_endian:
	58
	59	/* Change Au1 core to little endian */
	60	li t0, AU1500_SYS_ADDR
	61	li t1, 1
	62	sw t1, sys_endian(t0)
	63	mfc0 t2, CP0_CONFIG
	64	mtc0 t2, CP0_CONFIG
	65	nop
	66	nop
	67
	68	/* Big Endian is default so nothing to do but fall through */
	69
	70	big_endian:
	71
	72	/*
	73	* Step 2) Establish Status Register
	74	* (set BEV, clear ERL, clear EXL, clear IE)
	75	*/
	76	li t1, 0x00400000
	77	mtc0 t1, CP0_STATUS
	78
	79	/*
	80	* Step 3) Establish CP0 Config0
	81	* (set OD, set K0=3)
	82	*/
	83	li t1, 0x00080003
	84	mtc0 t1, CP0_CONFIG
	85
	86	/*
	87	* Step 4) Disable Watchpoint facilities
	88	*/
	89	li t1, 0x00000000
	90	mtc0 t1, CP0_WATCHLO
	91	mtc0 t1, CP0_IWATCHLO
	92	/*
	93	* Step 5) Disable the performance counters
	94	*/
	95	mtc0 zero, CP0_PERFORMANCE
	96	nop
	97
	98	/*
	99	* Step 6) Establish EJTAG Debug register
	100	*/
	101	mtc0 zero, CP0_DEBUG
	102	nop
	103
	104	/*
	105	* Step 7) Establish Cause
	106	* (set IV bit)
	107	*/
	108	li t1, 0x00800000
	109	mtc0 t1, CP0_CAUSE
	110
	111	/* Establish Wired (and Random) */
	112	mtc0 zero, CP0_WIRED
	113	nop
	114
ff36fd85 WD	115	#ifdef CONFIG_DBAU1550
	116	/* No workaround if running from ram */
	117	lui t0, 0xffc0
	118	lui t3, 0xbfc0
	119	and t1, ra, t0
	120	bne t1, t3, noCacheJump
	121	nop
	122
	123	/* From AMD YAMON */
	124	/*
	125	* Step 8) Initialize the caches
	126	*/
	127	li t0, (16*1024)
	128	li t1, 32
	129	li t2, 0x80000000
	130	addu t3, t0, t2
	131	cacheloop:
	132	cache 0, 0(t2)
	133	cache 1, 0(t2)
	134	addu t2, t1
	135	bne t2, t3, cacheloop
	136	nop
	137
	138	/* Save return address */
	139	move t3, ra
	140
	141	/* Run from cacheable space now */
	142	bal cachehere
	143	nop
	144	cachehere:
	145	li t1, ~0x20000000 /* convert to KSEG0 */
	146	and t0, ra, t1
	147	addi t0, 54 / 5 insns beyond cachehere */
	148	jr t0
	149	nop
	150
	151	/* Restore return address */
	152	move ra, t3
	153
	154	/*
	155	* Step 9) Initialize the TLB
	156	*/
	157	li t0, 0 # index value
	158	li t1, 0x00000000 # entryhi value
	159	li t2, 32 # 32 entries
	160
	161	tlbloop:
	162	/* Probe TLB for matching EntryHi */
	163	mtc0 t1, CP0_ENTRYHI
	164	tlbp
	165	nop
	166
	167	/* Examine Index[P], 1=no matching entry */
	168	mfc0 t3, CP0_INDEX
	169	li t4, 0x80000000
	170	and t3, t4, t3
	171	addiu t1, t1, 1 # increment t1 (asid)
	172	beq zero, t3, tlbloop
	173	nop
	174
	175	/* Initialize the TLB entry */
	176	mtc0 t0, CP0_INDEX
	177	mtc0 zero, CP0_ENTRYLO0
	178	mtc0 zero, CP0_ENTRYLO1
179	mtc0 zero, CP0_PAGEMASK
180	tlbwi
181
182	/* Do it again */
183	addiu t0, t0, 1
184	bne t0, t2, tlbloop
185	nop
186
ad88297e HS	187	#endif /* CONFIG_DBAU1550 */
ad88297e HS	188
5da627a4 WD	189	/* First setup pll:s to make serial work ok */
5da627a4 WD	190	/* We have a 12 MHz crystal */
63f34912	191	li t0, SYS_CPUPLL
ff36fd85	192	li t1, CPU_SCALE /* CPU clock */
63f34912	193	sw t1, 0(t0)
42d1f039 WD	194	sync
42d1f039 WD	195	nop
63f34912	196	nop
5da627a4	197
63f34912 WD	198	/* wait 1mS for clocks to settle */
	199	li t1, MEM_1MS
	200	1: add t1, -1
	201	bne t1, zero, 1b
	202	nop
42d1f039	203	/* Setup AUX PLL */
63f34912 WD	204	li t0, SYS_AUXPLL
	205	li t1, 0x20 /* 96 MHz */
	206	sw t1, 0(t0) /* aux pll */
42d1f039	207	sync
5da627a4	208
ad88297e	209	#ifdef CONFIG_DBAU1550
63f34912	210	/* Static memory controller */
ff36fd85 WD	211	/* RCE0 - can not change while fetching, do so from icache */
	212	move t2, ra /* Store return address */
	213	bal getAddr
	214	nop
5da627a4	215
ff36fd85 WD	216	getAddr:
	217	move t1, ra
	218	move ra, t2 /* Move return addess back */
	219
	220	cache 0x14,0(t1)
	221	cache 0x14,32(t1)
	222	/* /From YAMON */
	223
	224	noCacheJump:
	225	#endif /* CONFIG_DBAU1550 */
	226
	227	#ifdef CONFIG_DBAU1550
	228	li t0, MEM_STTIME0
	229	li t1, 0x040181D7
	230	sw t1, 0(t0)
	231
	232	/* RCE0 AMD MirrorBit Flash (?) */
63f34912	233	li t0, MEM_STCFG0
ff36fd85	234	li t1, 0x00000003
63f34912	235	sw t1, 0(t0)
5da627a4	236
ff36fd85 WD	237	li t0, MEM_STADDR0
	238	li t1, 0x11803E00
	239	sw t1, 0(t0)
	240	#else /* CONFIG_DBAU1550 */
63f34912	241	li t0, MEM_STTIME0
ad88297e	242	li t1, 0x040181D7
ff36fd85 WD	243	sw t1, 0(t0)
	244
	245	/* RCE0 AMD 29LV640M MirrorBit Flash */
	246	li t0, MEM_STCFG0
	247	li t1, 0x00000013
63f34912	248	sw t1, 0(t0)
5da627a4	249
63f34912 WD	250	li t0, MEM_STADDR0
	251	li t1, 0x11E03F80
	252	sw t1, 0(t0)
ff36fd85	253	#endif /* CONFIG_DBAU1550 */
5da627a4	254
63f34912 WD	255	/* RCE1 CPLD Board Logic */
	256	li t0, MEM_STCFG1
	257	li t1, 0x00000080
	258	sw t1, 0(t0)
5da627a4	259
63f34912 WD	260	li t0, MEM_STTIME1
	261	li t1, 0x22080a20
	262	sw t1, 0(t0)
5da627a4	263
63f34912 WD	264	li t0, MEM_STADDR1
	265	li t1, 0x10c03f00
	266	sw t1, 0(t0)
	267
ff36fd85	268	#ifdef CONFIG_DBAU1550
63f34912	269	/* RCE2 CPLD Board Logic */
ff36fd85 WD	270	li t0, MEM_STCFG2
	271	li t1, 0x00000040
	272	sw t1, 0(t0)
	273
	274	li t0, MEM_STTIME2
	275	li t1, 0x22080a20
	276	sw t1, 0(t0)
	277
	278	li t0, MEM_STADDR2
	279	li t1, 0x10c03f00
	280	sw t1, 0(t0)
	281	#else
63f34912 WD	282	li t0, MEM_STCFG2
	283	li t1, 0x00000000
	284	sw t1, 0(t0)
	285
	286	li t0, MEM_STTIME2
	287	li t1, 0x00000000
	288	sw t1, 0(t0)
	289
	290	li t0, MEM_STADDR2
	291	li t1, 0x00000000
	292	sw t1, 0(t0)
ff36fd85	293	#endif
63f34912 WD	294
	295	/* RCE3 PCMCIA 250ns */
	296	li t0, MEM_STCFG3
	297	li t1, 0x00000002
	298	sw t1, 0(t0)
	299
	300	li t0, MEM_STTIME3
	301	li t1, 0x280E3E07
	302	sw t1, 0(t0)
	303
	304	li t0, MEM_STADDR3
	305	li t1, 0x10000000
	306	sw t1, 0(t0)
5da627a4	307
5da627a4 WD	308	sync
5da627a4 WD	309
63f34912 WD	310	/* Set peripherals to a known state */
	311	li t0, IC0_CFG0CLR
	312	li t1, 0xFFFFFFFF
	313	sw t1, 0(t0)
	314
	315	li t0, IC0_CFG0CLR
	316	sw t1, 0(t0)
	317
	318	li t0, IC0_CFG1CLR
	319	sw t1, 0(t0)
	320
	321	li t0, IC0_CFG2CLR
	322	sw t1, 0(t0)
	323
	324	li t0, IC0_SRCSET
	325	sw t1, 0(t0)
	326
	327	li t0, IC0_ASSIGNSET
	328	sw t1, 0(t0)
	329
	330	li t0, IC0_WAKECLR
	331	sw t1, 0(t0)
	332
	333	li t0, IC0_RISINGCLR
	334	sw t1, 0(t0)
	335
	336	li t0, IC0_FALLINGCLR
	337	sw t1, 0(t0)
	338
	339	li t0, IC0_TESTBIT
	340	li t1, 0x00000000
	341	sw t1, 0(t0)
5da627a4 WD	342	sync
5da627a4 WD	343
63f34912 WD	344	li t0, IC1_CFG0CLR
	345	li t1, 0xFFFFFFFF
	346	sw t1, 0(t0)
	347
	348	li t0, IC1_CFG0CLR
	349	sw t1, 0(t0)
	350
	351	li t0, IC1_CFG1CLR
	352	sw t1, 0(t0)
	353
	354	li t0, IC1_CFG2CLR
	355	sw t1, 0(t0)
	356
	357	li t0, IC1_SRCSET
	358	sw t1, 0(t0)
	359
	360	li t0, IC1_ASSIGNSET
	361	sw t1, 0(t0)
	362
	363	li t0, IC1_WAKECLR
	364	sw t1, 0(t0)
	365
	366	li t0, IC1_RISINGCLR
	367	sw t1, 0(t0)
	368
	369	li t0, IC1_FALLINGCLR
	370	sw t1, 0(t0)
	371
	372	li t0, IC1_TESTBIT
	373	li t1, 0x00000000
	374	sw t1, 0(t0)
5da627a4 WD	375	sync
5da627a4 WD	376
63f34912 WD	377	li t0, SYS_FREQCTRL0
	378	li t1, 0x00000000
	379	sw t1, 0(t0)
	380
	381	li t0, SYS_FREQCTRL1
	382	li t1, 0x00000000
	383	sw t1, 0(t0)
	384
	385	li t0, SYS_CLKSRC
	386	li t1, 0x00000000
	387	sw t1, 0(t0)
	388
	389	li t0, SYS_PININPUTEN
	390	li t1, 0x00000000
	391	sw t1, 0(t0)
5da627a4 WD	392	sync
5da627a4 WD	393
63f34912 WD	394	li t0, 0xB1100100
	395	li t1, 0x00000000
	396	sw t1, 0(t0)
5da627a4	397
63f34912 WD	398	li t0, 0xB1400100
	399	li t1, 0x00000000
	400	sw t1, 0(t0)
5da627a4	401
5da627a4	402
63f34912 WD	403	li t0, SYS_WAKEMSK
	404	li t1, 0x00000000
	405	sw t1, 0(t0)
5da627a4	406
63f34912 WD	407	li t0, SYS_WAKESRC
	408	li t1, 0x00000000
	409	sw t1, 0(t0)
5da627a4	410
63f34912 WD	411	/* wait 1mS before setup */
	412	li t1, MEM_1MS
	413	1: add t1, -1
	414	bne t1, zero, 1b
	415	nop
5da627a4	416
ff36fd85 WD	417	#ifdef CONFIG_DBAU1550
	418	/* SDCS 0,1,2 DDR SDRAM */
	419	li t0, MEM_SDMODE0
	420	li t1, 0x04276221
	421	sw t1, 0(t0)
	422
	423	li t0, MEM_SDMODE1
	424	li t1, 0x04276221
	425	sw t1, 0(t0)
	426
	427	li t0, MEM_SDMODE2
	428	li t1, 0x04276221
	429	sw t1, 0(t0)
	430
	431	li t0, MEM_SDADDR0
	432	li t1, 0xe21003f0
	433	sw t1, 0(t0)
	434
	435	li t0, MEM_SDADDR1
	436	li t1, 0xe21043f0
	437	sw t1, 0(t0)
	438
	439	li t0, MEM_SDADDR2
	440	li t1, 0xe21083f0
	441	sw t1, 0(t0)
	442
	443	sync
	444
	445	li t0, MEM_SDCONFIGA
	446	li t1, 0x9030060a /* Program refresh - disabled */
	447	sw t1, 0(t0)
	448	sync
	449
	450	li t0, MEM_SDCONFIGB
	451	li t1, 0x00028000
	452	sw t1, 0(t0)
	453	sync
	454
	455	li t0, MEM_SDPRECMD /* Precharge all */
	456	li t1, 0
	457	sw t1, 0(t0)
	458	sync
	459
	460	li t0, MEM_SDWRMD0
	461	li t1, 0x40000000
	462	sw t1, 0(t0)
	463	sync
	464
	465	li t0, MEM_SDWRMD1
	466	li t1, 0x40000000
	467	sw t1, 0(t0)
	468	sync
	469
	470	li t0, MEM_SDWRMD2
	471	li t1, 0x40000000
	472	sw t1, 0(t0)
	473	sync
	474
	475	li t0, MEM_SDWRMD0
	476	li t1, 0x00000063
	477	sw t1, 0(t0)
	478	sync
	479
	480	li t0, MEM_SDWRMD1
481	li t1, 0x00000063
482	sw t1, 0(t0)
483	sync
484
485	li t0, MEM_SDWRMD2
486	li t1, 0x00000063
487	sw t1, 0(t0)
488	sync
489
490	li t0, MEM_SDPRECMD /* Precharge all */
491	sw zero, 0(t0)
492	sync
493
494	/* Issue 2 autoref */
495	li t0, MEM_SDAUTOREF
496	sw zero, 0(t0)
497	sync
498
499	li t0, MEM_SDAUTOREF
500	sw zero, 0(t0)
501	sync
502
503	/* Enable refresh */
504	li t0, MEM_SDCONFIGA
505	li t1, 0x9830060a /* Program refresh - enabled */
506	sw t1, 0(t0)
507	sync
508
509	#else /* CONFIG_DBAU1550 */
63f34912 WD	510	/* SDCS 0,1 SDRAM */
	511	li t0, MEM_SDMODE0
	512	li t1, 0x005522AA
	513	sw t1, 0(t0)
5da627a4	514
63f34912 WD	515	li t0, MEM_SDMODE1
	516	li t1, 0x005522AA
	517	sw t1, 0(t0)
5da627a4	518
63f34912 WD	519	li t0, MEM_SDMODE2
	520	li t1, 0x00000000
	521	sw t1, 0(t0)
	522
	523	li t0, MEM_SDADDR0
	524	li t1, 0x001003F8
	525	sw t1, 0(t0)
	526
	527
	528	li t0, MEM_SDADDR1
	529	li t1, 0x001023F8
	530	sw t1, 0(t0)
	531
	532	li t0, MEM_SDADDR2
	533	li t1, 0x00000000
	534	sw t1, 0(t0)
	535
	536	sync
	537
	538	li t0, MEM_SDREFCFG
	539	li t1, 0x64000C24 /* Disable */
	540	sw t1, 0(t0)
	541	sync
	542
	543	li t0, MEM_SDPRECMD
	544	sw zero, 0(t0)
	545	sync
	546
	547	li t0, MEM_SDAUTOREF
	548	sw zero, 0(t0)
	549	sync
	550	sw zero, 0(t0)
	551	sync
	552
	553	li t0, MEM_SDREFCFG
	554	li t1, 0x66000C24 /* Enable */
	555	sw t1, 0(t0)
	556	sync
	557
	558	li t0, MEM_SDWRMD0
	559	li t1, 0x00000033
	560	sw t1, 0(t0)
	561	sync
	562
	563	li t0, MEM_SDWRMD1
	564	li t1, 0x00000033
	565	sw t1, 0(t0)
	566	sync
	567
ff36fd85	568	#endif /* CONFIG_DBAU1550 */
63f34912 WD	569	/* wait 1mS after setup */
	570	li t1, MEM_1MS
	571	1: add t1, -1
	572	bne t1, zero, 1b
	573	nop
5da627a4	574
63f34912 WD	575	li t0, SYS_PINFUNC
	576	li t1, 0x00008080
	577	sw t1, 0(t0)
5da627a4	578
63f34912 WD	579	li t0, SYS_TRIOUTCLR
	580	li t1, 0x00001FFF
	581	sw t1, 0(t0)
5da627a4	582
63f34912 WD	583	li t0, SYS_OUTPUTCLR
	584	li t1, 0x00008000
	585	sw t1, 0(t0)
5da627a4 WD	586	sync
5da627a4 WD	587
43c50925	588	jr ra
5da627a4	589	nop