[people/ms/u-boot.git] / board / digsy_mtc / digsy_mtc.c

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * (C) Copyright 2005-2009
 * Modified for InterControl digsyMTC MPC5200 board by
 * Frank Bodammer, GCD Hard- & Software GmbH,
 *                 frank.bodammer@gcd-solutions.de
 *
 * (C) Copyright 2009
 * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc5xxx.h>
#include <net.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/io.h>
#include "eeprom.h"
#if defined(CONFIG_DIGSY_REV5)
#include "is45s16800a2.h"
#include <mtd/cfi_flash.h>
#else
#include "is42s16800a-7t.h"
#endif
#include <libfdt.h>

DECLARE_GLOBAL_DATA_PTR;

extern int usb_cpu_init(void);

#if defined(CONFIG_DIGSY_REV5)
/*
 * The M29W128GH needs a specail reset command function,
 * details see the doc/README.cfi file
 */
void flash_cmd_reset(flash_info_t *info)
{
	flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
}
#endif

#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start(int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	long control = SDRAM_CONTROL | hi_addr_bit;

	/* unlock mode register */
	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);

	/* precharge all banks */
	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);

	/* auto refresh */
	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);

	/* set mode register */
	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);

	/* normal operation */
	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
 *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
 */

phys_size_t initdram(int board_type)
{
	ulong dramsize = 0;
	ulong dramsize2 = 0;
	uint svr, pvr;
#ifndef CONFIG_SYS_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */

	/* setup config registers */
	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20))
		dramsize = 0;

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
	} else {
		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
	}

	/* let SDRAM CS1 start right after CS0 */
	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);

	/* find RAM size using SDRAM CS1 only */
	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
			0x08000000);
		dramsize2 = test1;

	/* memory smaller than 1MB is impossible */
	if (dramsize2 < (1 << 20))
		dramsize2 = 0;

	/* set SDRAM CS1 size according to the amount of RAM found */
	if (dramsize2 > 0) {
		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
			(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
	} else {
		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
	}

#else /* CONFIG_SYS_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
	if (dramsize >= 0x13)
		dramsize = (1 << (dramsize - 0x13)) << 20;
	else
		dramsize = 0;

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
	if (dramsize2 >= 0x13)
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	else
		dramsize2 = 0;

#endif /* CONFIG_SYS_RAMBOOT */

	/*
	 * On MPC5200B we need to set the special configuration delay in the
	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	 *
	 * "The SDelay should be written to a value of 0x00000004. It is
	 * required to account for changes caused by normal wafer processing
	 * parameters."
	 */
	svr = get_svr();
	pvr = get_pvr();
	if ((SVR_MJREV(svr) >= 2) &&
	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);

	return dramsize + dramsize2;
}

int checkboard(void)
{
	char *s = getenv("serial#");

	puts ("Board: InterControl digsyMTC");
#if defined(CONFIG_DIGSY_REV5)
	puts (" rev5");
#endif
	if (s != NULL) {
		puts(", ");
		puts(s);
	}
	putc('\n');

	return 0;
}

int board_early_init_r(void)
{
#ifdef CONFIG_MPC52XX_SPI
	struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
#endif
	/*
	 * Now, when we are in RAM, enable flash write access for detection
	 * process.  Note that CS_BOOT cannot be cleared when executing in
	 * flash.
	 */
	/* disable CS_BOOT */
	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
	/* enable CS1 */
	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
	/* enable CS0 */
	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));

#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
	/* Low level USB init, required for proper kernel operation */
	usb_cpu_init();
#endif
#ifdef CONFIG_MPC52XX_SPI
	/* GPT 6 Output Enable */
	out_be32(&gpt[6].emsr, 0x00000034);
	/* GPT 7 Output Enable */
	out_be32(&gpt[7].emsr, 0x00000034);
#endif

	return (0);
}

void board_get_enetaddr (uchar * enet)
{
	ushort read = 0;
	ushort addr_of_eth_addr = 0;
	ushort len_sys = 0;
	ushort len_sys_cfg = 0;

	/* check identification word */
	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
	if (read != EEPROM_IDENT)
		return;

	/* calculate offset of config area */
	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
		(uchar *)&len_sys_cfg, 2);
	addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
	if (addr_of_eth_addr >= EEPROM_LEN)
		return;

	eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
}

int misc_init_r(void)
{
	uchar enetaddr[6];

	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
		board_get_enetaddr(enetaddr);
		eth_setenv_enetaddr("ethaddr", enetaddr);
	}

	return 0;
}

#ifdef CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif

#ifdef CONFIG_CMD_IDE

#ifdef CONFIG_IDE_RESET

void init_ide_reset(void)
{
	debug ("init_ide_reset\n");

	/* set gpio output value to 1 */
	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
	/* open drain output */
	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
	/* direction output */
	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
	/* enable gpio */
	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));

}

void ide_set_reset(int idereset)
{
	debug ("ide_reset(%d)\n", idereset);

	/* set gpio output value to 0 */
	clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
	/* open drain output */
	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
	/* direction output */
	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
	/* enable gpio */
	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));

	udelay(10000);

	/* set gpio output value to 1 */
	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
	/* open drain output */
	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
	/* direction output */
	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
	/* enable gpio */
	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
}
#endif /* CONFIG_IDE_RESET */
#endif /* CONFIG_CMD_IDE */

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
static void ft_delete_node(void *fdt, const char *compat)
{
	int off = -1;
	int ret;

	off = fdt_node_offset_by_compatible(fdt, -1, compat);
	if (off < 0) {
		printf("Could not find %s node.\n", compat);
		return;
	}

	ret = fdt_del_node(fdt, off);
	if (ret < 0)
		printf("Could not delete %s node.\n", compat);
}
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
static void ft_adapt_flash_base(void *blob)
{
	flash_info_t	*dev = &flash_info[0];
	int off;
	struct fdt_property *prop;
	int len;
	u32 *reg, *reg2;

	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
	if (off < 0) {
		printf("Could not find fsl,mpc5200b-lpb node.\n");
		return;
	}

	/* found compatible property */
	prop = fdt_get_property_w(blob, off, "ranges", &len);
	if (prop) {
		reg = reg2 = (u32 *)&prop->data[0];

		reg[2] = dev->start[0];
		reg[3] = dev->size;
		fdt_setprop(blob, off, "ranges", reg2, len);
	} else
		printf("Could not find ranges\n");
}

extern ulong flash_get_size (phys_addr_t base, int banknum);

/* Update the Flash Baseaddr settings */
int update_flash_size (int flash_size)
{
	volatile struct mpc5xxx_mmap_ctl *mm =
		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
	flash_info_t	*dev;
	int	i;
	int size = 0;
	unsigned long base = 0x0;
	u32 *cs_reg = (u32 *)&mm->cs0_start;

	for (i = 0; i < 2; i++) {
		dev = &flash_info[i];

		if (dev->size) {
			/* calculate new base addr for this chipselect */
			base -= dev->size;
			out_be32(cs_reg, START_REG(base));
			cs_reg++;
			out_be32(cs_reg, STOP_REG(base, dev->size));
			cs_reg++;
			/* recalculate the sectoraddr in the cfi driver */
			size += flash_get_size(base, i);
		}
	}
	gd->bd->bi_flashstart = base;
	return 0;
}
#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */

void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
	/*
	 * There are 2 RTC nodes in the DTS, so remove
	 * the unneeded node here.
	 */
#if defined(CONFIG_DIGSY_REV5)
	ft_delete_node(blob, "dallas,ds1339");
#else
	ft_delete_node(blob, "mc,rv3029c2");
#endif
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
	ft_adapt_flash_base(blob);
#endif
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
Commit	Line	Data
5c4fa9b4 GB	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
	8	* (C) Copyright 2005-2009
	9	* Modified for InterControl digsyMTC MPC5200 board by
	10	* Frank Bodammer, GCD Hard- & Software GmbH,
	11	* frank.bodammer@gcd-solutions.de
	12	*
	13	* (C) Copyright 2009
	14	* Grzegorz Bernacki, Semihalf, gjb@semihalf.com
	15	*
	16	* See file CREDITS for list of people who contributed to this
	17	* project.
	18	*
	19	* This program is free software; you can redistribute it and/or
	20	* modify it under the terms of the GNU General Public License as
	21	* published by the Free Software Foundation; either version 2 of
	22	* the License, or (at your option) any later version.
	23	*
	24	* This program is distributed in the hope that it will be useful,
	25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	27	* GNU General Public License for more details.
	28	*
	29	* You should have received a copy of the GNU General Public License
	30	* along with this program; if not, write to the Free Software
	31	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	32	* MA 02111-1307 USA
	33	*/
	34
	35	#include <common.h>
	36	#include <mpc5xxx.h>
	37	#include <net.h>
	38	#include <pci.h>
	39	#include <asm/processor.h>
	40	#include <asm/io.h>
	41	#include "eeprom.h"
466f0137 HS	42	#if defined(CONFIG_DIGSY_REV5)
	43	#include "is45s16800a2.h"
	44	#include <mtd/cfi_flash.h>
	45	#else
5c4fa9b4	46	#include "is42s16800a-7t.h"
466f0137 HS	47	#endif
466f0137 HS	48	#include <libfdt.h>
5c4fa9b4 GB	49
	50	DECLARE_GLOBAL_DATA_PTR;
	51
	52	extern int usb_cpu_init(void);
	53
466f0137 HS	54	#if defined(CONFIG_DIGSY_REV5)
	55	/*
	56	* The M29W128GH needs a specail reset command function,
	57	* details see the doc/README.cfi file
	58	*/
	59	void flash_cmd_reset(flash_info_t *info)
	60	{
	61	flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
	62	}
	63	#endif
	64
5c4fa9b4 GB	65	#ifndef CONFIG_SYS_RAMBOOT
	66	static void sdram_start(int hi_addr)
	67	{
	68	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	69	long control = SDRAM_CONTROL \| hi_addr_bit;
	70
	71	/* unlock mode register */
	72	out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000000);
	73
	74	/* precharge all banks */
	75	out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000002);
	76
	77	/* auto refresh */
	78	out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000004);
	79
	80	/* set mode register */
	81	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
	82
	83	/* normal operation */
	84	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
	85	}
	86	#endif
	87
	88	/*
	89	* ATTENTION: Although partially referenced initdram does NOT make real use
	90	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
	91	* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
	92	*/
	93
	94	phys_size_t initdram(int board_type)
	95	{
	96	ulong dramsize = 0;
	97	ulong dramsize2 = 0;
	98	uint svr, pvr;
	99	#ifndef CONFIG_SYS_RAMBOOT
	100	ulong test1, test2;
	101
	102	/* setup SDRAM chip selects */
	103	out_be32((void )MPC5XXX_SDRAM_CS0CFG, 0x0000001C); / 512MB at 0x0 */
	104	out_be32((void )MPC5XXX_SDRAM_CS1CFG, 0x80000000); / disabled */
	105
	106	/* setup config registers */
	107	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
	108	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
	109
	110	/* find RAM size using SDRAM CS0 only */
	111	sdram_start(0);
	112	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
	113	sdram_start(1);
	114	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
	115	if (test1 > test2) {
	116	sdram_start(0);
	117	dramsize = test1;
	118	} else {
	119	dramsize = test2;
	120	}
	121
	122	/* memory smaller than 1MB is impossible */
	123	if (dramsize < (1 << 20))
	124	dramsize = 0;
	125
	126	/* set SDRAM CS0 size according to the amount of RAM found */
	127	if (dramsize > 0) {
	128	out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
129	(0x13 + __builtin_ffs(dramsize >> 20) - 1));
130	} else {
131	out_be32((void )MPC5XXX_SDRAM_CS0CFG, 0); / disabled */
132	}
133
134	/* let SDRAM CS1 start right after CS0 */
135	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
136
137	/* find RAM size using SDRAM CS1 only */
138	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
139	0x08000000);
140	dramsize2 = test1;
141
142	/* memory smaller than 1MB is impossible */
143	if (dramsize2 < (1 << 20))
144	dramsize2 = 0;
145
146	/* set SDRAM CS1 size according to the amount of RAM found */
147	if (dramsize2 > 0) {
148	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize \|
149	(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
150	} else {
151	out_be32((void )MPC5XXX_SDRAM_CS1CFG, dramsize); / disabled */
152	}
153
154	#else /* CONFIG_SYS_RAMBOOT */
155
156	/* retrieve size of memory connected to SDRAM CS0 */
157	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
158	if (dramsize >= 0x13)
159	dramsize = (1 << (dramsize - 0x13)) << 20;
160	else
161	dramsize = 0;
162
163	/* retrieve size of memory connected to SDRAM CS1 */
164	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
165	if (dramsize2 >= 0x13)
166	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
167	else
168	dramsize2 = 0;
169
170	#endif /* CONFIG_SYS_RAMBOOT */
171
172	/*
173	* On MPC5200B we need to set the special configuration delay in the
174	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
175	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
176	*
177	* "The SDelay should be written to a value of 0x00000004. It is
178	* required to account for changes caused by normal wafer processing
179	* parameters."
180	*/
181	svr = get_svr();
182	pvr = get_pvr();
183	if ((SVR_MJREV(svr) >= 2) &&
184	(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
185	out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
186
187	return dramsize + dramsize2;
188	}
189
190	int checkboard(void)
191	{
192	char *s = getenv("serial#");
193
194	puts ("Board: InterControl digsyMTC");
466f0137 HS	195	#if defined(CONFIG_DIGSY_REV5)
	196	puts (" rev5");
	197	#endif
5c4fa9b4 GB	198	if (s != NULL) {
	199	puts(", ");
	200	puts(s);
	201	}
	202	putc('\n');
	203
	204	return 0;
	205	}
	206
	207	int board_early_init_r(void)
	208	{
f1f66edf GB	209	#ifdef CONFIG_MPC52XX_SPI
	210	struct mpc5xxx_gpt gpt = (struct mpc5xxx_gpt)MPC5XXX_GPT;
	211	#endif
5c4fa9b4 GB	212	/*
	213	* Now, when we are in RAM, enable flash write access for detection
	214	* process. Note that CS_BOOT cannot be cleared when executing in
	215	* flash.
	216	*/
	217	/* disable CS_BOOT */
	218	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
	219	/* enable CS1 */
	220	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
	221	/* enable CS0 */
	222	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
	223
	224	#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
	225	/* Low level USB init, required for proper kernel operation */
	226	usb_cpu_init();
	227	#endif
f1f66edf GB	228	#ifdef CONFIG_MPC52XX_SPI
	229	/* GPT 6 Output Enable */
	230	out_be32(&gpt[6].emsr, 0x00000034);
	231	/* GPT 7 Output Enable */
	232	out_be32(&gpt[7].emsr, 0x00000034);
	233	#endif
	234
5c4fa9b4 GB	235	return (0);
	236	}
	237
	238	void board_get_enetaddr (uchar * enet)
	239	{
	240	ushort read = 0;
	241	ushort addr_of_eth_addr = 0;
	242	ushort len_sys = 0;
	243	ushort len_sys_cfg = 0;
	244
	245	/* check identification word */
	246	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
	247	if (read != EEPROM_IDENT)
	248	return;
	249
	250	/* calculate offset of config area */
	251	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
	252	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
	253	(uchar *)&len_sys_cfg, 2);
	254	addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
	255	if (addr_of_eth_addr >= EEPROM_LEN)
	256	return;
	257
	258	eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
	259	}
	260
	261	int misc_init_r(void)
	262	{
	263	uchar enetaddr[6];
	264
	265	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
	266	board_get_enetaddr(enetaddr);
	267	eth_setenv_enetaddr("ethaddr", enetaddr);
	268	}
	269
	270	return 0;
	271	}
	272
	273	#ifdef CONFIG_PCI
	274	static struct pci_controller hose;
	275
	276	extern void pci_mpc5xxx_init(struct pci_controller *);
	277
	278	void pci_init_board(void)
	279	{
	280	pci_mpc5xxx_init(&hose);
	281	}
	282	#endif
	283
	284	#ifdef CONFIG_CMD_IDE
	285
	286	#ifdef CONFIG_IDE_RESET
	287
	288	void init_ide_reset(void)
	289	{
	290	debug ("init_ide_reset\n");
	291
	292	/* set gpio output value to 1 */
	293	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
	294	/* open drain output */
	295	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
	296	/* direction output */
	297	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
	298	/* enable gpio */
299	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
300
301	}
302
303	void ide_set_reset(int idereset)
304	{
305	debug ("ide_reset(%d)\n", idereset);
306
307	/* set gpio output value to 0 */
308	clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
309	/* open drain output */
310	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
311	/* direction output */
312	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
313	/* enable gpio */
314	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
315
316	udelay(10000);
317
318	/* set gpio output value to 1 */
319	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
320	/* open drain output */
321	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
322	/* direction output */
323	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
324	/* enable gpio */
325	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
326	}
327	#endif /* CONFIG_IDE_RESET */
466f0137	328	#endif /* CONFIG_CMD_IDE */
5c4fa9b4 GB	329
5c4fa9b4 GB	330	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
466f0137 HS	331	static void ft_delete_node(void fdt, const char compat)
	332	{
	333	int off = -1;
	334	int ret;
	335
	336	off = fdt_node_offset_by_compatible(fdt, -1, compat);
	337	if (off < 0) {
	338	printf("Could not find %s node.\n", compat);
	339	return;
	340	}
	341
	342	ret = fdt_del_node(fdt, off);
	343	if (ret < 0)
	344	printf("Could not delete %s node.\n", compat);
	345	}
	346	#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
	347	static void ft_adapt_flash_base(void *blob)
	348	{
	349	flash_info_t *dev = &flash_info[0];
	350	int off;
	351	struct fdt_property *prop;
	352	int len;
	353	u32 reg, reg2;
	354
	355	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
	356	if (off < 0) {
	357	printf("Could not find fsl,mpc5200b-lpb node.\n");
	358	return;
	359	}
	360
	361	/* found compatible property */
	362	prop = fdt_get_property_w(blob, off, "ranges", &len);
	363	if (prop) {
	364	reg = reg2 = (u32 *)&prop->data[0];
	365
	366	reg[2] = dev->start[0];
	367	reg[3] = dev->size;
	368	fdt_setprop(blob, off, "ranges", reg2, len);
	369	} else
	370	printf("Could not find ranges\n");
	371	}
	372
	373	extern ulong flash_get_size (phys_addr_t base, int banknum);
	374
	375	/* Update the Flash Baseaddr settings */
	376	int update_flash_size (int flash_size)
	377	{
	378	volatile struct mpc5xxx_mmap_ctl *mm =
	379	(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
	380	flash_info_t *dev;
	381	int i;
	382	int size = 0;
	383	unsigned long base = 0x0;
	384	u32 cs_reg = (u32 )&mm->cs0_start;
	385
	386	for (i = 0; i < 2; i++) {
	387	dev = &flash_info[i];
	388
	389	if (dev->size) {
	390	/* calculate new base addr for this chipselect */
	391	base -= dev->size;
	392	out_be32(cs_reg, START_REG(base));
	393	cs_reg++;
	394	out_be32(cs_reg, STOP_REG(base, dev->size));
395	cs_reg++;
396	/* recalculate the sectoraddr in the cfi driver */
397	size += flash_get_size(base, i);
398	}
399	}
400	gd->bd->bi_flashstart = base;
401	return 0;
402	}
403	#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
404
5c4fa9b4 GB	405	void ft_board_setup(void blob, bd_t bd)
	406	{
	407	ft_cpu_setup(blob, bd);
466f0137 HS	408	/*
	409	* There are 2 RTC nodes in the DTS, so remove
	410	* the unneeded node here.
	411	*/
	412	#if defined(CONFIG_DIGSY_REV5)
	413	ft_delete_node(blob, "dallas,ds1339");
	414	#else
	415	ft_delete_node(blob, "mc,rv3029c2");
	416	#endif
	417	#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
	418	ft_adapt_flash_base(blob);
	419	#endif
5c4fa9b4 GB	420	}
5c4fa9b4 GB	421	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */