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7ebf7443 WD |
1 | /* |
2 | * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
3 | * Andreas Heppel <aheppel@sysgo.de> | |
4 | * (C) Copyright 2001 ELTEC Elektronik AG | |
5 | * Frank Gottschling <fgottschling@eltec.de> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
27 | #include <command.h> | |
28 | #include <mpc106.h> | |
29 | #include <mk48t59.h> | |
30 | #include <74xx_7xx.h> | |
31 | #include <ns87308.h> | |
32 | #include <video_fb.h> | |
33 | ||
d87080b7 WD |
34 | DECLARE_GLOBAL_DATA_PTR; |
35 | ||
7ebf7443 WD |
36 | /*---------------------------------------------------------------------------*/ |
37 | /* | |
38 | * Get Bus clock frequency | |
39 | */ | |
40 | ulong bab7xx_get_bus_freq (void) | |
41 | { | |
bf9e3b38 WD |
42 | /* |
43 | * The GPIO Port 1 on BAB7xx reflects the bus speed. | |
44 | */ | |
45 | volatile struct GPIO *gpio = | |
46 | (struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE); | |
7ebf7443 | 47 | |
bf9e3b38 | 48 | unsigned char data = gpio->dta1; |
7ebf7443 | 49 | |
bf9e3b38 WD |
50 | if (data & 0x02) |
51 | return 66666666; | |
7ebf7443 | 52 | |
bf9e3b38 | 53 | return 83333333; |
7ebf7443 WD |
54 | } |
55 | ||
56 | /*---------------------------------------------------------------------------*/ | |
57 | ||
58 | /* | |
59 | * Measure CPU clock speed (core clock GCLK1) (Approx. GCLK frequency in Hz) | |
60 | */ | |
61 | ulong bab7xx_get_gclk_freq (void) | |
62 | { | |
bf9e3b38 WD |
63 | static const int pllratio_to_factor[] = { |
64 | 00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35, | |
65 | 00, | |
66 | }; | |
7ebf7443 | 67 | |
bf9e3b38 WD |
68 | return pllratio_to_factor[get_hid1 () >> 28] * |
69 | (bab7xx_get_bus_freq () / 10); | |
7ebf7443 WD |
70 | } |
71 | ||
72 | /*----------------------------------------------------------------------------*/ | |
73 | ||
74 | int checkcpu (void) | |
75 | { | |
bf9e3b38 | 76 | uint pvr = get_pvr (); |
7ebf7443 | 77 | |
bf9e3b38 WD |
78 | printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF); |
79 | printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000, | |
80 | bab7xx_get_bus_freq () / 1000000); | |
7ebf7443 | 81 | |
bf9e3b38 | 82 | return (0); |
7ebf7443 WD |
83 | } |
84 | ||
85 | /* ------------------------------------------------------------------------- */ | |
86 | ||
87 | int checkboard (void) | |
88 | { | |
89 | #ifdef CFG_ADDRESS_MAP_A | |
bf9e3b38 | 90 | puts ("Board: ELTEC BAB7xx PReP\n"); |
7ebf7443 | 91 | #else |
bf9e3b38 | 92 | puts ("Board: ELTEC BAB7xx CHRP\n"); |
7ebf7443 | 93 | #endif |
bf9e3b38 | 94 | return (0); |
7ebf7443 WD |
95 | } |
96 | ||
97 | /* ------------------------------------------------------------------------- */ | |
98 | ||
99 | int checkflash (void) | |
100 | { | |
bf9e3b38 WD |
101 | /* TODO: XXX XXX XXX */ |
102 | printf ("2 MB ## Test not implemented yet ##\n"); | |
103 | return (0); | |
7ebf7443 WD |
104 | } |
105 | ||
106 | /* ------------------------------------------------------------------------- */ | |
107 | ||
108 | ||
109 | static unsigned int mpc106_read_cfg_dword (unsigned int reg) | |
110 | { | |
bf9e3b38 | 111 | unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC); |
7ebf7443 | 112 | |
bf9e3b38 | 113 | out32r (MPC106_REG_ADDR, reg_addr); |
7ebf7443 | 114 | |
bf9e3b38 | 115 | return (in32r (MPC106_REG_DATA | (reg & 0x3))); |
7ebf7443 WD |
116 | } |
117 | ||
118 | /* ------------------------------------------------------------------------- */ | |
119 | ||
120 | long int dram_size (int board_type) | |
121 | { | |
bf9e3b38 WD |
122 | /* No actual initialisation to do - done when setting up |
123 | * PICRs MCCRs ME/SARs etc in ram_init.S. | |
124 | */ | |
7ebf7443 | 125 | |
bf9e3b38 | 126 | register unsigned long i, msar1, mear1, memSize; |
7ebf7443 WD |
127 | |
128 | #if defined(CFG_MEMTEST) | |
bf9e3b38 | 129 | register unsigned long reg; |
7ebf7443 | 130 | |
bf9e3b38 | 131 | printf ("Testing DRAM\n"); |
7ebf7443 | 132 | |
bf9e3b38 WD |
133 | /* write each mem addr with it's address */ |
134 | for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) | |
135 | *reg = reg; | |
7ebf7443 | 136 | |
bf9e3b38 WD |
137 | for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) { |
138 | if (*reg != reg) | |
139 | return -1; | |
140 | } | |
7ebf7443 WD |
141 | #endif |
142 | ||
bf9e3b38 WD |
143 | /* |
144 | * Since MPC106 memory controller chip has already been set to | |
145 | * control all memory, just read and interpret its memory boundery register. | |
146 | */ | |
147 | memSize = 0; | |
148 | msar1 = mpc106_read_cfg_dword (MPC106_MSAR1); | |
149 | mear1 = mpc106_read_cfg_dword (MPC106_MEAR1); | |
150 | i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf; | |
151 | ||
152 | do { | |
153 | if (i & 0x01) /* is bank enabled ? */ | |
154 | memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1; | |
155 | msar1 >>= 8; | |
156 | mear1 >>= 8; | |
157 | i >>= 1; | |
158 | } while (i); | |
159 | ||
160 | return (memSize * 0x100000); | |
7ebf7443 WD |
161 | } |
162 | ||
163 | /* ------------------------------------------------------------------------- */ | |
164 | ||
bf9e3b38 | 165 | long int initdram (int board_type) |
7ebf7443 | 166 | { |
bf9e3b38 | 167 | return dram_size (board_type); |
7ebf7443 WD |
168 | } |
169 | ||
170 | /* ------------------------------------------------------------------------- */ | |
171 | ||
172 | void after_reloc (ulong dest_addr) | |
173 | { | |
bf9e3b38 WD |
174 | /* |
175 | * Jump to the main U-Boot board init code | |
176 | */ | |
177 | board_init_r ((gd_t *) gd, dest_addr); | |
7ebf7443 WD |
178 | } |
179 | ||
180 | /* ------------------------------------------------------------------------- */ | |
181 | ||
182 | /* | |
183 | * do_reset is done here because in this case it is board specific, since the | |
184 | * 7xx CPUs can only be reset by external HW (the RTC in this case). | |
185 | */ | |
bf9e3b38 | 186 | void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) |
7ebf7443 WD |
187 | { |
188 | #if defined(CONFIG_RTC_MK48T59) | |
bf9e3b38 WD |
189 | /* trigger watchdog immediately */ |
190 | rtc_set_watchdog (1, RTC_WD_RB_16TH); | |
7ebf7443 | 191 | #else |
bf9e3b38 | 192 | #error "You must define the macro CONFIG_RTC_MK48T59." |
7ebf7443 WD |
193 | #endif |
194 | } | |
195 | ||
196 | /* ------------------------------------------------------------------------- */ | |
197 | ||
198 | #if defined(CONFIG_WATCHDOG) | |
199 | /* | |
200 | * Since the 7xx CPUs don't have an internal watchdog, this function is | |
201 | * board specific. We use the RTC here. | |
202 | */ | |
bf9e3b38 | 203 | void watchdog_reset (void) |
7ebf7443 WD |
204 | { |
205 | #if defined(CONFIG_RTC_MK48T59) | |
bf9e3b38 WD |
206 | /* we use a 32 sec watchdog timer */ |
207 | rtc_set_watchdog (8, RTC_WD_RB_4); | |
7ebf7443 | 208 | #else |
bf9e3b38 | 209 | #error "You must define the macro CONFIG_RTC_MK48T59." |
7ebf7443 WD |
210 | #endif |
211 | } | |
bf9e3b38 | 212 | #endif /* CONFIG_WATCHDOG */ |
7ebf7443 WD |
213 | |
214 | /* ------------------------------------------------------------------------- */ | |
215 | ||
216 | #ifdef CONFIG_CONSOLE_EXTRA_INFO | |
217 | extern GraphicDevice smi; | |
218 | ||
219 | void video_get_info_str (int line_number, char *info) | |
220 | { | |
bf9e3b38 WD |
221 | /* init video info strings for graphic console */ |
222 | switch (line_number) { | |
223 | case 1: | |
224 | sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz", | |
225 | (get_pvr () >> 8) & 0xFF, | |
226 | get_pvr () & 0xFF, | |
227 | bab7xx_get_gclk_freq () / 1000000, | |
228 | bab7xx_get_bus_freq () / 1000000); | |
229 | return; | |
230 | case 2: | |
231 | sprintf (info, | |
232 | " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH", | |
233 | dram_size (0) / 0x100000, flash_init () / 0x100000); | |
234 | return; | |
235 | case 3: | |
236 | sprintf (info, " %s", smi.modeIdent); | |
237 | return; | |
238 | } | |
239 | ||
240 | /* no more info lines */ | |
241 | *info = 0; | |
8bde7f77 | 242 | return; |
7ebf7443 WD |
243 | } |
244 | #endif | |
245 | ||
246 | /*---------------------------------------------------------------------------*/ |