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c1896004 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2003 | |
6 | * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
c1896004 WD |
9 | */ |
10 | ||
11 | #include <common.h> | |
12 | #include <mpc5xxx.h> | |
13 | #include <pci.h> | |
14 | ||
15 | /***************************************************************************** | |
16 | * initialize SDRAM/DDRAM controller. | |
17 | * TBD: get data from I2C EEPROM | |
18 | *****************************************************************************/ | |
9973e3c6 | 19 | phys_size_t initdram (int board_type) |
c1896004 WD |
20 | { |
21 | ulong dramsize = 0; | |
6d0f6bcf | 22 | #ifndef CONFIG_SYS_RAMBOOT |
d4ca31c4 | 23 | #if 0 |
c1896004 WD |
24 | ulong t; |
25 | ulong tap_del; | |
d4ca31c4 | 26 | #endif |
c1896004 WD |
27 | |
28 | #define MODE_EN 0x80000000 | |
29 | #define SOFT_PRE 2 | |
30 | #define SOFT_REF 4 | |
31 | ||
32 | /* configure SDRAM start/end */ | |
6d0f6bcf | 33 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | CONFIG_SYS_DRAM_RAM_SIZE; |
c1896004 WD |
34 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ |
35 | ||
36 | /* setup config registers */ | |
6d0f6bcf JCPV |
37 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CONFIG_SYS_DRAM_CONFIG1; |
38 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CONFIG_SYS_DRAM_CONFIG2; | |
c1896004 WD |
39 | |
40 | /* unlock mode register */ | |
6d0f6bcf | 41 | *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN; |
c1896004 | 42 | /* precharge all banks */ |
6d0f6bcf JCPV |
43 | *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE; |
44 | #ifdef CONFIG_SYS_DRAM_DDR | |
c1896004 | 45 | /* set extended mode register */ |
6d0f6bcf | 46 | *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_EMODE; |
c1896004 WD |
47 | #endif |
48 | /* set mode register */ | |
6d0f6bcf | 49 | *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE | 0x0400; |
c1896004 | 50 | /* precharge all banks */ |
6d0f6bcf | 51 | *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE; |
c1896004 | 52 | /* auto refresh */ |
6d0f6bcf | 53 | *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_REF; |
c1896004 | 54 | /* set mode register */ |
6d0f6bcf | 55 | *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE; |
c1896004 | 56 | /* normal operation */ |
6d0f6bcf | 57 | *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL; |
c1896004 | 58 | /* write default TAP delay */ |
6d0f6bcf | 59 | *(vu_long *)MPC5XXX_CDM_PORCFG = CONFIG_SYS_DRAM_TAP_DEL << 24; |
c1896004 WD |
60 | |
61 | #if 0 | |
d4ca31c4 WD |
62 | for (tap_del = 0; tap_del < 32; tap_del++) |
63 | { | |
c1896004 WD |
64 | *(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24; |
65 | ||
66 | printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG); | |
67 | for (t = 0; t < 0x04000000; t+=4) | |
68 | *(vu_long *) t = t; | |
69 | printf ("Checking DRAM...\n"); | |
d4ca31c4 WD |
70 | for (t = 0; t < 0x04000000; t+=4) |
71 | { | |
c1896004 | 72 | ulong rval = *(vu_long *) t; |
d4ca31c4 WD |
73 | if (rval != t) |
74 | { | |
c1896004 WD |
75 | printf ("mismatch at %x: ", t); |
76 | printf (" 1.read %x", rval); | |
77 | printf (" 2.read %x", *(vu_long *) t); | |
78 | printf (" 3.read %x", *(vu_long *) t); | |
79 | break; | |
80 | } | |
81 | } | |
82 | } | |
83 | #endif | |
6d0f6bcf | 84 | #endif /* CONFIG_SYS_RAMBOOT */ |
c1896004 WD |
85 | |
86 | dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20); | |
87 | ||
88 | /* return total ram size */ | |
89 | return dramsize; | |
90 | } | |
91 | ||
92 | /***************************************************************************** | |
93 | * print board identification | |
94 | *****************************************************************************/ | |
95 | int checkboard (void) | |
96 | { | |
97 | #if defined (CONFIG_EVAL5200) | |
98 | puts ("Board: EMK TOP5200 on EVAL5200\n"); | |
99 | #else | |
4d13cbad WD |
100 | #if defined (CONFIG_LITE5200) |
101 | puts ("Board: LITE5200\n"); | |
102 | #else | |
c1896004 WD |
103 | #if defined (CONFIG_MINI5200) |
104 | puts ("Board: EMK TOP5200 on MINI5200\n"); | |
105 | #else | |
106 | puts ("Board: EMK TOP5200\n"); | |
107 | #endif | |
4d13cbad | 108 | #endif |
c1896004 WD |
109 | #endif |
110 | return 0; | |
111 | } | |
112 | ||
113 | /***************************************************************************** | |
114 | * prepare for FLASH detection | |
115 | *****************************************************************************/ | |
116 | void flash_preinit(void) | |
117 | { | |
118 | /* | |
119 | * Now, when we are in RAM, enable flash write | |
120 | * access for detection process. | |
121 | * Note that CS_BOOT cannot be cleared when | |
122 | * executing in flash. | |
123 | */ | |
124 | *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ | |
125 | } | |
126 | ||
127 | /***************************************************************************** | |
128 | * finalize FLASH setup | |
129 | *****************************************************************************/ | |
130 | void flash_afterinit(uint bank, ulong start, ulong size) | |
131 | { | |
132 | if (bank == 0) { /* adjust mapping */ | |
133 | *(vu_long *)MPC5XXX_BOOTCS_START = | |
134 | *(vu_long *)MPC5XXX_CS0_START = START_REG(start); | |
135 | *(vu_long *)MPC5XXX_BOOTCS_STOP = | |
136 | *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(start, size); | |
137 | } | |
138 | } | |
139 | ||
140 | /***************************************************************************** | |
141 | * otherinits after RAM is there and we are relocated to RAM | |
142 | * note: though this is an int function, nobody cares for the result! | |
143 | *****************************************************************************/ | |
144 | int misc_init_r (void) | |
145 | { | |
4d13cbad | 146 | #if !defined (CONFIG_LITE5200) |
c1896004 | 147 | /* read 'factory' part of EEPROM */ |
63e73c9a WD |
148 | extern void read_factory_r (void); |
149 | read_factory_r (); | |
4d13cbad | 150 | #endif |
c1896004 WD |
151 | return (0); |
152 | } | |
153 | ||
154 | /***************************************************************************** | |
155 | * initialize the PCI system | |
156 | *****************************************************************************/ | |
157 | #ifdef CONFIG_PCI | |
158 | static struct pci_controller hose; | |
159 | ||
160 | extern void pci_mpc5xxx_init(struct pci_controller *); | |
161 | ||
162 | void pci_init_board(void) | |
163 | { | |
164 | pci_mpc5xxx_init(&hose); | |
165 | } | |
166 | #endif | |
4d13cbad WD |
167 | |
168 | /***************************************************************************** | |
498b8db7 | 169 | * provide the IDE Reset Function |
4d13cbad | 170 | *****************************************************************************/ |
77a31854 | 171 | #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) |
498b8db7 | 172 | |
498b8db7 WD |
173 | void init_ide_reset (void) |
174 | { | |
175 | debug ("init_ide_reset\n"); | |
176 | ||
dd520bf3 | 177 | /* Configure PSC1_4 as GPIO output for ATA reset */ |
498b8db7 WD |
178 | *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; |
179 | *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; | |
180 | } | |
181 | ||
4d13cbad WD |
182 | void ide_set_reset (int idereset) |
183 | { | |
498b8db7 WD |
184 | debug ("ide_reset(%d)\n", idereset); |
185 | ||
4d13cbad | 186 | if (idereset) { |
dae80f3c | 187 | *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; |
4d13cbad | 188 | } else { |
dae80f3c | 189 | *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; |
4d13cbad | 190 | } |
4d13cbad | 191 | } |
77a31854 | 192 | #endif |