[people/ms/u-boot.git] / board / engicam / common / spl.c

/*
 * Copyright (C) 2016 Amarula Solutions B.V.
 * Copyright (C) 2016 Engicam S.r.l.
 * Author: Jagan Teki <jagan@amarulasolutions.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <spl.h>

#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>

#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>

#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/video.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
        PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

static iomux_v3_cfg_t const uart_pads[] = {
#ifdef CONFIG_MX6QDL
        IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
        IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
#elif CONFIG_MX6UL
	IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
	IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
#endif
};

#ifdef CONFIG_MX6QDL
/*
 * Driving strength:
 *   0x30 == 40 Ohm
 *   0x28 == 48 Ohm
 */
#define IMX6DQ_DRIVE_STRENGTH		0x30
#define IMX6SDL_DRIVE_STRENGTH		0x28

/* configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
};

/* configure MX6Q/DUAL mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_ddrmode = 0x00020000,
	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
	.grp_ddr_type = 0x000c0000,
};

/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
};

/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
};

/* mt41j256 */
static struct mx6_ddr3_cfg mt41j256 = {
	.mem_speed = 1066,
	.density = 2,
	.width = 16,
	.banks = 8,
	.rowaddr = 13,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
	.SRT = 0,
};

static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
	.p0_mpwldectrl0 = 0x000E0009,
	.p0_mpwldectrl1 = 0x0018000E,
	.p1_mpwldectrl0 = 0x00000007,
	.p1_mpwldectrl1 = 0x00000000,
	.p0_mpdgctrl0 = 0x43280334,
	.p0_mpdgctrl1 = 0x031C0314,
	.p1_mpdgctrl0 = 0x4318031C,
	.p1_mpdgctrl1 = 0x030C0258,
	.p0_mprddlctl = 0x3E343A40,
	.p1_mprddlctl = 0x383C3844,
	.p0_mpwrdlctl = 0x40404440,
	.p1_mpwrdlctl = 0x4C3E4446,
};

/* DDR 64bit */
static struct mx6_ddr_sysinfo mem_q = {
	.ddr_type	= DDR_TYPE_DDR3,
	.dsize		= 2,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 2,
	.rtt_wr		= 2,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
};

static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
	.p0_mpwldectrl0 = 0x001F0024,
	.p0_mpwldectrl1 = 0x00110018,
	.p1_mpwldectrl0 = 0x001F0024,
	.p1_mpwldectrl1 = 0x00110018,
	.p0_mpdgctrl0 = 0x4230022C,
	.p0_mpdgctrl1 = 0x02180220,
	.p1_mpdgctrl0 = 0x42440248,
	.p1_mpdgctrl1 = 0x02300238,
	.p0_mprddlctl = 0x44444A48,
	.p1_mprddlctl = 0x46484A42,
	.p0_mpwrdlctl = 0x38383234,
	.p1_mpwrdlctl = 0x3C34362E,
};

/* DDR 64bit 1GB */
static struct mx6_ddr_sysinfo mem_dl = {
	.dsize		= 2,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 1,
	.rtt_wr		= 1,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
};

/* DDR 32bit 512MB */
static struct mx6_ddr_sysinfo mem_s = {
	.dsize		= 1,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 1,
	.rtt_wr		= 1,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
};
#endif /* CONFIG_MX6QDL */

#ifdef CONFIG_MX6UL
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
	.grp_addds = 0x00000030,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_b0ds = 0x00000030,
	.grp_ctlds = 0x00000030,
	.grp_b1ds = 0x00000030,
	.grp_ddrpke = 0x00000000,
	.grp_ddrmode = 0x00020000,
	.grp_ddr_type = 0x000c0000,
};

static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
	.dram_dqm0 = 0x00000030,
	.dram_dqm1 = 0x00000030,
	.dram_ras = 0x00000030,
	.dram_cas = 0x00000030,
	.dram_odt0 = 0x00000030,
	.dram_odt1 = 0x00000030,
	.dram_sdba2 = 0x00000000,
	.dram_sdclk_0 = 0x00000008,
	.dram_sdqs0 = 0x00000038,
	.dram_sdqs1 = 0x00000030,
	.dram_reset = 0x00000030,
};

static struct mx6_mmdc_calibration mx6_mmcd_calib = {
	.p0_mpwldectrl0 = 0x00070007,
	.p0_mpdgctrl0 = 0x41490145,
	.p0_mprddlctl = 0x40404546,
	.p0_mpwrdlctl = 0x4040524D,
};

struct mx6_ddr_sysinfo ddr_sysinfo = {
	.dsize = 0,
	.cs_density = 20,
	.ncs = 1,
	.cs1_mirror = 0,
	.rtt_wr = 2,
	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
	.walat = 1,		/* Write additional latency */
	.ralat = 5,		/* Read additional latency */
	.mif3_mode = 3,		/* Command prediction working mode */
	.bi_on = 1,		/* Bank interleaving enabled */
	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
	.ddr_type = DDR_TYPE_DDR3,
};

static struct mx6_ddr3_cfg mem_ddr = {
	.mem_speed = 800,
	.density = 4,
	.width = 16,
	.banks = 8,
#ifdef TARGET_MX6UL_ISIOT
	.rowaddr = 15,
#else
	.rowaddr = 13,
#endif
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};
#endif /* CONFIG_MX6UL */

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

#ifdef CONFIG_MX6QDL
	writel(0x00003F3F, &ccm->CCGR0);
	writel(0x0030FC00, &ccm->CCGR1);
	writel(0x000FC000, &ccm->CCGR2);
	writel(0x3F300000, &ccm->CCGR3);
	writel(0xFF00F300, &ccm->CCGR4);
	writel(0x0F0000C3, &ccm->CCGR5);
	writel(0x000003CC, &ccm->CCGR6);
#elif CONFIG_MX6UL
	writel(0x00c03f3f, &ccm->CCGR0);
	writel(0xfcffff00, &ccm->CCGR1);
	writel(0x0cffffcc, &ccm->CCGR2);
	writel(0x3f3c3030, &ccm->CCGR3);
	writel(0xff00fffc, &ccm->CCGR4);
	writel(0x033f30ff, &ccm->CCGR5);
	writel(0x00c00fff, &ccm->CCGR6);
#endif
}

static void gpr_init(void)
{
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	/* enable AXI cache for VDOA/VPU/IPU */
	writel(0xF00000CF, &iomux->gpr[4]);
	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	writel(0x007F007F, &iomux->gpr[6]);
	writel(0x007F007F, &iomux->gpr[7]);
}

static void spl_dram_init(void)
{
#ifdef CONFIG_MX6QDL
	if (is_mx6solo()) {
		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
		mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
	} else if (is_mx6dl()) {
		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
		mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
	} else if (is_mx6dq()) {
		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
		mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
	}
#elif CONFIG_MX6UL
	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
#endif

	udelay(100);
}

void board_init_f(ulong dummy)
{
	ccgr_init();

	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	gpr_init();

	/* iomux */
	SETUP_IOMUX_PADS(uart_pads);

	/* setup GP timer */
	timer_init();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* DDR initialization */
	spl_dram_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}
Commit	Line	Data
d8de3c73 JT	1	/*
	2	* Copyright (C) 2016 Amarula Solutions B.V.
	3	* Copyright (C) 2016 Engicam S.r.l.
	4	* Author: Jagan Teki <jagan@amarulasolutions.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <common.h>
	10	#include <spl.h>
	11
	12	#include <asm/io.h>
	13	#include <asm/gpio.h>
	14	#include <linux/sizes.h>
	15
	16	#include <asm/arch/clock.h>
	17	#include <asm/arch/crm_regs.h>
	18	#include <asm/arch/iomux.h>
	19	#include <asm/arch/mx6-ddr.h>
	20	#include <asm/arch/mx6-pins.h>
	21	#include <asm/arch/sys_proto.h>
	22
	23	#include <asm/imx-common/iomux-v3.h>
	24	#include <asm/imx-common/video.h>
	25
	26	DECLARE_GLOBAL_DATA_PTR;
	27
	28	#define UART_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	29	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	30	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	31
a81b0fd6 JT	32	static iomux_v3_cfg_t const uart_pads[] = {
a81b0fd6 JT	33	#ifdef CONFIG_MX6QDL
d8de3c73 JT	34	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
d8de3c73 JT	35	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
a81b0fd6 JT	36	#elif CONFIG_MX6UL
	37	IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX \| MUX_PAD_CTRL(UART_PAD_CTRL)),
	38	IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX \| MUX_PAD_CTRL(UART_PAD_CTRL)),
	39	#endif
d8de3c73 JT	40	};
d8de3c73 JT	41
a81b0fd6	42	#ifdef CONFIG_MX6QDL
d8de3c73 JT	43	/*
	44	* Driving strength:
	45	* 0x30 == 40 Ohm
	46	* 0x28 == 48 Ohm
	47	*/
	48	#define IMX6DQ_DRIVE_STRENGTH 0x30
	49	#define IMX6SDL_DRIVE_STRENGTH 0x28
	50
	51	/* configure MX6Q/DUAL mmdc DDR io registers */
	52	static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	53	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
	54	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
	55	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
	56	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
	57	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
	58	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
	59	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
	60	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
	61	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
	62	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
	63	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
	64	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
	65	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
	66	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
	67	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
	68	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
	69	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
	70	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
	71	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
	72	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
	73	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
	74	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
	75	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
	76	.dram_sdba2 = 0x00000000,
	77	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
	78	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
	79	};
	80
	81	/* configure MX6Q/DUAL mmdc GRP io registers */
	82	static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	83	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
	84	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
	85	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
	86	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
	87	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
	88	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
	89	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
	90	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
	91	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
	92	.grp_ddrmode_ctl = 0x00020000,
	93	.grp_ddrpke = 0x00000000,
	94	.grp_ddrmode = 0x00020000,
	95	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
	96	.grp_ddr_type = 0x000c0000,
	97	};
	98
	99	/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
	100	struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	101	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
	102	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
	103	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
	104	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
	105	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
	106	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
107	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
108	.dram_sdba2 = 0x00000000,
109	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
110	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
111	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
112	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
113	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
114	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
115	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
116	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
117	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
118	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
119	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
120	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
121	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
122	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
123	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
124	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
125	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
126	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
127	};
128
129	/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
130	struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
131	.grp_ddr_type = 0x000c0000,
132	.grp_ddrmode_ctl = 0x00020000,
133	.grp_ddrpke = 0x00000000,
134	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
135	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
136	.grp_ddrmode = 0x00020000,
137	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
138	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
139	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
140	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
141	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
142	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
143	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
144	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
145	};
146
147	/* mt41j256 */
148	static struct mx6_ddr3_cfg mt41j256 = {
149	.mem_speed = 1066,
150	.density = 2,
151	.width = 16,
152	.banks = 8,
153	.rowaddr = 13,
154	.coladdr = 10,
155	.pagesz = 2,
156	.trcd = 1375,
157	.trcmin = 4875,
158	.trasmin = 3500,
159	.SRT = 0,
160	};
161
162	static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
163	.p0_mpwldectrl0 = 0x000E0009,
164	.p0_mpwldectrl1 = 0x0018000E,
165	.p1_mpwldectrl0 = 0x00000007,
166	.p1_mpwldectrl1 = 0x00000000,
167	.p0_mpdgctrl0 = 0x43280334,
168	.p0_mpdgctrl1 = 0x031C0314,
169	.p1_mpdgctrl0 = 0x4318031C,
170	.p1_mpdgctrl1 = 0x030C0258,
171	.p0_mprddlctl = 0x3E343A40,
172	.p1_mprddlctl = 0x383C3844,
173	.p0_mpwrdlctl = 0x40404440,
174	.p1_mpwrdlctl = 0x4C3E4446,
175	};
176
177	/* DDR 64bit */
178	static struct mx6_ddr_sysinfo mem_q = {
179	.ddr_type = DDR_TYPE_DDR3,
180	.dsize = 2,
181	.cs1_mirror = 0,
182	/* config for full 4GB range so that get_mem_size() works */
183	.cs_density = 32,
184	.ncs = 1,
185	.bi_on = 1,
186	.rtt_nom = 2,
187	.rtt_wr = 2,
188	.ralat = 5,
189	.walat = 0,
190	.mif3_mode = 3,
191	.rst_to_cke = 0x23,
192	.sde_to_rst = 0x10,
193	};
194
195	static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
196	.p0_mpwldectrl0 = 0x001F0024,
197	.p0_mpwldectrl1 = 0x00110018,
198	.p1_mpwldectrl0 = 0x001F0024,
199	.p1_mpwldectrl1 = 0x00110018,
200	.p0_mpdgctrl0 = 0x4230022C,
201	.p0_mpdgctrl1 = 0x02180220,
202	.p1_mpdgctrl0 = 0x42440248,
203	.p1_mpdgctrl1 = 0x02300238,
204	.p0_mprddlctl = 0x44444A48,
205	.p1_mprddlctl = 0x46484A42,
206	.p0_mpwrdlctl = 0x38383234,
207	.p1_mpwrdlctl = 0x3C34362E,
208	};
209
210	/* DDR 64bit 1GB */
211	static struct mx6_ddr_sysinfo mem_dl = {
212	.dsize = 2,
213	.cs1_mirror = 0,
214	/* config for full 4GB range so that get_mem_size() works */
215	.cs_density = 32,
216	.ncs = 1,
217	.bi_on = 1,
218	.rtt_nom = 1,
219	.rtt_wr = 1,
220	.ralat = 5,
221	.walat = 0,
222	.mif3_mode = 3,
223	.rst_to_cke = 0x23,
224	.sde_to_rst = 0x10,
225	};
226
227	/* DDR 32bit 512MB */
228	static struct mx6_ddr_sysinfo mem_s = {
229	.dsize = 1,
230	.cs1_mirror = 0,
231	/* config for full 4GB range so that get_mem_size() works */
232	.cs_density = 32,
233	.ncs = 1,
234	.bi_on = 1,
235	.rtt_nom = 1,
236	.rtt_wr = 1,
237	.ralat = 5,
238	.walat = 0,
239	.mif3_mode = 3,
240	.rst_to_cke = 0x23,
241	.sde_to_rst = 0x10,
242	};
a81b0fd6 JT	243	#endif /* CONFIG_MX6QDL */
	244
	245	#ifdef CONFIG_MX6UL
	246	static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
	247	.grp_addds = 0x00000030,
	248	.grp_ddrmode_ctl = 0x00020000,
	249	.grp_b0ds = 0x00000030,
	250	.grp_ctlds = 0x00000030,
	251	.grp_b1ds = 0x00000030,
	252	.grp_ddrpke = 0x00000000,
	253	.grp_ddrmode = 0x00020000,
	254	.grp_ddr_type = 0x000c0000,
	255	};
	256
	257	static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
	258	.dram_dqm0 = 0x00000030,
	259	.dram_dqm1 = 0x00000030,
	260	.dram_ras = 0x00000030,
	261	.dram_cas = 0x00000030,
	262	.dram_odt0 = 0x00000030,
	263	.dram_odt1 = 0x00000030,
	264	.dram_sdba2 = 0x00000000,
	265	.dram_sdclk_0 = 0x00000008,
	266	.dram_sdqs0 = 0x00000038,
	267	.dram_sdqs1 = 0x00000030,
	268	.dram_reset = 0x00000030,
	269	};
	270
	271	static struct mx6_mmdc_calibration mx6_mmcd_calib = {
	272	.p0_mpwldectrl0 = 0x00070007,
	273	.p0_mpdgctrl0 = 0x41490145,
	274	.p0_mprddlctl = 0x40404546,
	275	.p0_mpwrdlctl = 0x4040524D,
	276	};
	277
	278	struct mx6_ddr_sysinfo ddr_sysinfo = {
	279	.dsize = 0,
	280	.cs_density = 20,
	281	.ncs = 1,
	282	.cs1_mirror = 0,
	283	.rtt_wr = 2,
	284	.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
	285	.walat = 1, /* Write additional latency */
	286	.ralat = 5, /* Read additional latency */
	287	.mif3_mode = 3, /* Command prediction working mode */
	288	.bi_on = 1, /* Bank interleaving enabled */
	289	.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
	290	.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
	291	.ddr_type = DDR_TYPE_DDR3,
	292	};
	293
	294	static struct mx6_ddr3_cfg mem_ddr = {
	295	.mem_speed = 800,
	296	.density = 4,
	297	.width = 16,
	298	.banks = 8,
	299	#ifdef TARGET_MX6UL_ISIOT
	300	.rowaddr = 15,
	301	#else
	302	.rowaddr = 13,
	303	#endif
	304	.coladdr = 10,
	305	.pagesz = 2,
	306	.trcd = 1375,
307	.trcmin = 4875,
308	.trasmin = 3500,
309	};
310	#endif /* CONFIG_MX6UL */
d8de3c73 JT	311
	312	static void ccgr_init(void)
	313	{
	314	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	315
a81b0fd6	316	#ifdef CONFIG_MX6QDL
d8de3c73 JT	317	writel(0x00003F3F, &ccm->CCGR0);
	318	writel(0x0030FC00, &ccm->CCGR1);
	319	writel(0x000FC000, &ccm->CCGR2);
	320	writel(0x3F300000, &ccm->CCGR3);
	321	writel(0xFF00F300, &ccm->CCGR4);
	322	writel(0x0F0000C3, &ccm->CCGR5);
	323	writel(0x000003CC, &ccm->CCGR6);
a81b0fd6 JT	324	#elif CONFIG_MX6UL
	325	writel(0x00c03f3f, &ccm->CCGR0);
	326	writel(0xfcffff00, &ccm->CCGR1);
	327	writel(0x0cffffcc, &ccm->CCGR2);
	328	writel(0x3f3c3030, &ccm->CCGR3);
	329	writel(0xff00fffc, &ccm->CCGR4);
	330	writel(0x033f30ff, &ccm->CCGR5);
	331	writel(0x00c00fff, &ccm->CCGR6);
	332	#endif
d8de3c73 JT	333	}
	334
	335	static void gpr_init(void)
	336	{
	337	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	338
	339	/* enable AXI cache for VDOA/VPU/IPU */
	340	writel(0xF00000CF, &iomux->gpr[4]);
	341	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	342	writel(0x007F007F, &iomux->gpr[6]);
	343	writel(0x007F007F, &iomux->gpr[7]);
	344	}
	345
	346	static void spl_dram_init(void)
	347	{
a81b0fd6	348	#ifdef CONFIG_MX6QDL
d8de3c73 JT	349	if (is_mx6solo()) {
	350	mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
	351	mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
	352	} else if (is_mx6dl()) {
	353	mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
	354	mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
	355	} else if (is_mx6dq()) {
	356	mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
	357	mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
	358	}
a81b0fd6 JT	359	#elif CONFIG_MX6UL
	360	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
	361	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
	362	#endif
d8de3c73 JT	363
	364	udelay(100);
	365	}
	366
	367	void board_init_f(ulong dummy)
	368	{
	369	ccgr_init();
	370
	371	/* setup AIPS and disable watchdog */
	372	arch_cpu_init();
	373
	374	gpr_init();
	375
	376	/* iomux */
a81b0fd6	377	SETUP_IOMUX_PADS(uart_pads);
d8de3c73 JT	378
	379	/* setup GP timer */
	380	timer_init();
	381
	382	/* UART clocks enabled and gd valid - init serial console */
	383	preloader_console_init();
	384
	385	/* DDR initialization */
	386	spl_dram_init();
	387
	388	/* Clear the BSS. */
	389	memset(__bss_start, 0, __bss_end - __bss_start);
	390
	391	/* load/boot image from boot device */
	392	board_init_r(NULL, 0);
	393	}