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f4b7532f JT |
1 | /* |
2 | * Copyright (C) 2016 Amarula Solutions B.V. | |
3 | * Copyright (C) 2016 Engicam S.r.l. | |
4 | * Author: Jagan Teki <jagan@amarulasolutions.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
f4b7532f JT |
10 | |
11 | #include <asm/io.h> | |
12 | #include <asm/gpio.h> | |
13 | #include <linux/sizes.h> | |
14 | ||
15 | #include <asm/arch/clock.h> | |
58413366 | 16 | #include <asm/arch/crm_regs.h> |
f4b7532f JT |
17 | #include <asm/arch/iomux.h> |
18 | #include <asm/arch/mx6-pins.h> | |
19 | #include <asm/arch/sys_proto.h> | |
20 | #include <asm/imx-common/iomux-v3.h> | |
ca7463c9 | 21 | #include <asm/imx-common/video.h> |
f4b7532f JT |
22 | |
23 | DECLARE_GLOBAL_DATA_PTR; | |
24 | ||
25 | #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
26 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ | |
27 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
28 | ||
f4b7532f JT |
29 | static iomux_v3_cfg_t const uart4_pads[] = { |
30 | IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
31 | IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
32 | }; | |
33 | ||
023ff2f7 JT |
34 | #ifdef CONFIG_NAND_MXS |
35 | ||
36 | #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) | |
37 | #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ | |
38 | PAD_CTL_SRE_FAST) | |
39 | #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) | |
40 | ||
41 | iomux_v3_cfg_t gpmi_pads[] = { | |
42 | IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
43 | IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
44 | IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
45 | IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)), | |
46 | IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
47 | IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
48 | IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
49 | IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
50 | IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
51 | IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
52 | IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
53 | IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
54 | IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
55 | IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
56 | IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
57 | }; | |
58 | ||
59 | static void setup_gpmi_nand(void) | |
60 | { | |
61 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
62 | ||
63 | /* config gpmi nand iomux */ | |
64 | SETUP_IOMUX_PADS(gpmi_pads); | |
65 | ||
66 | /* gate ENFC_CLK_ROOT clock first,before clk source switch */ | |
67 | clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
68 | ||
69 | /* config gpmi and bch clock to 100 MHz */ | |
70 | clrsetbits_le32(&mxc_ccm->cs2cdr, | |
71 | MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | | |
72 | MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | | |
73 | MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, | |
74 | MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | | |
75 | MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | | |
76 | MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); | |
77 | ||
78 | /* enable ENFC_CLK_ROOT clock */ | |
79 | setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
80 | ||
81 | /* enable gpmi and bch clock gating */ | |
82 | setbits_le32(&mxc_ccm->CCGR4, | |
83 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
84 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
85 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
86 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
87 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); | |
88 | ||
89 | /* enable apbh clock gating */ | |
90 | setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); | |
91 | } | |
92 | #endif | |
93 | ||
ca7463c9 JT |
94 | #if defined(CONFIG_VIDEO_IPUV3) |
95 | static iomux_v3_cfg_t const rgb_pads[] = { | |
96 | IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), | |
97 | IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), | |
98 | IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), | |
99 | IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), | |
100 | IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), | |
101 | IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), | |
102 | IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), | |
103 | IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), | |
104 | IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), | |
105 | IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), | |
106 | IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), | |
107 | IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), | |
108 | IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), | |
109 | IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), | |
110 | IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), | |
111 | IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), | |
112 | IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), | |
113 | IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), | |
114 | IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), | |
115 | IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), | |
116 | IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), | |
117 | IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), | |
118 | }; | |
119 | ||
120 | static void enable_rgb(struct display_info_t const *dev) | |
121 | { | |
122 | SETUP_IOMUX_PADS(rgb_pads); | |
123 | } | |
124 | ||
125 | struct display_info_t const displays[] = { | |
126 | { | |
127 | .bus = -1, | |
128 | .addr = 0, | |
129 | .pixfmt = IPU_PIX_FMT_RGB666, | |
130 | .detect = NULL, | |
131 | .enable = enable_rgb, | |
132 | .mode = { | |
133 | .name = "Amp-WD", | |
134 | .refresh = 60, | |
135 | .xres = 800, | |
136 | .yres = 480, | |
137 | .pixclock = 30000, | |
138 | .left_margin = 30, | |
139 | .right_margin = 30, | |
140 | .upper_margin = 5, | |
141 | .lower_margin = 5, | |
142 | .hsync_len = 64, | |
143 | .vsync_len = 20, | |
144 | .sync = FB_SYNC_EXT, | |
145 | .vmode = FB_VMODE_NONINTERLACED | |
146 | } | |
147 | }, | |
148 | }; | |
149 | ||
150 | size_t display_count = ARRAY_SIZE(displays); | |
151 | ||
152 | static void setup_display(void) | |
153 | { | |
154 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
155 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
156 | int reg; | |
157 | ||
158 | enable_ipu_clock(); | |
159 | ||
160 | /* Turn on LDB0,IPU,IPU DI0 clocks */ | |
161 | reg = __raw_readl(&mxc_ccm->CCGR3); | |
162 | reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff); | |
163 | writel(reg, &mxc_ccm->CCGR3); | |
164 | ||
165 | /* set LDB0, LDB1 clk select to 011/011 */ | |
166 | reg = readl(&mxc_ccm->cs2cdr); | |
167 | reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | | |
168 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); | |
169 | reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | | |
170 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); | |
171 | writel(reg, &mxc_ccm->cs2cdr); | |
172 | ||
173 | reg = readl(&mxc_ccm->cscmr2); | |
174 | reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; | |
175 | writel(reg, &mxc_ccm->cscmr2); | |
176 | ||
177 | reg = readl(&mxc_ccm->chsccdr); | |
178 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << | |
179 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); | |
180 | writel(reg, &mxc_ccm->chsccdr); | |
181 | ||
182 | reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | | |
183 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | | |
184 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | | |
185 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | | |
186 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | | |
187 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | | |
188 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | | |
189 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | | |
190 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; | |
191 | writel(reg, &iomux->gpr[2]); | |
192 | ||
193 | reg = readl(&iomux->gpr[3]); | |
194 | reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | | |
195 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << | |
196 | IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); | |
197 | writel(reg, &iomux->gpr[3]); | |
198 | } | |
199 | #endif /* CONFIG_VIDEO_IPUV3 */ | |
200 | ||
f4b7532f JT |
201 | int board_early_init_f(void) |
202 | { | |
203 | SETUP_IOMUX_PADS(uart4_pads); | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | int board_init(void) | |
209 | { | |
210 | /* Address of boot parameters */ | |
211 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
212 | ||
023ff2f7 JT |
213 | #ifdef CONFIG_NAND_MXS |
214 | setup_gpmi_nand(); | |
215 | #endif | |
ca7463c9 JT |
216 | |
217 | #ifdef CONFIG_VIDEO_IPUV3 | |
218 | setup_display(); | |
219 | #endif | |
220 | ||
f4b7532f JT |
221 | return 0; |
222 | } | |
223 | ||
224 | int dram_init(void) | |
225 | { | |
226 | gd->ram_size = imx_ddr_size(); | |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
231 | #ifdef CONFIG_SPL_BUILD | |
232 | #include <libfdt.h> | |
233 | #include <spl.h> | |
234 | ||
235 | #include <asm/arch/crm_regs.h> | |
236 | #include <asm/arch/mx6-ddr.h> | |
237 | ||
f160c5c8 JT |
238 | /* MMC board initialization is needed till adding DM support in SPL */ |
239 | #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) | |
240 | #include <mmc.h> | |
241 | #include <fsl_esdhc.h> | |
242 | ||
243 | #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
244 | PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ | |
245 | PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
246 | ||
247 | static iomux_v3_cfg_t const usdhc1_pads[] = { | |
248 | IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
249 | IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
250 | IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
251 | IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
252 | IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
253 | IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
254 | IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */ | |
255 | }; | |
256 | ||
257 | #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) | |
258 | ||
259 | struct fsl_esdhc_cfg usdhc_cfg[1] = { | |
260 | {USDHC1_BASE_ADDR, 0, 4}, | |
261 | }; | |
262 | ||
263 | int board_mmc_getcd(struct mmc *mmc) | |
264 | { | |
265 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | |
266 | int ret = 0; | |
267 | ||
268 | switch (cfg->esdhc_base) { | |
269 | case USDHC1_BASE_ADDR: | |
270 | ret = !gpio_get_value(USDHC1_CD_GPIO); | |
271 | break; | |
272 | } | |
273 | ||
274 | return ret; | |
275 | } | |
276 | ||
277 | int board_mmc_init(bd_t *bis) | |
278 | { | |
279 | int i, ret; | |
280 | ||
281 | /* | |
282 | * According to the board_mmc_init() the following map is done: | |
283 | * (U-boot device node) (Physical Port) | |
284 | * mmc0 USDHC1 | |
285 | */ | |
286 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { | |
287 | switch (i) { | |
288 | case 0: | |
289 | SETUP_IOMUX_PADS(usdhc1_pads); | |
290 | gpio_direction_input(USDHC1_CD_GPIO); | |
291 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); | |
292 | break; | |
293 | default: | |
294 | printf("Warning - USDHC%d controller not supporting\n", | |
295 | i + 1); | |
296 | return 0; | |
297 | } | |
298 | ||
299 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); | |
300 | if (ret) { | |
301 | printf("Warning: failed to initialize mmc dev %d\n", i); | |
302 | return ret; | |
303 | } | |
304 | } | |
305 | ||
306 | return 0; | |
307 | } | |
308 | #endif | |
309 | ||
f4b7532f JT |
310 | /* |
311 | * Driving strength: | |
312 | * 0x30 == 40 Ohm | |
313 | * 0x28 == 48 Ohm | |
314 | */ | |
315 | ||
316 | #define IMX6DQ_DRIVE_STRENGTH 0x30 | |
317 | #define IMX6SDL_DRIVE_STRENGTH 0x28 | |
318 | ||
319 | /* configure MX6Q/DUAL mmdc DDR io registers */ | |
320 | static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { | |
321 | .dram_sdqs0 = 0x28, | |
322 | .dram_sdqs1 = 0x28, | |
323 | .dram_sdqs2 = 0x28, | |
324 | .dram_sdqs3 = 0x28, | |
325 | .dram_sdqs4 = 0x28, | |
326 | .dram_sdqs5 = 0x28, | |
327 | .dram_sdqs6 = 0x28, | |
328 | .dram_sdqs7 = 0x28, | |
329 | .dram_dqm0 = 0x28, | |
330 | .dram_dqm1 = 0x28, | |
331 | .dram_dqm2 = 0x28, | |
332 | .dram_dqm3 = 0x28, | |
333 | .dram_dqm4 = 0x28, | |
334 | .dram_dqm5 = 0x28, | |
335 | .dram_dqm6 = 0x28, | |
336 | .dram_dqm7 = 0x28, | |
337 | .dram_cas = 0x30, | |
338 | .dram_ras = 0x30, | |
339 | .dram_sdclk_0 = 0x30, | |
340 | .dram_sdclk_1 = 0x30, | |
341 | .dram_reset = 0x30, | |
342 | .dram_sdcke0 = 0x3000, | |
343 | .dram_sdcke1 = 0x3000, | |
344 | .dram_sdba2 = 0x00000000, | |
345 | .dram_sdodt0 = 0x30, | |
346 | .dram_sdodt1 = 0x30, | |
347 | }; | |
348 | ||
349 | /* configure MX6Q/DUAL mmdc GRP io registers */ | |
350 | static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { | |
351 | .grp_b0ds = 0x30, | |
352 | .grp_b1ds = 0x30, | |
353 | .grp_b2ds = 0x30, | |
354 | .grp_b3ds = 0x30, | |
355 | .grp_b4ds = 0x30, | |
356 | .grp_b5ds = 0x30, | |
357 | .grp_b6ds = 0x30, | |
358 | .grp_b7ds = 0x30, | |
359 | .grp_addds = 0x30, | |
360 | .grp_ddrmode_ctl = 0x00020000, | |
361 | .grp_ddrpke = 0x00000000, | |
362 | .grp_ddrmode = 0x00020000, | |
363 | .grp_ctlds = 0x30, | |
364 | .grp_ddr_type = 0x000c0000, | |
365 | }; | |
366 | ||
367 | /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ | |
368 | struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { | |
369 | .dram_sdclk_0 = 0x30, | |
370 | .dram_sdclk_1 = 0x30, | |
371 | .dram_cas = 0x30, | |
372 | .dram_ras = 0x30, | |
373 | .dram_reset = 0x30, | |
374 | .dram_sdcke0 = 0x30, | |
375 | .dram_sdcke1 = 0x30, | |
376 | .dram_sdba2 = 0x00000000, | |
377 | .dram_sdodt0 = 0x30, | |
378 | .dram_sdodt1 = 0x30, | |
379 | .dram_sdqs0 = 0x28, | |
380 | .dram_sdqs1 = 0x28, | |
381 | .dram_sdqs2 = 0x28, | |
382 | .dram_sdqs3 = 0x28, | |
383 | .dram_sdqs4 = 0x28, | |
384 | .dram_sdqs5 = 0x28, | |
385 | .dram_sdqs6 = 0x28, | |
386 | .dram_sdqs7 = 0x28, | |
387 | .dram_dqm0 = 0x28, | |
388 | .dram_dqm1 = 0x28, | |
389 | .dram_dqm2 = 0x28, | |
390 | .dram_dqm3 = 0x28, | |
391 | .dram_dqm4 = 0x28, | |
392 | .dram_dqm5 = 0x28, | |
393 | .dram_dqm6 = 0x28, | |
394 | .dram_dqm7 = 0x28, | |
395 | }; | |
396 | ||
397 | /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ | |
398 | struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { | |
399 | .grp_ddr_type = 0x000c0000, | |
400 | .grp_ddrmode_ctl = 0x00020000, | |
401 | .grp_ddrpke = 0x00000000, | |
402 | .grp_addds = 0x30, | |
403 | .grp_ctlds = 0x30, | |
404 | .grp_ddrmode = 0x00020000, | |
405 | .grp_b0ds = 0x28, | |
406 | .grp_b1ds = 0x28, | |
407 | .grp_b2ds = 0x28, | |
408 | .grp_b3ds = 0x28, | |
409 | .grp_b4ds = 0x28, | |
410 | .grp_b5ds = 0x28, | |
411 | .grp_b6ds = 0x28, | |
412 | .grp_b7ds = 0x28, | |
413 | }; | |
414 | ||
415 | /* mt41j256 */ | |
416 | static struct mx6_ddr3_cfg mt41j256 = { | |
417 | .mem_speed = 1066, | |
418 | .density = 2, | |
419 | .width = 16, | |
420 | .banks = 8, | |
421 | .rowaddr = 13, | |
422 | .coladdr = 10, | |
423 | .pagesz = 2, | |
424 | .trcd = 1375, | |
425 | .trcmin = 4875, | |
426 | .trasmin = 3500, | |
427 | .SRT = 0, | |
428 | }; | |
429 | ||
430 | static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { | |
431 | .p0_mpwldectrl0 = 0x000E0009, | |
432 | .p0_mpwldectrl1 = 0x0018000E, | |
433 | .p1_mpwldectrl0 = 0x00000007, | |
434 | .p1_mpwldectrl1 = 0x00000000, | |
435 | .p0_mpdgctrl0 = 0x43280334, | |
436 | .p0_mpdgctrl1 = 0x031C0314, | |
437 | .p1_mpdgctrl0 = 0x4318031C, | |
438 | .p1_mpdgctrl1 = 0x030C0258, | |
439 | .p0_mprddlctl = 0x3E343A40, | |
440 | .p1_mprddlctl = 0x383C3844, | |
441 | .p0_mpwrdlctl = 0x40404440, | |
442 | .p1_mpwrdlctl = 0x4C3E4446, | |
443 | }; | |
444 | ||
445 | /* DDR 64bit */ | |
446 | static struct mx6_ddr_sysinfo mem_q = { | |
447 | .ddr_type = DDR_TYPE_DDR3, | |
448 | .dsize = 2, | |
449 | .cs1_mirror = 0, | |
450 | /* config for full 4GB range so that get_mem_size() works */ | |
451 | .cs_density = 32, | |
452 | .ncs = 1, | |
453 | .bi_on = 1, | |
454 | .rtt_nom = 2, | |
455 | .rtt_wr = 2, | |
456 | .ralat = 5, | |
457 | .walat = 0, | |
458 | .mif3_mode = 3, | |
459 | .rst_to_cke = 0x23, | |
460 | .sde_to_rst = 0x10, | |
461 | }; | |
462 | ||
463 | static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { | |
464 | .p0_mpwldectrl0 = 0x001F0024, | |
465 | .p0_mpwldectrl1 = 0x00110018, | |
466 | .p1_mpwldectrl0 = 0x001F0024, | |
467 | .p1_mpwldectrl1 = 0x00110018, | |
468 | .p0_mpdgctrl0 = 0x4230022C, | |
469 | .p0_mpdgctrl1 = 0x02180220, | |
470 | .p1_mpdgctrl0 = 0x42440248, | |
471 | .p1_mpdgctrl1 = 0x02300238, | |
472 | .p0_mprddlctl = 0x44444A48, | |
473 | .p1_mprddlctl = 0x46484A42, | |
474 | .p0_mpwrdlctl = 0x38383234, | |
475 | .p1_mpwrdlctl = 0x3C34362E, | |
476 | }; | |
477 | ||
478 | /* DDR 64bit 1GB */ | |
479 | static struct mx6_ddr_sysinfo mem_dl = { | |
480 | .dsize = 2, | |
481 | .cs1_mirror = 0, | |
482 | /* config for full 4GB range so that get_mem_size() works */ | |
483 | .cs_density = 32, | |
484 | .ncs = 1, | |
485 | .bi_on = 1, | |
486 | .rtt_nom = 1, | |
487 | .rtt_wr = 1, | |
488 | .ralat = 5, | |
489 | .walat = 0, | |
490 | .mif3_mode = 3, | |
491 | .rst_to_cke = 0x23, | |
492 | .sde_to_rst = 0x10, | |
493 | }; | |
494 | ||
495 | /* DDR 32bit 512MB */ | |
496 | static struct mx6_ddr_sysinfo mem_s = { | |
497 | .dsize = 1, | |
498 | .cs1_mirror = 0, | |
499 | /* config for full 4GB range so that get_mem_size() works */ | |
500 | .cs_density = 32, | |
501 | .ncs = 1, | |
502 | .bi_on = 1, | |
503 | .rtt_nom = 1, | |
504 | .rtt_wr = 1, | |
505 | .ralat = 5, | |
506 | .walat = 0, | |
507 | .mif3_mode = 3, | |
508 | .rst_to_cke = 0x23, | |
509 | .sde_to_rst = 0x10, | |
510 | }; | |
511 | ||
512 | static void ccgr_init(void) | |
513 | { | |
514 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
515 | ||
516 | writel(0x00003F3F, &ccm->CCGR0); | |
517 | writel(0x0030FC00, &ccm->CCGR1); | |
518 | writel(0x000FC000, &ccm->CCGR2); | |
519 | writel(0x3F300000, &ccm->CCGR3); | |
520 | writel(0xFF00F300, &ccm->CCGR4); | |
521 | writel(0x0F0000C3, &ccm->CCGR5); | |
522 | writel(0x000003CC, &ccm->CCGR6); | |
523 | } | |
524 | ||
525 | static void gpr_init(void) | |
526 | { | |
527 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
528 | ||
529 | /* enable AXI cache for VDOA/VPU/IPU */ | |
530 | writel(0xF00000CF, &iomux->gpr[4]); | |
531 | /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ | |
532 | writel(0x007F007F, &iomux->gpr[6]); | |
533 | writel(0x007F007F, &iomux->gpr[7]); | |
534 | } | |
535 | ||
536 | static void spl_dram_init(void) | |
537 | { | |
538 | if (is_mx6solo()) { | |
539 | mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); | |
540 | mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); | |
541 | } else if (is_mx6dl()) { | |
542 | mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); | |
543 | mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); | |
544 | } else if (is_mx6dq()) { | |
545 | mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); | |
546 | mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); | |
547 | } | |
548 | ||
549 | udelay(100); | |
550 | } | |
551 | ||
552 | void board_init_f(ulong dummy) | |
553 | { | |
554 | ccgr_init(); | |
555 | ||
556 | /* setup AIPS and disable watchdog */ | |
557 | arch_cpu_init(); | |
558 | ||
559 | gpr_init(); | |
560 | ||
561 | /* iomux */ | |
562 | board_early_init_f(); | |
563 | ||
564 | /* setup GP timer */ | |
565 | timer_init(); | |
566 | ||
567 | /* UART clocks enabled and gd valid - init serial console */ | |
568 | preloader_console_init(); | |
569 | ||
570 | /* DDR initialization */ | |
571 | spl_dram_init(); | |
572 | ||
573 | /* Clear the BSS. */ | |
574 | memset(__bss_start, 0, __bss_end - __bss_start); | |
575 | ||
576 | /* load/boot image from boot device */ | |
577 | board_init_r(NULL, 0); | |
578 | } | |
579 | #endif |