[people/ms/u-boot.git] / board / engicam / icorem6_rqs / icorem6_rqs.c

/*
 * Copyright (C) 2016 Amarula Solutions B.V.
 * Copyright (C) 2016 Engicam S.r.l.
 * Author: Jagan Teki <jagan@amarulasolutions.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>

#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>

#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/iomux-v3.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

static iomux_v3_cfg_t const uart4_pads[] = {
	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};

int board_early_init_f(void)
{
	SETUP_IOMUX_PADS(uart4_pads);

	return 0;
}

int board_init(void)
{
	/* Address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	return 0;
}

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

#ifdef CONFIG_SPL_BUILD
#include <libfdt.h>
#include <spl.h>

#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>

/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
#include <fsl_esdhc.h>

#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_HIGH |               \
	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

static iomux_v3_cfg_t const usdhc3_pads[] = {
	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};

static iomux_v3_cfg_t const usdhc4_pads[] = {
	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};

struct fsl_esdhc_cfg usdhc_cfg[2] = {
	{USDHC3_BASE_ADDR, 1, 4},
	{USDHC4_BASE_ADDR, 1, 8},
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC3_BASE_ADDR:
	case USDHC4_BASE_ADDR:
		ret = 1;
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	int i, ret;

	/*
	* According to the board_mmc_init() the following map is done:
	* (U-boot device node)    (Physical Port)
	* mmc0			USDHC3
	* mmc1			USDHC4
	*/
	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
		switch (i) {
		case 0:
			SETUP_IOMUX_PADS(usdhc3_pads);
			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
			break;
		case 1:
			SETUP_IOMUX_PADS(usdhc4_pads);
			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
			break;
		default:
			printf("Warning - USDHC%d controller not supporting\n",
			       i + 1);
			return 0;
		}

		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		if (ret) {
			printf("Warning: failed to initialize mmc dev %d\n", i);
			return ret;
		}
	}

	return 0;
}

#ifdef CONFIG_ENV_IS_IN_MMC
void board_boot_order(u32 *spl_boot_list)
{
	u32 bmode = imx6_src_get_boot_mode();
	u8 boot_dev = BOOT_DEVICE_MMC1;

	switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
	case IMX6_BMODE_SD:
	case IMX6_BMODE_ESD:
		/* SD/eSD - BOOT_DEVICE_MMC1 */
		break;
	case IMX6_BMODE_MMC:
	case IMX6_BMODE_EMMC:
		/* MMC/eMMC */
		boot_dev = BOOT_DEVICE_MMC2;
		break;
	default:
		/* Default - BOOT_DEVICE_MMC1 */
		printf("Wrong board boot order\n");
		break;
	}

	spl_boot_list[0] = boot_dev;
}
#endif
#endif

/*
 * Driving strength:
 *   0x30 == 40 Ohm
 *   0x28 == 48 Ohm
 */

#define IMX6DQ_DRIVE_STRENGTH		0x30
#define IMX6SDL_DRIVE_STRENGTH		0x28

/* configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	.dram_sdqs0 = 0x28,
	.dram_sdqs1 = 0x28,
	.dram_sdqs2 = 0x28,
	.dram_sdqs3 = 0x28,
	.dram_sdqs4 = 0x28,
	.dram_sdqs5 = 0x28,
	.dram_sdqs6 = 0x28,
	.dram_sdqs7 = 0x28,
	.dram_dqm0 = 0x28,
	.dram_dqm1 = 0x28,
	.dram_dqm2 = 0x28,
	.dram_dqm3 = 0x28,
	.dram_dqm4 = 0x28,
	.dram_dqm5 = 0x28,
	.dram_dqm6 = 0x28,
	.dram_dqm7 = 0x28,
	.dram_cas = 0x30,
	.dram_ras = 0x30,
	.dram_sdclk_0 = 0x30,
	.dram_sdclk_1 = 0x30,
	.dram_reset = 0x30,
	.dram_sdcke0 = 0x3000,
	.dram_sdcke1 = 0x3000,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = 0x30,
	.dram_sdodt1 = 0x30,
};

/* configure MX6Q/DUAL mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	.grp_b0ds = 0x30,
	.grp_b1ds = 0x30,
	.grp_b2ds = 0x30,
	.grp_b3ds = 0x30,
	.grp_b4ds = 0x30,
	.grp_b5ds = 0x30,
	.grp_b6ds = 0x30,
	.grp_b7ds = 0x30,
	.grp_addds = 0x30,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_ddrmode = 0x00020000,
	.grp_ctlds = 0x30,
	.grp_ddr_type = 0x000c0000,
};

/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	.dram_sdclk_0 = 0x30,
	.dram_sdclk_1 = 0x30,
	.dram_cas = 0x30,
	.dram_ras = 0x30,
	.dram_reset = 0x30,
	.dram_sdcke0 = 0x30,
	.dram_sdcke1 = 0x30,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = 0x30,
	.dram_sdodt1 = 0x30,
	.dram_sdqs0 = 0x28,
	.dram_sdqs1 = 0x28,
	.dram_sdqs2 = 0x28,
	.dram_sdqs3 = 0x28,
	.dram_sdqs4 = 0x28,
	.dram_sdqs5 = 0x28,
	.dram_sdqs6 = 0x28,
	.dram_sdqs7 = 0x28,
	.dram_dqm0 = 0x28,
	.dram_dqm1 = 0x28,
	.dram_dqm2 = 0x28,
	.dram_dqm3 = 0x28,
	.dram_dqm4 = 0x28,
	.dram_dqm5 = 0x28,
	.dram_dqm6 = 0x28,
	.dram_dqm7 = 0x28,
};

/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_addds = 0x30,
	.grp_ctlds = 0x30,
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = 0x28,
	.grp_b1ds = 0x28,
	.grp_b2ds = 0x28,
	.grp_b3ds = 0x28,
	.grp_b4ds = 0x28,
	.grp_b5ds = 0x28,
	.grp_b6ds = 0x28,
	.grp_b7ds = 0x28,
};

/* mt41j256 */
static struct mx6_ddr3_cfg mt41j256 = {
	.mem_speed = 1066,
	.density = 2,
	.width = 16,
	.banks = 8,
	.rowaddr = 13,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
	.SRT = 0,
};

static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
	.p0_mpwldectrl0 = 0x000E0009,
	.p0_mpwldectrl1 = 0x0018000E,
	.p1_mpwldectrl0 = 0x00000007,
	.p1_mpwldectrl1 = 0x00000000,
	.p0_mpdgctrl0 = 0x43280334,
	.p0_mpdgctrl1 = 0x031C0314,
	.p1_mpdgctrl0 = 0x4318031C,
	.p1_mpdgctrl1 = 0x030C0258,
	.p0_mprddlctl = 0x3E343A40,
	.p1_mprddlctl = 0x383C3844,
	.p0_mpwrdlctl = 0x40404440,
	.p1_mpwrdlctl = 0x4C3E4446,
};

/* DDR 64bit */
static struct mx6_ddr_sysinfo mem_q = {
	.ddr_type	= DDR_TYPE_DDR3,
	.dsize		= 2,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 2,
	.rtt_wr		= 2,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
};

static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
	.p0_mpwldectrl0 = 0x001F0024,
	.p0_mpwldectrl1 = 0x00110018,
	.p1_mpwldectrl0 = 0x001F0024,
	.p1_mpwldectrl1 = 0x00110018,
	.p0_mpdgctrl0 = 0x4230022C,
	.p0_mpdgctrl1 = 0x02180220,
	.p1_mpdgctrl0 = 0x42440248,
	.p1_mpdgctrl1 = 0x02300238,
	.p0_mprddlctl = 0x44444A48,
	.p1_mprddlctl = 0x46484A42,
	.p0_mpwrdlctl = 0x38383234,
	.p1_mpwrdlctl = 0x3C34362E,
};

/* DDR 64bit 1GB */
static struct mx6_ddr_sysinfo mem_dl = {
	.dsize		= 2,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 1,
	.rtt_wr		= 1,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
};

/* DDR 32bit 512MB */
static struct mx6_ddr_sysinfo mem_s = {
	.dsize		= 1,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 1,
	.rtt_wr		= 1,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
};

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0x00003F3F, &ccm->CCGR0);
	writel(0x0030FC00, &ccm->CCGR1);
	writel(0x000FC000, &ccm->CCGR2);
	writel(0x3F300000, &ccm->CCGR3);
	writel(0xFF00F300, &ccm->CCGR4);
	writel(0x0F0000C3, &ccm->CCGR5);
	writel(0x000003CC, &ccm->CCGR6);
}

static void gpr_init(void)
{
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	/* enable AXI cache for VDOA/VPU/IPU */
	writel(0xF00000CF, &iomux->gpr[4]);
	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	writel(0x007F007F, &iomux->gpr[6]);
	writel(0x007F007F, &iomux->gpr[7]);
}

static void spl_dram_init(void)
{
	if (is_mx6solo()) {
		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
		mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
	} else if (is_mx6dl()) {
		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
		mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
	} else if (is_mx6dq()) {
		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
		mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
	}

	udelay(100);
}

void board_init_f(ulong dummy)
{
	ccgr_init();

	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	gpr_init();

	/* iomux */
	board_early_init_f();

	/* setup GP timer */
	timer_init();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* DDR initialization */
	spl_dram_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}
#endif
Commit	Line	Data
871ec6da JT	1	/*
	2	* Copyright (C) 2016 Amarula Solutions B.V.
	3	* Copyright (C) 2016 Engicam S.r.l.
	4	* Author: Jagan Teki <jagan@amarulasolutions.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <common.h>
	10
	11	#include <asm/io.h>
	12	#include <asm/gpio.h>
	13	#include <linux/sizes.h>
	14
	15	#include <asm/arch/clock.h>
	16	#include <asm/arch/crm_regs.h>
	17	#include <asm/arch/iomux.h>
	18	#include <asm/arch/mx6-pins.h>
	19	#include <asm/arch/sys_proto.h>
	20	#include <asm/imx-common/iomux-v3.h>
	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
	24	#define UART_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	25	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	26	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	27
	28	static iomux_v3_cfg_t const uart4_pads[] = {
	29	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
	30	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
	31	};
	32
	33	int board_early_init_f(void)
	34	{
	35	SETUP_IOMUX_PADS(uart4_pads);
	36
	37	return 0;
	38	}
	39
	40	int board_init(void)
	41	{
	42	/* Address of boot parameters */
	43	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	44
	45	return 0;
	46	}
	47
	48	int dram_init(void)
	49	{
	50	gd->ram_size = imx_ddr_size();
	51
	52	return 0;
	53	}
	54
	55	#ifdef CONFIG_SPL_BUILD
	56	#include <libfdt.h>
	57	#include <spl.h>
	58
	59	#include <asm/arch/crm_regs.h>
	60	#include <asm/arch/mx6-ddr.h>
	61
	62	/* MMC board initialization is needed till adding DM support in SPL */
	63	#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
	64	#include <mmc.h>
65	#include <fsl_esdhc.h>
66
67	#define USDHC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
68	PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_HIGH \| \
69	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
70
71	static iomux_v3_cfg_t const usdhc3_pads[] = {
72	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
73	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
74	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
75	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
76	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
78	};
79
ffa11c33 JT	80	static iomux_v3_cfg_t const usdhc4_pads[] = {
	81	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	82	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	83	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	84	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	85	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	86	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	87	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	88	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	89	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	90	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	91	};
	92
	93	struct fsl_esdhc_cfg usdhc_cfg[2] = {
871ec6da	94	{USDHC3_BASE_ADDR, 1, 4},
ffa11c33	95	{USDHC4_BASE_ADDR, 1, 8},
871ec6da JT	96	};
	97
	98	int board_mmc_getcd(struct mmc *mmc)
	99	{
	100	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	101	int ret = 0;
	102
	103	switch (cfg->esdhc_base) {
	104	case USDHC3_BASE_ADDR:
ffa11c33	105	case USDHC4_BASE_ADDR:
871ec6da JT	106	ret = 1;
	107	break;
	108	}
	109
	110	return ret;
	111	}
	112
	113	int board_mmc_init(bd_t *bis)
	114	{
	115	int i, ret;
	116
	117	/*
	118	* According to the board_mmc_init() the following map is done:
	119	* (U-boot device node) (Physical Port)
ffa11c33 JT	120	* mmc0 USDHC3
ffa11c33 JT	121	* mmc1 USDHC4
871ec6da JT	122	*/
	123	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
	124	switch (i) {
	125	case 0:
	126	SETUP_IOMUX_PADS(usdhc3_pads);
	127	usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	128	break;
ffa11c33 JT	129	case 1:
	130	SETUP_IOMUX_PADS(usdhc4_pads);
	131	usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
	132	break;
871ec6da JT	133	default:
	134	printf("Warning - USDHC%d controller not supporting\n",
	135	i + 1);
	136	return 0;
	137	}
	138
	139	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
	140	if (ret) {
	141	printf("Warning: failed to initialize mmc dev %d\n", i);
	142	return ret;
	143	}
	144	}
	145
	146	return 0;
	147	}
10fa3ee0 JT	148
	149	#ifdef CONFIG_ENV_IS_IN_MMC
	150	void board_boot_order(u32 *spl_boot_list)
	151	{
	152	u32 bmode = imx6_src_get_boot_mode();
	153	u8 boot_dev = BOOT_DEVICE_MMC1;
	154
	155	switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
	156	case IMX6_BMODE_SD:
	157	case IMX6_BMODE_ESD:
	158	/* SD/eSD - BOOT_DEVICE_MMC1 */
	159	break;
	160	case IMX6_BMODE_MMC:
	161	case IMX6_BMODE_EMMC:
	162	/* MMC/eMMC */
	163	boot_dev = BOOT_DEVICE_MMC2;
	164	break;
	165	default:
	166	/* Default - BOOT_DEVICE_MMC1 */
	167	printf("Wrong board boot order\n");
	168	break;
	169	}
	170
	171	spl_boot_list[0] = boot_dev;
	172	}
	173	#endif
871ec6da JT	174	#endif
	175
	176	/*
	177	* Driving strength:
	178	* 0x30 == 40 Ohm
	179	* 0x28 == 48 Ohm
	180	*/
	181
	182	#define IMX6DQ_DRIVE_STRENGTH 0x30
	183	#define IMX6SDL_DRIVE_STRENGTH 0x28
	184
	185	/* configure MX6Q/DUAL mmdc DDR io registers */
	186	static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	187	.dram_sdqs0 = 0x28,
	188	.dram_sdqs1 = 0x28,
	189	.dram_sdqs2 = 0x28,
	190	.dram_sdqs3 = 0x28,
	191	.dram_sdqs4 = 0x28,
	192	.dram_sdqs5 = 0x28,
	193	.dram_sdqs6 = 0x28,
	194	.dram_sdqs7 = 0x28,
	195	.dram_dqm0 = 0x28,
	196	.dram_dqm1 = 0x28,
	197	.dram_dqm2 = 0x28,
	198	.dram_dqm3 = 0x28,
	199	.dram_dqm4 = 0x28,
	200	.dram_dqm5 = 0x28,
	201	.dram_dqm6 = 0x28,
	202	.dram_dqm7 = 0x28,
	203	.dram_cas = 0x30,
	204	.dram_ras = 0x30,
	205	.dram_sdclk_0 = 0x30,
	206	.dram_sdclk_1 = 0x30,
	207	.dram_reset = 0x30,
	208	.dram_sdcke0 = 0x3000,
	209	.dram_sdcke1 = 0x3000,
	210	.dram_sdba2 = 0x00000000,
	211	.dram_sdodt0 = 0x30,
	212	.dram_sdodt1 = 0x30,
	213	};
	214
	215	/* configure MX6Q/DUAL mmdc GRP io registers */
	216	static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	217	.grp_b0ds = 0x30,
	218	.grp_b1ds = 0x30,
	219	.grp_b2ds = 0x30,
	220	.grp_b3ds = 0x30,
	221	.grp_b4ds = 0x30,
	222	.grp_b5ds = 0x30,
	223	.grp_b6ds = 0x30,
	224	.grp_b7ds = 0x30,
	225	.grp_addds = 0x30,
	226	.grp_ddrmode_ctl = 0x00020000,
	227	.grp_ddrpke = 0x00000000,
	228	.grp_ddrmode = 0x00020000,
	229	.grp_ctlds = 0x30,
	230	.grp_ddr_type = 0x000c0000,
	231	};
	232
	233	/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
	234	struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	235	.dram_sdclk_0 = 0x30,
	236	.dram_sdclk_1 = 0x30,
	237	.dram_cas = 0x30,
238	.dram_ras = 0x30,
239	.dram_reset = 0x30,
240	.dram_sdcke0 = 0x30,
241	.dram_sdcke1 = 0x30,
242	.dram_sdba2 = 0x00000000,
243	.dram_sdodt0 = 0x30,
244	.dram_sdodt1 = 0x30,
245	.dram_sdqs0 = 0x28,
246	.dram_sdqs1 = 0x28,
247	.dram_sdqs2 = 0x28,
248	.dram_sdqs3 = 0x28,
249	.dram_sdqs4 = 0x28,
250	.dram_sdqs5 = 0x28,
251	.dram_sdqs6 = 0x28,
252	.dram_sdqs7 = 0x28,
253	.dram_dqm0 = 0x28,
254	.dram_dqm1 = 0x28,
255	.dram_dqm2 = 0x28,
256	.dram_dqm3 = 0x28,
257	.dram_dqm4 = 0x28,
258	.dram_dqm5 = 0x28,
259	.dram_dqm6 = 0x28,
260	.dram_dqm7 = 0x28,
261	};
262
263	/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
264	struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
265	.grp_ddr_type = 0x000c0000,
266	.grp_ddrmode_ctl = 0x00020000,
267	.grp_ddrpke = 0x00000000,
268	.grp_addds = 0x30,
269	.grp_ctlds = 0x30,
270	.grp_ddrmode = 0x00020000,
271	.grp_b0ds = 0x28,
272	.grp_b1ds = 0x28,
273	.grp_b2ds = 0x28,
274	.grp_b3ds = 0x28,
275	.grp_b4ds = 0x28,
276	.grp_b5ds = 0x28,
277	.grp_b6ds = 0x28,
278	.grp_b7ds = 0x28,
279	};
280
281	/* mt41j256 */
282	static struct mx6_ddr3_cfg mt41j256 = {
283	.mem_speed = 1066,
284	.density = 2,
285	.width = 16,
286	.banks = 8,
287	.rowaddr = 13,
288	.coladdr = 10,
289	.pagesz = 2,
290	.trcd = 1375,
291	.trcmin = 4875,
292	.trasmin = 3500,
293	.SRT = 0,
294	};
295
296	static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
297	.p0_mpwldectrl0 = 0x000E0009,
298	.p0_mpwldectrl1 = 0x0018000E,
299	.p1_mpwldectrl0 = 0x00000007,
300	.p1_mpwldectrl1 = 0x00000000,
301	.p0_mpdgctrl0 = 0x43280334,
302	.p0_mpdgctrl1 = 0x031C0314,
303	.p1_mpdgctrl0 = 0x4318031C,
304	.p1_mpdgctrl1 = 0x030C0258,
305	.p0_mprddlctl = 0x3E343A40,
306	.p1_mprddlctl = 0x383C3844,
307	.p0_mpwrdlctl = 0x40404440,
308	.p1_mpwrdlctl = 0x4C3E4446,
309	};
310
311	/* DDR 64bit */
312	static struct mx6_ddr_sysinfo mem_q = {
313	.ddr_type = DDR_TYPE_DDR3,
314	.dsize = 2,
315	.cs1_mirror = 0,
316	/* config for full 4GB range so that get_mem_size() works */
317	.cs_density = 32,
318	.ncs = 1,
319	.bi_on = 1,
320	.rtt_nom = 2,
321	.rtt_wr = 2,
322	.ralat = 5,
323	.walat = 0,
324	.mif3_mode = 3,
325	.rst_to_cke = 0x23,
326	.sde_to_rst = 0x10,
327	};
328
329	static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
330	.p0_mpwldectrl0 = 0x001F0024,
331	.p0_mpwldectrl1 = 0x00110018,
332	.p1_mpwldectrl0 = 0x001F0024,
333	.p1_mpwldectrl1 = 0x00110018,
334	.p0_mpdgctrl0 = 0x4230022C,
335	.p0_mpdgctrl1 = 0x02180220,
336	.p1_mpdgctrl0 = 0x42440248,
337	.p1_mpdgctrl1 = 0x02300238,
338	.p0_mprddlctl = 0x44444A48,
339	.p1_mprddlctl = 0x46484A42,
340	.p0_mpwrdlctl = 0x38383234,
341	.p1_mpwrdlctl = 0x3C34362E,
342	};
343
344	/* DDR 64bit 1GB */
345	static struct mx6_ddr_sysinfo mem_dl = {
346	.dsize = 2,
347	.cs1_mirror = 0,
348	/* config for full 4GB range so that get_mem_size() works */
349	.cs_density = 32,
350	.ncs = 1,
351	.bi_on = 1,
352	.rtt_nom = 1,
353	.rtt_wr = 1,
354	.ralat = 5,
355	.walat = 0,
356	.mif3_mode = 3,
357	.rst_to_cke = 0x23,
358	.sde_to_rst = 0x10,
359	};
360
361	/* DDR 32bit 512MB */
362	static struct mx6_ddr_sysinfo mem_s = {
363	.dsize = 1,
364	.cs1_mirror = 0,
365	/* config for full 4GB range so that get_mem_size() works */
366	.cs_density = 32,
367	.ncs = 1,
368	.bi_on = 1,
369	.rtt_nom = 1,
370	.rtt_wr = 1,
371	.ralat = 5,
372	.walat = 0,
373	.mif3_mode = 3,
374	.rst_to_cke = 0x23,
375	.sde_to_rst = 0x10,
376	};
377
378	static void ccgr_init(void)
379	{
380	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
381
382	writel(0x00003F3F, &ccm->CCGR0);
383	writel(0x0030FC00, &ccm->CCGR1);
384	writel(0x000FC000, &ccm->CCGR2);
385	writel(0x3F300000, &ccm->CCGR3);
386	writel(0xFF00F300, &ccm->CCGR4);
387	writel(0x0F0000C3, &ccm->CCGR5);
388	writel(0x000003CC, &ccm->CCGR6);
389	}
390
391	static void gpr_init(void)
392	{
393	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
394
395	/* enable AXI cache for VDOA/VPU/IPU */
396	writel(0xF00000CF, &iomux->gpr[4]);
397	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
398	writel(0x007F007F, &iomux->gpr[6]);
399	writel(0x007F007F, &iomux->gpr[7]);
400	}
401
402	static void spl_dram_init(void)
403	{
404	if (is_mx6solo()) {
405	mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
406	mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
407	} else if (is_mx6dl()) {
408	mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
409	mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
410	} else if (is_mx6dq()) {
411	mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
412	mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
413	}
414
415	udelay(100);
416	}
417
418	void board_init_f(ulong dummy)
419	{
420	ccgr_init();
421
422	/* setup AIPS and disable watchdog */
423	arch_cpu_init();
424
425	gpr_init();
426
427	/* iomux */
428	board_early_init_f();
429
430	/* setup GP timer */
431	timer_init();
432
433	/* UART clocks enabled and gd valid - init serial console */
434	preloader_console_init();
435
436	/* DDR initialization */
437	spl_dram_init();
438
439	/* Clear the BSS. */
440	memset(__bss_start, 0, __bss_end - __bss_start);
441
442	/* load/boot image from boot device */
443	board_init_r(NULL, 0);
444	}
445	#endif