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isiot: Fix to use usdhc2_pads for mmc2
[people/ms/u-boot.git] / board / engicam / isiotmx6ul / isiotmx6ul.c
CommitLineData
e9dfa1e1
JT		 1/*
2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
0dd259a1 10#include <mmc.h>
e9dfa1e1
JT		 11
12#include <asm/io.h>
13#include <asm/gpio.h>
14#include <linux/sizes.h>
15
16#include <asm/arch/clock.h>
17#include <asm/arch/crm_regs.h>
18#include <asm/arch/iomux.h>
19#include <asm/arch/mx6-pins.h>
20#include <asm/arch/sys_proto.h>
21#include <asm/imx-common/iomux-v3.h>
22
23DECLARE_GLOBAL_DATA_PTR;
24
6788a7e4
JT		 25#ifdef CONFIG_NAND_MXS
26
27#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
28#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
29 PAD_CTL_SRE_FAST)
30#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
31
32static iomux_v3_cfg_t const nand_pads[] = {
33 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
34 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
35 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
36 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
37 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
38 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
39 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
40 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
41 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
42 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
43 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
44 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
45 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
46 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
47 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
48};
49
50static void setup_gpmi_nand(void)
51{
52 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
53
54 /* config gpmi nand iomux */
55 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
56
57 clrbits_le32(&mxc_ccm->CCGR4,
58 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
59 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
60 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
61 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
62 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
63
64 /*
65 * config gpmi and bch clock to 100 MHz
66 * bch/gpmi select PLL2 PFD2 400M
67 * 100M = 400M / 4
68 */
69 clrbits_le32(&mxc_ccm->cscmr1,
70 MXC_CCM_CSCMR1_BCH_CLK_SEL |
71 MXC_CCM_CSCMR1_GPMI_CLK_SEL);
72 clrsetbits_le32(&mxc_ccm->cscdr1,
73 MXC_CCM_CSCDR1_BCH_PODF_MASK |
74 MXC_CCM_CSCDR1_GPMI_PODF_MASK,
75 (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
76 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
77
78 /* enable gpmi and bch clock gating */
79 setbits_le32(&mxc_ccm->CCGR4,
80 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
81 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
82 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
83 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
84 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
85
86 /* enable apbh clock gating */
87 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
88}
89#endif /* CONFIG_NAND_MXS */
90
0dd259a1 91#ifdef CONFIG_ENV_IS_IN_MMC
e9685967
JT		 92int board_mmc_get_env_dev(int devno)
93{
94 /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
95 return (devno == 0) ? 0 : 1;
96}
97
0dd259a1
JT		 98static void mmc_late_init(void)
99{
100 char cmd[32];
101 char mmcblk[32];
102 u32 dev_no = mmc_get_env_dev();
103
104 setenv_ulong("mmcdev", dev_no);
105
106 /* Set mmcblk env */
107 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
108 setenv("mmcroot", mmcblk);
109
110 sprintf(cmd, "mmc dev %d", dev_no);
111 run_command(cmd, 0);
112}
113#endif
114
2e2a8dc6
JT		 115int board_late_init(void)
116{
117 switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
118 IMX6_BMODE_SHIFT) {
119 case IMX6_BMODE_SD:
120 case IMX6_BMODE_ESD:
121 case IMX6_BMODE_MMC:
122 case IMX6_BMODE_EMMC:
0dd259a1
JT		 123#ifdef CONFIG_ENV_IS_IN_MMC
124 mmc_late_init();
125#endif
2e2a8dc6
JT		 126 setenv("modeboot", "mmcboot");
127 break;
128 case IMX6_BMODE_NAND:
129 setenv("modeboot", "nandboot");
130 break;
131 default:
132 setenv("modeboot", "");
133 break;
134 }
135
6f1f3f59
JT		 136 if (is_mx6ul()) {
137#ifdef CONFIG_ENV_IS_IN_MMC
138 setenv("fdt_file", "imx6ul-isiot-emmc.dtb");
139#else
140 setenv("fdt_file", "imx6ul-isiot-nand.dtb");
141#endif
142 }
143
2e2a8dc6
JT		 144 return 0;
145}
146
e9dfa1e1
JT		 147int board_init(void)
148{
149 /* Address of boot parameters */
150 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
151
6788a7e4
JT		 152#ifdef CONFIG_NAND_MXS
153 setup_gpmi_nand();
154#endif
e9dfa1e1
JT		 155 return 0;
156}
157
158int dram_init(void)
159{
160 gd->ram_size = imx_ddr_size();
161
162 return 0;
163}
164
165#ifdef CONFIG_SPL_BUILD
166#include <libfdt.h>
167#include <spl.h>
168
169#include <asm/arch/crm_regs.h>
170#include <asm/arch/mx6-ddr.h>
171
b805b174
JT		 172#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
173 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
174 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
175
176static iomux_v3_cfg_t const uart1_pads[] = {
177 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
178 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
179};
180
e9dfa1e1
JT		 181/* MMC board initialization is needed till adding DM support in SPL */
182#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
183#include <mmc.h>
184#include <fsl_esdhc.h>
185
186#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
187 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
188 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
189
190static iomux_v3_cfg_t const usdhc1_pads[] = {
191 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
192 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
193 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
194 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
195 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
196 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
197
198 /* VSELECT */
199 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
200 /* CD */
201 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
202 /* RST_B */
203 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
204};
205
7cf22dc8
JT		 206static iomux_v3_cfg_t const usdhc2_pads[] = {
207 MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
208 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
209 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
210 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
211 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
212 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
213 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
214 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
215 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
216};
217
e9dfa1e1 218#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
7cf22dc8 219#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
e9dfa1e1 220
7cf22dc8 221struct fsl_esdhc_cfg usdhc_cfg[2] = {
e9dfa1e1 222 {USDHC1_BASE_ADDR, 0, 4},
7cf22dc8 223 {USDHC2_BASE_ADDR, 0, 8},
e9dfa1e1
JT		 224};
225
226int board_mmc_getcd(struct mmc *mmc)
227{
228 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
229 int ret = 0;
230
231 switch (cfg->esdhc_base) {
232 case USDHC1_BASE_ADDR:
233 ret = !gpio_get_value(USDHC1_CD_GPIO);
234 break;
7cf22dc8
JT		 235 case USDHC2_BASE_ADDR:
236 ret = !gpio_get_value(USDHC2_CD_GPIO);
237 break;
e9dfa1e1
JT		 238 }
239
240 return ret;
241}
242
243int board_mmc_init(bd_t *bis)
244{
245 int i, ret;
246
247 /*
248 * According to the board_mmc_init() the following map is done:
249 * (U-boot device node) (Physical Port)
250 * mmc0 USDHC1
7cf22dc8 251 * mmc1 USDHC2
e9dfa1e1
JT		 252 */
253 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
254 switch (i) {
255 case 0:
256 imx_iomux_v3_setup_multiple_pads(
257 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
258 gpio_direction_input(USDHC1_CD_GPIO);
259 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
260 break;
7cf22dc8
JT		 261 case 1:
262 imx_iomux_v3_setup_multiple_pads(
5f31ed49 263 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
7cf22dc8
JT		 264 gpio_direction_input(USDHC2_CD_GPIO);
265 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
266 break;
e9dfa1e1
JT		 267 default:
268 printf("Warning - USDHC%d controller not supporting\n",
269 i + 1);
270 return 0;
271 }
272
273 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
274 if (ret) {
275 printf("Warning: failed to initialize mmc dev %d\n", i);
276 return ret;
277 }
278 }
279
280 return 0;
281}
cde5aa37
JT		 282
283#ifdef CONFIG_ENV_IS_IN_MMC
284void board_boot_order(u32 *spl_boot_list)
285{
286 u32 bmode = imx6_src_get_boot_mode();
287 u8 boot_dev = BOOT_DEVICE_MMC1;
288
289 switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
290 case IMX6_BMODE_SD:
291 case IMX6_BMODE_ESD:
292 /* SD/eSD - BOOT_DEVICE_MMC1 */
293 break;
294 case IMX6_BMODE_MMC:
295 case IMX6_BMODE_EMMC:
296 /* MMC/eMMC */
297 boot_dev = BOOT_DEVICE_MMC2;
298 break;
299 default:
300 /* Default - BOOT_DEVICE_MMC1 */
301 printf("Wrong board boot order\n");
302 break;
303 }
304
305 spl_boot_list[0] = boot_dev;
306}
307#endif
e9dfa1e1
JT		 308#endif /* CONFIG_FSL_ESDHC */
309
310static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
311 .grp_addds = 0x00000030,
312 .grp_ddrmode_ctl = 0x00020000,
313 .grp_b0ds = 0x00000030,
314 .grp_ctlds = 0x00000030,
315 .grp_b1ds = 0x00000030,
316 .grp_ddrpke = 0x00000000,
317 .grp_ddrmode = 0x00020000,
318 .grp_ddr_type = 0x000c0000,
319};
320
321static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
322 .dram_dqm0 = 0x00000030,
323 .dram_dqm1 = 0x00000030,
324 .dram_ras = 0x00000030,
325 .dram_cas = 0x00000030,
326 .dram_odt0 = 0x00000030,
327 .dram_odt1 = 0x00000030,
328 .dram_sdba2 = 0x00000000,
329 .dram_sdclk_0 = 0x00000008,
330 .dram_sdqs0 = 0x00000038,
331 .dram_sdqs1 = 0x00000030,
332 .dram_reset = 0x00000030,
333};
334
335static struct mx6_mmdc_calibration mx6_mmcd_calib = {
336 .p0_mpwldectrl0 = 0x00070007,
337 .p0_mpdgctrl0 = 0x41490145,
338 .p0_mprddlctl = 0x40404546,
339 .p0_mpwrdlctl = 0x4040524D,
340};
341
342struct mx6_ddr_sysinfo ddr_sysinfo = {
343 .dsize = 0,
344 .cs_density = 20,
345 .ncs = 1,
346 .cs1_mirror = 0,
347 .rtt_wr = 2,
348 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
349 .walat = 1, /* Write additional latency */
350 .ralat = 5, /* Read additional latency */
351 .mif3_mode = 3, /* Command prediction working mode */
352 .bi_on = 1, /* Bank interleaving enabled */
353 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
354 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
355 .ddr_type = DDR_TYPE_DDR3,
356};
357
358static struct mx6_ddr3_cfg mem_ddr = {
359 .mem_speed = 800,
360 .density = 4,
361 .width = 16,
362 .banks = 8,
363 .rowaddr = 15,
364 .coladdr = 10,
365 .pagesz = 2,
366 .trcd = 1375,
367 .trcmin = 4875,
368 .trasmin = 3500,
369};
370
371static void ccgr_init(void)
372{
373 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
374
375 writel(0x00c03f3f, &ccm->CCGR0);
376 writel(0xfcffff00, &ccm->CCGR1);
377 writel(0x0cffffcc, &ccm->CCGR2);
378 writel(0x3f3c3030, &ccm->CCGR3);
379 writel(0xff00fffc, &ccm->CCGR4);
380 writel(0x033f30ff, &ccm->CCGR5);
381 writel(0x00c00fff, &ccm->CCGR6);
382}
383
384static void spl_dram_init(void)
385{
386 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
387 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
388}
389
390void board_init_f(ulong dummy)
391{
392 /* setup AIPS and disable watchdog */
393 arch_cpu_init();
394
395 ccgr_init();
396
397 /* iomux and setup of i2c */
b805b174 398 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
e9dfa1e1
JT		 399
400 /* setup GP timer */
401 timer_init();
402
403 /* UART clocks enabled and gd valid - init serial console */
404 preloader_console_init();
405
406 /* DDR initialization */
407 spl_dram_init();
408
409 /* Clear the BSS. */
410 memset(__bss_start, 0, __bss_end - __bss_start);
411
412 /* load/boot image from boot device */
413 board_init_r(NULL, 0);
414}
415#endif /* CONFIG_SPL_BUILD */
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