]> git.ipfire.org Git - people/ms/u-boot.git/blame - board/engicam/isiotmx6ul/isiotmx6ul.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
engicam: Set fdt_file env during run-time
[people/ms/u-boot.git] / board / engicam / isiotmx6ul / isiotmx6ul.c
CommitLineData
e9dfa1e1
JT		 1/*
2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
0dd259a1 10#include <mmc.h>
e9dfa1e1
JT		 11
12#include <asm/io.h>
13#include <asm/gpio.h>
14#include <linux/sizes.h>
15
16#include <asm/arch/clock.h>
17#include <asm/arch/crm_regs.h>
18#include <asm/arch/iomux.h>
19#include <asm/arch/mx6-pins.h>
20#include <asm/arch/sys_proto.h>
21#include <asm/imx-common/iomux-v3.h>
22
23DECLARE_GLOBAL_DATA_PTR;
24
25#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
26 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
27 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
28
29static iomux_v3_cfg_t const uart1_pads[] = {
30 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
31 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
32};
33
34int board_early_init_f(void)
35{
36 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
37
38 return 0;
39}
40
6788a7e4
JT		 41#ifdef CONFIG_NAND_MXS
42
43#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
44#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
45 PAD_CTL_SRE_FAST)
46#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
47
48static iomux_v3_cfg_t const nand_pads[] = {
49 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
50 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
51 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
52 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
53 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
54 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
55 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
56 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
57 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
58 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
59 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
60 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
61 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
62 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
63 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
64};
65
66static void setup_gpmi_nand(void)
67{
68 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
69
70 /* config gpmi nand iomux */
71 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
72
73 clrbits_le32(&mxc_ccm->CCGR4,
74 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
75 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
76 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
77 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
78 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
79
80 /*
81 * config gpmi and bch clock to 100 MHz
82 * bch/gpmi select PLL2 PFD2 400M
83 * 100M = 400M / 4
84 */
85 clrbits_le32(&mxc_ccm->cscmr1,
86 MXC_CCM_CSCMR1_BCH_CLK_SEL |
87 MXC_CCM_CSCMR1_GPMI_CLK_SEL);
88 clrsetbits_le32(&mxc_ccm->cscdr1,
89 MXC_CCM_CSCDR1_BCH_PODF_MASK |
90 MXC_CCM_CSCDR1_GPMI_PODF_MASK,
91 (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
92 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
93
94 /* enable gpmi and bch clock gating */
95 setbits_le32(&mxc_ccm->CCGR4,
96 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
97 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
98 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
99 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
100 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
101
102 /* enable apbh clock gating */
103 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
104}
105#endif /* CONFIG_NAND_MXS */
106
0dd259a1 107#ifdef CONFIG_ENV_IS_IN_MMC
e9685967
JT		 108int board_mmc_get_env_dev(int devno)
109{
110 /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
111 return (devno == 0) ? 0 : 1;
112}
113
0dd259a1
JT		 114static void mmc_late_init(void)
115{
116 char cmd[32];
117 char mmcblk[32];
118 u32 dev_no = mmc_get_env_dev();
119
120 setenv_ulong("mmcdev", dev_no);
121
122 /* Set mmcblk env */
123 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
124 setenv("mmcroot", mmcblk);
125
126 sprintf(cmd, "mmc dev %d", dev_no);
127 run_command(cmd, 0);
128}
129#endif
130
2e2a8dc6
JT		 131int board_late_init(void)
132{
133 switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
134 IMX6_BMODE_SHIFT) {
135 case IMX6_BMODE_SD:
136 case IMX6_BMODE_ESD:
137 case IMX6_BMODE_MMC:
138 case IMX6_BMODE_EMMC:
0dd259a1
JT		 139#ifdef CONFIG_ENV_IS_IN_MMC
140 mmc_late_init();
141#endif
2e2a8dc6
JT		 142 setenv("modeboot", "mmcboot");
143 break;
144 case IMX6_BMODE_NAND:
145 setenv("modeboot", "nandboot");
146 break;
147 default:
148 setenv("modeboot", "");
149 break;
150 }
151
6f1f3f59
JT		 152 if (is_mx6ul()) {
153#ifdef CONFIG_ENV_IS_IN_MMC
154 setenv("fdt_file", "imx6ul-isiot-emmc.dtb");
155#else
156 setenv("fdt_file", "imx6ul-isiot-nand.dtb");
157#endif
158 }
159
2e2a8dc6
JT		 160 return 0;
161}
162
e9dfa1e1
JT		 163int board_init(void)
164{
165 /* Address of boot parameters */
166 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
167
6788a7e4
JT		 168#ifdef CONFIG_NAND_MXS
169 setup_gpmi_nand();
170#endif
e9dfa1e1
JT		 171 return 0;
172}
173
174int dram_init(void)
175{
176 gd->ram_size = imx_ddr_size();
177
178 return 0;
179}
180
181#ifdef CONFIG_SPL_BUILD
182#include <libfdt.h>
183#include <spl.h>
184
185#include <asm/arch/crm_regs.h>
186#include <asm/arch/mx6-ddr.h>
187
188/* MMC board initialization is needed till adding DM support in SPL */
189#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
190#include <mmc.h>
191#include <fsl_esdhc.h>
192
193#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
194 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
195 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
196
197static iomux_v3_cfg_t const usdhc1_pads[] = {
198 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
199 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
200 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
201 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
202 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
203 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
204
205 /* VSELECT */
206 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
207 /* CD */
208 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
209 /* RST_B */
210 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
211};
212
7cf22dc8
JT		 213static iomux_v3_cfg_t const usdhc2_pads[] = {
214 MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
215 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
216 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
217 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
218 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
219 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
220 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
221 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
222 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
223};
224
e9dfa1e1 225#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
7cf22dc8 226#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
e9dfa1e1 227
7cf22dc8 228struct fsl_esdhc_cfg usdhc_cfg[2] = {
e9dfa1e1 229 {USDHC1_BASE_ADDR, 0, 4},
7cf22dc8 230 {USDHC2_BASE_ADDR, 0, 8},
e9dfa1e1
JT		 231};
232
233int board_mmc_getcd(struct mmc *mmc)
234{
235 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
236 int ret = 0;
237
238 switch (cfg->esdhc_base) {
239 case USDHC1_BASE_ADDR:
240 ret = !gpio_get_value(USDHC1_CD_GPIO);
241 break;
7cf22dc8
JT		 242 case USDHC2_BASE_ADDR:
243 ret = !gpio_get_value(USDHC2_CD_GPIO);
244 break;
e9dfa1e1
JT		 245 }
246
247 return ret;
248}
249
250int board_mmc_init(bd_t *bis)
251{
252 int i, ret;
253
254 /*
255 * According to the board_mmc_init() the following map is done:
256 * (U-boot device node) (Physical Port)
257 * mmc0 USDHC1
7cf22dc8 258 * mmc1 USDHC2
e9dfa1e1
JT		 259 */
260 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
261 switch (i) {
262 case 0:
263 imx_iomux_v3_setup_multiple_pads(
264 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
265 gpio_direction_input(USDHC1_CD_GPIO);
266 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
267 break;
7cf22dc8
JT		 268 case 1:
269 imx_iomux_v3_setup_multiple_pads(
270 usdhc1_pads, ARRAY_SIZE(usdhc2_pads));
271 gpio_direction_input(USDHC2_CD_GPIO);
272 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
273 break;
e9dfa1e1
JT		 274 default:
275 printf("Warning - USDHC%d controller not supporting\n",
276 i + 1);
277 return 0;
278 }
279
280 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
281 if (ret) {
282 printf("Warning: failed to initialize mmc dev %d\n", i);
283 return ret;
284 }
285 }
286
287 return 0;
288}
cde5aa37
JT		 289
290#ifdef CONFIG_ENV_IS_IN_MMC
291void board_boot_order(u32 *spl_boot_list)
292{
293 u32 bmode = imx6_src_get_boot_mode();
294 u8 boot_dev = BOOT_DEVICE_MMC1;
295
296 switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
297 case IMX6_BMODE_SD:
298 case IMX6_BMODE_ESD:
299 /* SD/eSD - BOOT_DEVICE_MMC1 */
300 break;
301 case IMX6_BMODE_MMC:
302 case IMX6_BMODE_EMMC:
303 /* MMC/eMMC */
304 boot_dev = BOOT_DEVICE_MMC2;
305 break;
306 default:
307 /* Default - BOOT_DEVICE_MMC1 */
308 printf("Wrong board boot order\n");
309 break;
310 }
311
312 spl_boot_list[0] = boot_dev;
313}
314#endif
e9dfa1e1
JT		 315#endif /* CONFIG_FSL_ESDHC */
316
317static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
318 .grp_addds = 0x00000030,
319 .grp_ddrmode_ctl = 0x00020000,
320 .grp_b0ds = 0x00000030,
321 .grp_ctlds = 0x00000030,
322 .grp_b1ds = 0x00000030,
323 .grp_ddrpke = 0x00000000,
324 .grp_ddrmode = 0x00020000,
325 .grp_ddr_type = 0x000c0000,
326};
327
328static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
329 .dram_dqm0 = 0x00000030,
330 .dram_dqm1 = 0x00000030,
331 .dram_ras = 0x00000030,
332 .dram_cas = 0x00000030,
333 .dram_odt0 = 0x00000030,
334 .dram_odt1 = 0x00000030,
335 .dram_sdba2 = 0x00000000,
336 .dram_sdclk_0 = 0x00000008,
337 .dram_sdqs0 = 0x00000038,
338 .dram_sdqs1 = 0x00000030,
339 .dram_reset = 0x00000030,
340};
341
342static struct mx6_mmdc_calibration mx6_mmcd_calib = {
343 .p0_mpwldectrl0 = 0x00070007,
344 .p0_mpdgctrl0 = 0x41490145,
345 .p0_mprddlctl = 0x40404546,
346 .p0_mpwrdlctl = 0x4040524D,
347};
348
349struct mx6_ddr_sysinfo ddr_sysinfo = {
350 .dsize = 0,
351 .cs_density = 20,
352 .ncs = 1,
353 .cs1_mirror = 0,
354 .rtt_wr = 2,
355 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
356 .walat = 1, /* Write additional latency */
357 .ralat = 5, /* Read additional latency */
358 .mif3_mode = 3, /* Command prediction working mode */
359 .bi_on = 1, /* Bank interleaving enabled */
360 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
361 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
362 .ddr_type = DDR_TYPE_DDR3,
363};
364
365static struct mx6_ddr3_cfg mem_ddr = {
366 .mem_speed = 800,
367 .density = 4,
368 .width = 16,
369 .banks = 8,
370 .rowaddr = 15,
371 .coladdr = 10,
372 .pagesz = 2,
373 .trcd = 1375,
374 .trcmin = 4875,
375 .trasmin = 3500,
376};
377
378static void ccgr_init(void)
379{
380 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
381
382 writel(0x00c03f3f, &ccm->CCGR0);
383 writel(0xfcffff00, &ccm->CCGR1);
384 writel(0x0cffffcc, &ccm->CCGR2);
385 writel(0x3f3c3030, &ccm->CCGR3);
386 writel(0xff00fffc, &ccm->CCGR4);
387 writel(0x033f30ff, &ccm->CCGR5);
388 writel(0x00c00fff, &ccm->CCGR6);
389}
390
391static void spl_dram_init(void)
392{
393 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
394 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
395}
396
397void board_init_f(ulong dummy)
398{
399 /* setup AIPS and disable watchdog */
400 arch_cpu_init();
401
402 ccgr_init();
403
404 /* iomux and setup of i2c */
405 board_early_init_f();
406
407 /* setup GP timer */
408 timer_init();
409
410 /* UART clocks enabled and gd valid - init serial console */
411 preloader_console_init();
412
413 /* DDR initialization */
414 spl_dram_init();
415
416 /* Clear the BSS. */
417 memset(__bss_start, 0, __bss_end - __bss_start);
418
419 /* load/boot image from boot device */
420 board_init_r(NULL, 0);
421}
422#endif /* CONFIG_SPL_BUILD */
"Das U-Boot" Source Tree