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e9dfa1e1 JT |
1 | /* |
2 | * Copyright (C) 2016 Amarula Solutions B.V. | |
3 | * Copyright (C) 2016 Engicam S.r.l. | |
4 | * Author: Jagan Teki <jagan@amarulasolutions.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
0dd259a1 | 10 | #include <mmc.h> |
e9dfa1e1 JT |
11 | |
12 | #include <asm/io.h> | |
13 | #include <asm/gpio.h> | |
14 | #include <linux/sizes.h> | |
15 | ||
16 | #include <asm/arch/clock.h> | |
17 | #include <asm/arch/crm_regs.h> | |
18 | #include <asm/arch/iomux.h> | |
19 | #include <asm/arch/mx6-pins.h> | |
20 | #include <asm/arch/sys_proto.h> | |
21 | #include <asm/imx-common/iomux-v3.h> | |
22 | ||
900c847e JT |
23 | #include "../common/board.h" |
24 | ||
e9dfa1e1 JT |
25 | DECLARE_GLOBAL_DATA_PTR; |
26 | ||
6788a7e4 JT |
27 | #ifdef CONFIG_NAND_MXS |
28 | ||
29 | #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) | |
30 | #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ | |
31 | PAD_CTL_SRE_FAST) | |
32 | #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) | |
33 | ||
34 | static iomux_v3_cfg_t const nand_pads[] = { | |
8c4629e0 JT |
35 | IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), |
36 | IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
37 | IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
38 | IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
39 | IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
40 | IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
41 | IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
42 | IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
43 | IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
44 | IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
45 | IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
46 | IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
47 | IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
48 | IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
49 | IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
6788a7e4 JT |
50 | }; |
51 | ||
900c847e | 52 | void setup_gpmi_nand(void) |
6788a7e4 JT |
53 | { |
54 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
55 | ||
56 | /* config gpmi nand iomux */ | |
8c4629e0 | 57 | SETUP_IOMUX_PADS(nand_pads); |
6788a7e4 JT |
58 | |
59 | clrbits_le32(&mxc_ccm->CCGR4, | |
60 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
61 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
62 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
63 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
64 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); | |
65 | ||
66 | /* | |
67 | * config gpmi and bch clock to 100 MHz | |
68 | * bch/gpmi select PLL2 PFD2 400M | |
69 | * 100M = 400M / 4 | |
70 | */ | |
71 | clrbits_le32(&mxc_ccm->cscmr1, | |
72 | MXC_CCM_CSCMR1_BCH_CLK_SEL | | |
73 | MXC_CCM_CSCMR1_GPMI_CLK_SEL); | |
74 | clrsetbits_le32(&mxc_ccm->cscdr1, | |
75 | MXC_CCM_CSCDR1_BCH_PODF_MASK | | |
76 | MXC_CCM_CSCDR1_GPMI_PODF_MASK, | |
77 | (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | | |
78 | (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); | |
79 | ||
80 | /* enable gpmi and bch clock gating */ | |
81 | setbits_le32(&mxc_ccm->CCGR4, | |
82 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
83 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
84 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
85 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
86 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); | |
87 | ||
88 | /* enable apbh clock gating */ | |
89 | setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); | |
90 | } | |
91 | #endif /* CONFIG_NAND_MXS */ | |
92 | ||
0dd259a1 | 93 | #ifdef CONFIG_ENV_IS_IN_MMC |
e9685967 JT |
94 | int board_mmc_get_env_dev(int devno) |
95 | { | |
96 | /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */ | |
97 | return (devno == 0) ? 0 : 1; | |
98 | } | |
0dd259a1 JT |
99 | #endif |
100 | ||
2e2a8dc6 JT |
101 | int board_late_init(void) |
102 | { | |
103 | switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> | |
104 | IMX6_BMODE_SHIFT) { | |
105 | case IMX6_BMODE_SD: | |
106 | case IMX6_BMODE_ESD: | |
107 | case IMX6_BMODE_MMC: | |
108 | case IMX6_BMODE_EMMC: | |
0dd259a1 JT |
109 | #ifdef CONFIG_ENV_IS_IN_MMC |
110 | mmc_late_init(); | |
111 | #endif | |
2e2a8dc6 JT |
112 | setenv("modeboot", "mmcboot"); |
113 | break; | |
114 | case IMX6_BMODE_NAND: | |
115 | setenv("modeboot", "nandboot"); | |
116 | break; | |
117 | default: | |
118 | setenv("modeboot", ""); | |
119 | break; | |
120 | } | |
121 | ||
77a8c918 JT |
122 | if (is_mx6ul()) { |
123 | #ifdef CONFIG_ENV_IS_IN_MMC | |
124 | setenv("fdt_file", "imx6ul-isiot-emmc.dtb"); | |
125 | #else | |
126 | setenv("fdt_file", "imx6ul-isiot-nand.dtb"); | |
127 | #endif | |
128 | } | |
129 | ||
2e2a8dc6 JT |
130 | return 0; |
131 | } | |
132 | ||
e9dfa1e1 | 133 | #ifdef CONFIG_SPL_BUILD |
e9dfa1e1 JT |
134 | #include <spl.h> |
135 | ||
e9dfa1e1 JT |
136 | /* MMC board initialization is needed till adding DM support in SPL */ |
137 | #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) | |
138 | #include <mmc.h> | |
139 | #include <fsl_esdhc.h> | |
140 | ||
141 | #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
142 | PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ | |
143 | PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
144 | ||
145 | static iomux_v3_cfg_t const usdhc1_pads[] = { | |
8c4629e0 JT |
146 | IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
147 | IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
148 | IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
149 | IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
150 | IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
151 | IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
e9dfa1e1 JT |
152 | |
153 | /* VSELECT */ | |
8c4629e0 | 154 | IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
e9dfa1e1 | 155 | /* CD */ |
8c4629e0 | 156 | IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
e9dfa1e1 | 157 | /* RST_B */ |
8c4629e0 | 158 | IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
e9dfa1e1 JT |
159 | }; |
160 | ||
7cf22dc8 | 161 | static iomux_v3_cfg_t const usdhc2_pads[] = { |
8c4629e0 JT |
162 | IOMUX_PADS(PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
163 | IOMUX_PADS(PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
164 | IOMUX_PADS(PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
165 | IOMUX_PADS(PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
166 | IOMUX_PADS(PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
167 | IOMUX_PADS(PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
168 | IOMUX_PADS(PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
169 | IOMUX_PADS(PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
170 | IOMUX_PADS(PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
7cf22dc8 JT |
171 | }; |
172 | ||
e9dfa1e1 | 173 | #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) |
7cf22dc8 | 174 | #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) |
e9dfa1e1 | 175 | |
7cf22dc8 | 176 | struct fsl_esdhc_cfg usdhc_cfg[2] = { |
e9dfa1e1 | 177 | {USDHC1_BASE_ADDR, 0, 4}, |
7cf22dc8 | 178 | {USDHC2_BASE_ADDR, 0, 8}, |
e9dfa1e1 JT |
179 | }; |
180 | ||
181 | int board_mmc_getcd(struct mmc *mmc) | |
182 | { | |
183 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | |
184 | int ret = 0; | |
185 | ||
186 | switch (cfg->esdhc_base) { | |
187 | case USDHC1_BASE_ADDR: | |
188 | ret = !gpio_get_value(USDHC1_CD_GPIO); | |
189 | break; | |
7cf22dc8 JT |
190 | case USDHC2_BASE_ADDR: |
191 | ret = !gpio_get_value(USDHC2_CD_GPIO); | |
192 | break; | |
e9dfa1e1 JT |
193 | } |
194 | ||
195 | return ret; | |
196 | } | |
197 | ||
198 | int board_mmc_init(bd_t *bis) | |
199 | { | |
200 | int i, ret; | |
201 | ||
202 | /* | |
203 | * According to the board_mmc_init() the following map is done: | |
204 | * (U-boot device node) (Physical Port) | |
205 | * mmc0 USDHC1 | |
7cf22dc8 | 206 | * mmc1 USDHC2 |
e9dfa1e1 JT |
207 | */ |
208 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { | |
209 | switch (i) { | |
210 | case 0: | |
8c4629e0 | 211 | SETUP_IOMUX_PADS(usdhc1_pads); |
e9dfa1e1 JT |
212 | gpio_direction_input(USDHC1_CD_GPIO); |
213 | usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); | |
214 | break; | |
7cf22dc8 | 215 | case 1: |
8c4629e0 | 216 | SETUP_IOMUX_PADS(usdhc2_pads); |
7cf22dc8 JT |
217 | gpio_direction_input(USDHC2_CD_GPIO); |
218 | usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); | |
219 | break; | |
e9dfa1e1 JT |
220 | default: |
221 | printf("Warning - USDHC%d controller not supporting\n", | |
222 | i + 1); | |
223 | return 0; | |
224 | } | |
225 | ||
226 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); | |
227 | if (ret) { | |
228 | printf("Warning: failed to initialize mmc dev %d\n", i); | |
229 | return ret; | |
230 | } | |
231 | } | |
232 | ||
233 | return 0; | |
234 | } | |
cde5aa37 JT |
235 | |
236 | #ifdef CONFIG_ENV_IS_IN_MMC | |
237 | void board_boot_order(u32 *spl_boot_list) | |
238 | { | |
239 | u32 bmode = imx6_src_get_boot_mode(); | |
240 | u8 boot_dev = BOOT_DEVICE_MMC1; | |
241 | ||
242 | switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { | |
243 | case IMX6_BMODE_SD: | |
244 | case IMX6_BMODE_ESD: | |
245 | /* SD/eSD - BOOT_DEVICE_MMC1 */ | |
246 | break; | |
247 | case IMX6_BMODE_MMC: | |
248 | case IMX6_BMODE_EMMC: | |
249 | /* MMC/eMMC */ | |
250 | boot_dev = BOOT_DEVICE_MMC2; | |
251 | break; | |
252 | default: | |
253 | /* Default - BOOT_DEVICE_MMC1 */ | |
254 | printf("Wrong board boot order\n"); | |
255 | break; | |
256 | } | |
257 | ||
258 | spl_boot_list[0] = boot_dev; | |
259 | } | |
260 | #endif | |
e9dfa1e1 | 261 | #endif /* CONFIG_FSL_ESDHC */ |
e9dfa1e1 | 262 | #endif /* CONFIG_SPL_BUILD */ |