[people/ms/u-boot.git] / board / esd / apc405 / apc405.c

/*
 * (C) Copyright 2005-2008
 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
 *
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
#include <flash.h>
#include <mtd/cfi_flash.h>
#include <asm/4xx_pci.h>
#include <pci.h>

DECLARE_GLOBAL_DATA_PTR;

#undef FPGA_DEBUG

extern void lxt971_no_sleep(void);

/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
{
#include "fpgadata.c"
};

/*
 * include common fpga code (for esd boards)
 */
#include "../common/fpga.c"

#ifdef CONFIG_LCD_USED
/* logo bitmap data - gzip compressed and generated by bin2c */
unsigned char logo_bmp[] =
{
#include "logo_640_480_24bpp.c"
};

/*
 * include common lcd code (for esd boards)
 */
#include "../common/lcd.c"
#include "../common/s1d13505_640_480_16bpp.h"
#include "../common/s1d13806_640_480_16bpp.h"
#endif /* CONFIG_LCD_USED */

/*
 * include common auto-update code (for esd boards)
 */
#include "../common/auto_update.h"

au_image_t au_image[] = {
	{"preinst.img", 0, -1, AU_SCRIPT},
	{"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
	{"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
	{"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
	{"work.img", 0xfe500000, 0x01400000, AU_NOR},
	{"data.img", 0xff900000, 0x00580000, AU_NOR},
	{"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
	{"postinst.img", 0, 0, AU_SCRIPT},
};

int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));

int board_revision(void)
{
	unsigned long CPC0_CR0Reg;
	unsigned long value;

	/*
	 * Get version of APC405 board from GPIO's
	 */

	/* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
	CPC0_CR0Reg = mfdcr(CPC0_CR0);
	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);

	/* wait some time before reading input */
	udelay(1000);

	/* get config bits */
	value = in_be32((void*)GPIO0_IR) & 0x001c0000;
	/*
	 * Restore GPIO settings
	 */
	mtdcr(CPC0_CR0, CPC0_CR0Reg);

	switch (value) {
	case 0x001c0000:
		/* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
		return 2;
	case 0x000c0000:
		/* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
		return 3;
	case 0x00180000:
		/* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
		return 6;
	case 0x00140000:
		/* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
		return 8;
	default:
		/* should not be reached! */
		return 0;
	}
}

int board_early_init_f (void)
{
	/*
	 * First pull fpga-prg pin low, to disable fpga logic
	 */
	out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins */
	out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output   */
	out_be32((void*)GPIO0_OR, 0);                  /* pull prg low       */

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	 */
	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
	mtdcr(UIC0PR, 0xFFFFFF81);       /* set int polarities */
	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0 */
	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */

	/*
	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
	 */
	mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */

	/*
	 * New boards have a single 32MB flash connected to CS0
	 * instead of two 16MB flashes on CS0+1.
	 */
	if (board_revision() >= 8) {
		/* disable CS1 */
		mtebc(PB1AP, 0);
		mtebc(PB1CR, 0);

		/* resize CS0 to 32MB */
		mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
		mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
	}

	return 0;
}

int board_early_init_r(void)
{
	if (gd->board_type >= 8)
		cfi_flash_num_flash_banks = 1;

	return 0;
}

#define FUJI_BASE    0xf0100200
#define LCDBL_PWM    0xa0
#define LCDBL_PWMMIN 0xa4
#define LCDBL_PWMMAX 0xa8

int misc_init_r(void)
{
	u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
	u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
	u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
	u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
	unsigned char *dst;
	ulong len = sizeof(fpgadata);
	int status;
	int index;
	int i;
	unsigned long CPC0_CR0Reg;
	char *str;
	uchar *logo_addr;
	ulong logo_size;
	ushort minb, maxb;
	int result;

	/*
	 * Setup GPIO pins (CS6+CS7 as GPIO)
	 */
	CPC0_CR0Reg = mfdcr(CPC0_CR0);
	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);

	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
		printf("GUNZIP ERROR - must RESET board to recover\n");
		do_reset(NULL, 0, 0, NULL);
	}

	status = fpga_boot(dst, len);
	if (status != 0) {
		printf("\nFPGA: Booting failed ");
		switch (status) {
		case ERROR_FPGA_PRG_INIT_LOW:
			printf("(Timeout: "
			       "INIT not low after asserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_INIT_HIGH:
			printf("(Timeout: "
			       "INIT not high after deasserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_DONE:
			printf("(Timeout: "
			       "DONE not high after programming FPGA)\n ");
			break;
		}

		/* display infos on fpgaimage */
		index = 15;
		for (i = 0; i < 4; i++) {
			len = dst[index];
			printf("FPGA: %s\n", &(dst[index+1]));
			index += len + 3;
		}
		putc('\n');
		/* delayed reboot */
		for (i = 20; i > 0; i--) {
			printf("Rebooting in %2d seconds \r",i);
			for (index = 0; index < 1000; index++)
				udelay(1000);
		}
		putc('\n');
		do_reset(NULL, 0, 0, NULL);
	}

	/* restore gpio/cs settings */
	mtdcr(CPC0_CR0, CPC0_CR0Reg);

	puts("FPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i = 0; i < 4; i++) {
		len = dst[index];
		printf("%s ", &(dst[index + 1]));
		index += len + 3;
	}
	putc('\n');

	free(dst);

	/*
	 * Reset FPGA via FPGA_DATA pin
	 */
	SET_FPGA(FPGA_PRG | FPGA_CLK);
	udelay(1000); /* wait 1ms */
	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
	udelay(1000); /* wait 1ms */

	/*
	 * Write board revision in FPGA
	 */
	out_be16(fpga_ctrl2,
		 (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));

	/*
	 * Enable power on PS/2 interface (with reset)
	 */
	out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
	for (i=0;i<100;i++)
		udelay(1000);
	udelay(1000);
	out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);

	/*
	 * Enable interrupts in exar duart mcr[3]
	 */
	out_8(duart0_mcr, 0x08);
	out_8(duart1_mcr, 0x08);

	/*
	 * Init lcd interface and display logo
	 */
	str = getenv("splashimage");
	if (str) {
		logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
		logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
	} else {
		logo_addr = logo_bmp;
		logo_size = sizeof(logo_bmp);
	}

	if (gd->board_type >= 6) {
		result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
				  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
				  regs_13505_640_480_16bpp,
				  sizeof(regs_13505_640_480_16bpp) /
				  sizeof(regs_13505_640_480_16bpp[0]),
				  logo_addr, logo_size);
		if (result && str) {
			/* retry with internal image */
			logo_addr = logo_bmp;
			logo_size = sizeof(logo_bmp);
			lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
				 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
				 regs_13505_640_480_16bpp,
				 sizeof(regs_13505_640_480_16bpp) /
				 sizeof(regs_13505_640_480_16bpp[0]),
				 logo_addr, logo_size);
		}
	} else {
		result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
				  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
				  regs_13806_640_480_16bpp,
				  sizeof(regs_13806_640_480_16bpp) /
				  sizeof(regs_13806_640_480_16bpp[0]),
				  logo_addr, logo_size);
		if (result && str) {
			/* retry with internal image */
			logo_addr = logo_bmp;
			logo_size = sizeof(logo_bmp);
			lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
				 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
				 regs_13806_640_480_16bpp,
				 sizeof(regs_13806_640_480_16bpp) /
				 sizeof(regs_13806_640_480_16bpp[0]),
				 logo_addr, logo_size);
		}
	}

	/*
	 * Reset microcontroller and setup backlight PWM controller
	 */
	out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
	for (i=0;i<10;i++)
		udelay(1000);
	out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);

	minb = 0;
	maxb = 0xff;
	str = getenv("lcdbl");
	if (str) {
		minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
		if (str && (*str=',')) {
			str++;
			maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
		} else
			minb = 0;

		out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
		out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);

		printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
	}
	out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);

	/*
	 * fix environment for field updated units
	 */
	if (getenv("altbootcmd") == NULL) {
		setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
		setenv("usbargs", CONFIG_SYS_USB_ARGS);
		setenv("bootcmd", CONFIG_BOOTCOMMAND);
		setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
		setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
		setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
		saveenv();
	}

	return (0);
}

/*
 * Check Board Identity:
 */
int checkboard (void)
{
	char str[64];
	int i = getenv_f("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming APC405");
	} else {
		puts(str);
	}

	gd->board_type = board_revision();
	printf(", Rev. 1.%ld\n", gd->board_type);

	return 0;
}

#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
	u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);

	/*
	 * Assert or deassert CompactFlash Reset Pin
	 */
	if (on) {
		out_be16(fpga_mode,
			 in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
	} else {
		out_be16(fpga_mode,
			 in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
	}
}
#endif /* CONFIG_IDE_RESET */

void reset_phy(void)
{
	/*
	 * Disable sleep mode in LXT971
	 */
	lxt971_no_sleep();
}

#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
int usb_board_init(void)
{
	return 0;
}

int usb_board_stop(void)
{
	unsigned short tmp;
	int i;

	/*
	 * reset PCI bus
	 * This is required to make some very old Linux OHCI driver
	 * work after U-Boot has used the OHCI controller.
	 */
	pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
	pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));

	for (i = 0; i < 100; i++)
		udelay(1000);

	pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
	return 0;
}

int usb_board_init_fail(void)
{
	usb_board_stop();
	return 0;
}
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
Commit	Line	Data
1bc0f141	1	/*
0b987251 MF	2	* (C) Copyright 2005-2008
	3	* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
	4	*
1bc0f141 SR	5	* (C) Copyright 2001-2003
	6	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
1bc0f141 SR	9	*/
	10
	11	#include <common.h>
	12	#include <asm/processor.h>
0b987251	13	#include <asm/io.h>
1bc0f141 SR	14	#include <command.h>
1bc0f141 SR	15	#include <malloc.h>
0b987251	16	#include <flash.h>
ca5def3f	17	#include <mtd/cfi_flash.h>
0b987251 MF	18	#include <asm/4xx_pci.h>
0b987251 MF	19	#include <pci.h>
1bc0f141	20
d87080b7	21	DECLARE_GLOBAL_DATA_PTR;
1bc0f141	22
0b987251	23	#undef FPGA_DEBUG
1bc0f141	24
1bc0f141 SR	25	extern void lxt971_no_sleep(void);
	26
	27	/* fpga configuration data - gzip compressed and generated by bin2c */
	28	const unsigned char fpgadata[] =
	29	{
	30	#include "fpgadata.c"
	31	};
	32
	33	/*
	34	* include common fpga code (for esd boards)
	35	*/
	36	#include "../common/fpga.c"
	37
1bc0f141 SR	38	#ifdef CONFIG_LCD_USED
	39	/* logo bitmap data - gzip compressed and generated by bin2c */
	40	unsigned char logo_bmp[] =
	41	{
0b987251	42	#include "logo_640_480_24bpp.c"
1bc0f141 SR	43	};
	44
	45	/*
	46	* include common lcd code (for esd boards)
	47	*/
	48	#include "../common/lcd.c"
0b987251 MF	49	#include "../common/s1d13505_640_480_16bpp.h"
0b987251 MF	50	#include "../common/s1d13806_640_480_16bpp.h"
1bc0f141 SR	51	#endif /* CONFIG_LCD_USED */
1bc0f141 SR	52
0b987251 MF	53	/*
	54	* include common auto-update code (for esd boards)
	55	*/
	56	#include "../common/auto_update.h"
	57
	58	au_image_t au_image[] = {
	59	{"preinst.img", 0, -1, AU_SCRIPT},
	60	{"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE \| AU_PROTECT},
	61	{"pImage", 0xfe000000, 0x00100000, AU_NOR \| AU_PROTECT},
	62	{"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR \| AU_PROTECT},
	63	{"work.img", 0xfe500000, 0x01400000, AU_NOR},
	64	{"data.img", 0xff900000, 0x00580000, AU_NOR},
	65	{"logo.img", 0xffe80000, 0x00100000, AU_NOR \| AU_PROTECT},
	66	{"postinst.img", 0, 0, AU_SCRIPT},
	67	};
	68
	69	int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
1bc0f141	70
04e93ec9 SR	71	int board_revision(void)
04e93ec9 SR	72	{
d1c3b275	73	unsigned long CPC0_CR0Reg;
049216f0	74	unsigned long value;
04e93ec9 SR	75
	76	/*
	77	* Get version of APC405 board from GPIO's
	78	*/
	79
0b987251	80	/* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
d1c3b275 SR	81	CPC0_CR0Reg = mfdcr(CPC0_CR0);
d1c3b275 SR	82	mtdcr(CPC0_CR0, CPC0_CR0Reg \| 0x03800000);
0b987251 MF	83	out_be32((void)GPIO0_ODR, in_be32((void)GPIO0_ODR) & ~0x001c0000);
	84	out_be32((void)GPIO0_TCR, in_be32((void)GPIO0_TCR) & ~0x001c0000);
	85
	86	/* wait some time before reading input */
	87	udelay(1000);
04e93ec9	88
0b987251 MF	89	/* get config bits */
0b987251 MF	90	value = in_be32((void*)GPIO0_IR) & 0x001c0000;
04e93ec9 SR	91	/*
	92	* Restore GPIO settings
	93	*/
d1c3b275	94	mtdcr(CPC0_CR0, CPC0_CR0Reg);
04e93ec9 SR	95
04e93ec9 SR	96	switch (value) {
0b987251 MF	97	case 0x001c0000:
0b987251 MF	98	/* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
04e93ec9	99	return 2;
0b987251 MF	100	case 0x000c0000:
0b987251 MF	101	/* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
04e93ec9	102	return 3;
0b987251 MF	103	case 0x00180000:
	104	/* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
	105	return 6;
	106	case 0x00140000:
	107	/* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
	108	return 8;
04e93ec9 SR	109	default:
	110	/* should not be reached! */
	111	return 0;
	112	}
	113	}
	114
1bc0f141 SR	115	int board_early_init_f (void)
	116	{
	117	/*
0b987251	118	* First pull fpga-prg pin low, to disable fpga logic
1bc0f141	119	*/
0b987251	120	out_be32((void)GPIO0_ODR, 0x00000000); / no open drain pins */
6d0f6bcf	121	out_be32((void)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); / setup for output */
0b987251	122	out_be32((void)GPIO0_OR, 0); / pull prg low */
1bc0f141 SR	123
	124	/*
	125	* IRQ 0-15 405GP internally generated; active high; level sensitive
	126	* IRQ 16 405GP internally generated; active low; level sensitive
	127	* IRQ 17-24 RESERVED
	128	* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	129	* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	130	* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	131	* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	132	* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	133	* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	134	* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	135	*/
952e7760 SR	136	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
	137	mtdcr(UIC0ER, 0x00000000); /* disable all ints */
	138	mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
	139	mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
	140	mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
	141	mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */
	142	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
1bc0f141 SR	143
1bc0f141 SR	144	/*
0b987251 MF	145	* EBC Configuration Register: set ready timeout to 512 ebc-clks
0b987251 MF	146	*/
d1c3b275	147	mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
0b987251 MF	148
	149	/*
	150	* New boards have a single 32MB flash connected to CS0
	151	* instead of two 16MB flashes on CS0+1.
1bc0f141	152	*/
0b987251 MF	153	if (board_revision() >= 8) {
0b987251 MF	154	/* disable CS1 */
d1c3b275 SR	155	mtebc(PB1AP, 0);
d1c3b275 SR	156	mtebc(PB1CR, 0);
0b987251 MF	157
0b987251 MF	158	/* resize CS0 to 32MB */
d1c3b275 SR	159	mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
d1c3b275 SR	160	mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
0b987251	161	}
1bc0f141 SR	162
	163	return 0;
	164	}
	165
0b987251	166	int board_early_init_r(void)
1bc0f141	167	{
0b987251	168	if (gd->board_type >= 8)
ca5def3f	169	cfi_flash_num_flash_banks = 1;
0b987251 MF	170
0b987251 MF	171	return 0;
1bc0f141 SR	172	}
1bc0f141 SR	173
0b987251 MF	174	#define FUJI_BASE 0xf0100200
	175	#define LCDBL_PWM 0xa0
	176	#define LCDBL_PWMMIN 0xa4
	177	#define LCDBL_PWMMAX 0xa8
1bc0f141	178
0b987251	179	int misc_init_r(void)
1bc0f141	180	{
6d0f6bcf JCPV	181	u16 fpga_mode = (u16 )(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
6d0f6bcf JCPV	182	u16 fpga_ctrl2 =(u16 )(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
0b987251 MF	183	u8 duart0_mcr = (u8 )(DUART0_BA + 4);
0b987251 MF	184	u8 duart1_mcr = (u8 )(DUART1_BA + 4);
1bc0f141 SR	185	unsigned char *dst;
	186	ulong len = sizeof(fpgadata);
	187	int status;
	188	int index;
	189	int i;
d1c3b275	190	unsigned long CPC0_CR0Reg;
0b987251 MF	191	char *str;
	192	uchar *logo_addr;
	193	ulong logo_size;
	194	ushort minb, maxb;
	195	int result;
1bc0f141 SR	196
	197	/*
	198	* Setup GPIO pins (CS6+CS7 as GPIO)
	199	*/
d1c3b275 SR	200	CPC0_CR0Reg = mfdcr(CPC0_CR0);
d1c3b275 SR	201	mtdcr(CPC0_CR0, CPC0_CR0Reg \| 0x00300000);
1bc0f141	202
6d0f6bcf JCPV	203	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
6d0f6bcf JCPV	204	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
0b987251 MF	205	printf("GUNZIP ERROR - must RESET board to recover\n");
0b987251 MF	206	do_reset(NULL, 0, 0, NULL);
1bc0f141 SR	207	}
	208
	209	status = fpga_boot(dst, len);
	210	if (status != 0) {
	211	printf("\nFPGA: Booting failed ");
	212	switch (status) {
	213	case ERROR_FPGA_PRG_INIT_LOW:
0b987251 MF	214	printf("(Timeout: "
0b987251 MF	215	"INIT not low after asserting PROGRAM*)\n ");
1bc0f141 SR	216	break;
1bc0f141 SR	217	case ERROR_FPGA_PRG_INIT_HIGH:
0b987251 MF	218	printf("(Timeout: "
0b987251 MF	219	"INIT not high after deasserting PROGRAM*)\n ");
1bc0f141 SR	220	break;
1bc0f141 SR	221	case ERROR_FPGA_PRG_DONE:
0b987251 MF	222	printf("(Timeout: "
0b987251 MF	223	"DONE not high after programming FPGA)\n ");
1bc0f141 SR	224	break;
	225	}
	226
	227	/* display infos on fpgaimage */
	228	index = 15;
0b987251	229	for (i = 0; i < 4; i++) {
1bc0f141 SR	230	len = dst[index];
1bc0f141 SR	231	printf("FPGA: %s\n", &(dst[index+1]));
0b987251	232	index += len + 3;
1bc0f141	233	}
0b987251	234	putc('\n');
1bc0f141	235	/* delayed reboot */
0b987251	236	for (i = 20; i > 0; i--) {
1bc0f141	237	printf("Rebooting in %2d seconds \r",i);
0b987251	238	for (index = 0; index < 1000; index++)
1bc0f141 SR	239	udelay(1000);
1bc0f141 SR	240	}
0b987251	241	putc('\n');
1bc0f141 SR	242	do_reset(NULL, 0, 0, NULL);
	243	}
	244
	245	/* restore gpio/cs settings */
d1c3b275	246	mtdcr(CPC0_CR0, CPC0_CR0Reg);
1bc0f141 SR	247
	248	puts("FPGA: ");
	249
	250	/* display infos on fpgaimage */
	251	index = 15;
0b987251	252	for (i = 0; i < 4; i++) {
1bc0f141	253	len = dst[index];
0b987251 MF	254	printf("%s ", &(dst[index + 1]));
0b987251 MF	255	index += len + 3;
1bc0f141	256	}
0b987251	257	putc('\n');
1bc0f141 SR	258
	259	free(dst);
	260
	261	/*
	262	* Reset FPGA via FPGA_DATA pin
	263	*/
	264	SET_FPGA(FPGA_PRG \| FPGA_CLK);
	265	udelay(1000); /* wait 1ms */
	266	SET_FPGA(FPGA_PRG \| FPGA_CLK \| FPGA_DATA);
	267	udelay(1000); /* wait 1ms */
	268
04e93ec9 SR	269	/*
	270	* Write board revision in FPGA
	271	*/
0b987251 MF	272	out_be16(fpga_ctrl2,
0b987251 MF	273	(in_be16(fpga_ctrl2) & 0xfff0) \| (gd->board_type & 0x000f));
04e93ec9	274
1bc0f141 SR	275	/*
	276	* Enable power on PS/2 interface (with reset)
	277	*/
6d0f6bcf	278	out_be16(fpga_mode, in_be16(fpga_mode) \| CONFIG_SYS_FPGA_CTRL_PS2_RESET);
1bc0f141 SR	279	for (i=0;i<100;i++)
	280	udelay(1000);
	281	udelay(1000);
6d0f6bcf	282	out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
1bc0f141 SR	283
	284	/*
	285	* Enable interrupts in exar duart mcr[3]
	286	*/
0b987251 MF	287	out_8(duart0_mcr, 0x08);
0b987251 MF	288	out_8(duart1_mcr, 0x08);
1bc0f141 SR	289
	290	/*
	291	* Init lcd interface and display logo
	292	*/
0b987251 MF	293	str = getenv("splashimage");
	294	if (str) {
	295	logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
6d0f6bcf	296	logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
0b987251 MF	297	} else {
	298	logo_addr = logo_bmp;
	299	logo_size = sizeof(logo_bmp);
	300	}
	301
	302	if (gd->board_type >= 6) {
6d0f6bcf JCPV	303	result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
6d0f6bcf JCPV	304	(uchar *)CONFIG_SYS_LCD_BIG_MEM,
0b987251 MF	305	regs_13505_640_480_16bpp,
	306	sizeof(regs_13505_640_480_16bpp) /
	307	sizeof(regs_13505_640_480_16bpp[0]),
	308	logo_addr, logo_size);
	309	if (result && str) {
	310	/* retry with internal image */
	311	logo_addr = logo_bmp;
	312	logo_size = sizeof(logo_bmp);
6d0f6bcf JCPV	313	lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
6d0f6bcf JCPV	314	(uchar *)CONFIG_SYS_LCD_BIG_MEM,
0b987251 MF	315	regs_13505_640_480_16bpp,
	316	sizeof(regs_13505_640_480_16bpp) /
	317	sizeof(regs_13505_640_480_16bpp[0]),
	318	logo_addr, logo_size);
	319	}
	320	} else {
6d0f6bcf JCPV	321	result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
6d0f6bcf JCPV	322	(uchar *)CONFIG_SYS_LCD_BIG_MEM,
0b987251 MF	323	regs_13806_640_480_16bpp,
	324	sizeof(regs_13806_640_480_16bpp) /
	325	sizeof(regs_13806_640_480_16bpp[0]),
	326	logo_addr, logo_size);
	327	if (result && str) {
	328	/* retry with internal image */
	329	logo_addr = logo_bmp;
	330	logo_size = sizeof(logo_bmp);
6d0f6bcf JCPV	331	lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
6d0f6bcf JCPV	332	(uchar *)CONFIG_SYS_LCD_BIG_MEM,
0b987251 MF	333	regs_13806_640_480_16bpp,
	334	sizeof(regs_13806_640_480_16bpp) /
	335	sizeof(regs_13806_640_480_16bpp[0]),
	336	logo_addr, logo_size);
	337	}
	338	}
1bc0f141 SR	339
1bc0f141 SR	340	/*
04e93ec9	341	* Reset microcontroller and setup backlight PWM controller
1bc0f141	342	*/
0b987251	343	out_be16(fpga_mode, in_be16(fpga_mode) \| 0x0014);
04e93ec9 SR	344	for (i=0;i<10;i++)
04e93ec9 SR	345	udelay(1000);
0b987251 MF	346	out_be16(fpga_mode, in_be16(fpga_mode) \| 0x001c);
	347
	348	minb = 0;
	349	maxb = 0xff;
	350	str = getenv("lcdbl");
	351	if (str) {
	352	minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
	353	if (str && (*str=',')) {
	354	str++;
	355	maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
	356	} else
	357	minb = 0;
	358
	359	out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
	360	out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
	361
	362	printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
	363	}
	364	out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
	365
8e048c43 MF	366	/*
	367	* fix environment for field updated units
	368	*/
	369	if (getenv("altbootcmd") == NULL) {
6d0f6bcf JCPV	370	setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
6d0f6bcf JCPV	371	setenv("usbargs", CONFIG_SYS_USB_ARGS);
0b987251	372	setenv("bootcmd", CONFIG_BOOTCOMMAND);
6d0f6bcf JCPV	373	setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
	374	setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
	375	setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
0b987251 MF	376	saveenv();
0b987251 MF	377	}
1bc0f141 SR	378
	379	return (0);
	380	}
	381
1bc0f141 SR	382	/*
	383	* Check Board Identity:
	384	*/
1bc0f141 SR	385	int checkboard (void)
1bc0f141 SR	386	{
0b987251	387	char str[64];
cdb74977	388	int i = getenv_f("serial#", str, sizeof(str));
1bc0f141 SR	389
	390	puts ("Board: ");
	391
	392	if (i == -1) {
	393	puts ("### No HW ID - assuming APC405");
	394	} else {
	395	puts(str);
	396	}
	397
04e93ec9	398	gd->board_type = board_revision();
0b987251	399	printf(", Rev. 1.%ld\n", gd->board_type);
1bc0f141 SR	400
	401	return 0;
	402	}
	403
0b987251 MF	404	#ifdef CONFIG_IDE_RESET
0b987251 MF	405	void ide_set_reset(int on)
1bc0f141	406	{
6d0f6bcf	407	u16 fpga_mode = (u16 )(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
1bc0f141	408
0b987251 MF	409	/*
	410	* Assert or deassert CompactFlash Reset Pin
	411	*/
	412	if (on) {
	413	out_be16(fpga_mode,
6d0f6bcf	414	in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
0b987251 MF	415	} else {
0b987251 MF	416	out_be16(fpga_mode,
6d0f6bcf	417	in_be16(fpga_mode) \| CONFIG_SYS_FPGA_CTRL_CF_RESET);
0b987251	418	}
1bc0f141	419	}
0b987251	420	#endif /* CONFIG_IDE_RESET */
1bc0f141	421
0b987251 MF	422	void reset_phy(void)
	423	{
	424	/*
	425	* Disable sleep mode in LXT971
	426	*/
	427	lxt971_no_sleep();
	428	}
1bc0f141	429
6d0f6bcf	430	#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
0b987251 MF	431	int usb_board_init(void)
	432	{
	433	return 0;
	434	}
1bc0f141	435
0b987251	436	int usb_board_stop(void)
1bc0f141	437	{
0b987251 MF	438	unsigned short tmp;
0b987251 MF	439	int i;
1bc0f141 SR	440
1bc0f141 SR	441	/*
0b987251 MF	442	* reset PCI bus
	443	* This is required to make some very old Linux OHCI driver
	444	* work after U-Boot has used the OHCI controller.
1bc0f141	445	*/
0b987251 MF	446	pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
0b987251 MF	447	pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp \| 0x1000));
1bc0f141	448
0b987251 MF	449	for (i = 0; i < 100; i++)
0b987251 MF	450	udelay(1000);
1bc0f141	451
0b987251 MF	452	pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
	453	return 0;
	454	}
	455
	456	int usb_board_init_fail(void)
	457	{
	458	usb_board_stop();
	459	return 0;
	460	}
6d0f6bcf	461	#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */