[people/ms/u-boot.git] / board / esd / ar405 / ar405.c

/*
 * (C) Copyright 2001-2004
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include "ar405.h"
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>

DECLARE_GLOBAL_DATA_PTR;

/*cmd_boot.c*/
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern void lxt971_no_sleep(void);

/* ------------------------------------------------------------------------- */

#if 0
#define FPGA_DEBUG
#endif

/* fpga configuration data - generated by bin2cc */
const unsigned char fpgadata[] = {
#include "fpgadata.c"
};

const unsigned char fpgadata_xl30[] = {
#include "fpgadata_xl30.c"
};

/*
 * include common fpga code (for esd boards)
 */
#include "../common/fpga.c"


int board_early_init_f (void)
{
	int index, len, i;
	int status;

#ifdef FPGA_DEBUG
	/* set up serial port with default baudrate */
	(void) get_clocks ();
	gd->baudrate = CONFIG_BAUDRATE;
	serial_init ();
	console_init_f ();
#endif

	/*
	 * Boot onboard FPGA
	 */
	/* first try 40er image */
	gd->board_type = 40;
	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
	if (status != 0) {
		/* try xl30er image */
		gd->board_type = 30;
		status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
		if (status != 0) {
			/* booting FPGA failed */
#ifndef FPGA_DEBUG
			/* set up serial port with default baudrate */
			(void) get_clocks ();
			gd->baudrate = CONFIG_BAUDRATE;
			serial_init ();
			console_init_f ();
#endif
			printf ("\nFPGA: Booting failed ");
			switch (status) {
			case ERROR_FPGA_PRG_INIT_LOW:
				printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
				break;
			case ERROR_FPGA_PRG_INIT_HIGH:
				printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
				break;
			case ERROR_FPGA_PRG_DONE:
				printf ("(Timeout: DONE not high after programming FPGA)\n ");
				break;
			}

			/* display infos on fpgaimage */
			index = 15;
			for (i = 0; i < 4; i++) {
				len = fpgadata[index];
				printf ("FPGA: %s\n", &(fpgadata[index + 1]));
				index += len + 3;
			}
			putc ('\n');
			/* delayed reboot */
			for (i = 20; i > 0; i--) {
				printf ("Rebooting in %2d seconds \r", i);
				for (index = 0; index < 1000; index++)
					udelay (1000);
			}
			putc ('\n');
			do_reset (NULL, 0, 0, NULL);
		}
	}

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	 */
	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
	mtdcr (UIC0PR, 0xFFFFFF81);	/* set int polarities */
	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */

	out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */

	return 0;
}

/*
 * Check Board Identity:
 */
int checkboard (void)
{
	int index;
	int len;
	char str[64];
	int i = getenv_f("serial#", str, sizeof (str));
	const unsigned char *fpga;

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming AR405");
	} else {
		puts(str);
	}

	puts ("\nFPGA:  ");

	/* display infos on fpgaimage */
	if (gd->board_type == 30) {
		fpga = fpgadata_xl30;
	} else {
		fpga = fpgadata;
	}
	index = 15;
	for (i = 0; i < 4; i++) {
		len = fpga[index];
		printf ("%s ", &(fpga[index + 1]));
		index += len + 3;
	}

	putc ('\n');

	/*
	 * Disable sleep mode in LXT971
	 */
	lxt971_no_sleep();

	return 0;
}


#if 1 /* test-only: some internal test routines... */
#define DIGEN	((void *)0xf03000b4) /* u8 */
#define DIGOUT	((void *)0xf03000b0) /* u16 */
#define DIGIN	((void *)0xf03000a0) /* u16 */

/*
 * Some test routines
 */
int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	int i;
	int k;
	int start;
	int end;

	if (argc != 3) {
		puts("Usage: digtest n_start n_end (digtest 0 7)\n");
		return 0;
	}

	start = simple_strtol (argv[1], NULL, 10);
	end = simple_strtol (argv[2], NULL, 10);

	/*
	 * Enable digital outputs
	 */
	out_8(DIGEN, 0x08);

	printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n",
	       start, end);

	/*
	 * Set outputs one by one
	 */
	for (;;) {
		for (i=start; i<=end; i++) {
			out_be16(DIGOUT, 0x0001 << i);
			for (k=0; k<200; k++)
				udelay(1000);

			if (in_be16(DIGIN) != (0x0001 << i)) {
				printf("ERROR: OUT=0x%04X, IN=0x%04X\n",
				       0x0001 << i, in_be16(DIGIN));
				return 0;
			}

			/* Abort if ctrl-c was pressed */
			if (ctrlc()) {
				puts("\nAbort\n");
				return 0;
			}
		}
	}

	return 0;
}
U_BOOT_CMD(
	digtest,	3,	1,	do_digtest,
	"Test digital in-/output",
	""
);

#define ERROR_DELTA     256

struct io {
	short val;
	short dummy;
};

int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	short val;
	int i;
	int volt;
	struct io *out;
	struct io *in;

	out = (struct io *)0xf0300090;
	in = (struct io *)0xf0300000;

	i = simple_strtol (argv[1], NULL, 10);

	volt = 0;
	printf("Setting Channel %d to %dV...\n", i, volt);
	out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
	udelay(10000);
	val = in_be16((void *)&(in[i*2].val));
	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
		return -1;
	}
	val = in_be16((void *)&(in[i*2+1].val));
	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
		return -1;
	}

	volt = 5;
	printf("Setting Channel %d to %dV...\n", i, volt);
	out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
	udelay(10000);
	val = in_be16((void *)&(in[i*2].val));
	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
		return -1;
	}
	val = in_be16((void *)&(in[i*2+1].val));
	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
		return -1;
	}

	volt = 10;
	printf("Setting Channel %d to %dV...\n", i, volt);
	out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
	udelay(10000);
	val = in_be16((void *)&(in[i*2].val));
	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
		return -1;
	}
	val = in_be16((void *)&(in[i*2+1].val));
	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
		return -1;
	}

	printf("Channel %d OK!\n", i);

	return 0;
}
U_BOOT_CMD(
	anatest,	2,	1,	do_anatest,
	"Test analog in-/output",
	""
);


int counter = 0;

void cyclicInt(void *ptr)
{
	out_be16((void *)0xf03000e8, 0x0800); /* ack int */
	counter++;
}


int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	ulong *incin;
	int i;

	incin = (ulong *)0xf0300040;

	/*
	 * Clear inc counter
	 */
	out_be32((void *)&incin[0], 0);
	out_be32((void *)&incin[1], 0);
	out_be32((void *)&incin[2], 0);
	out_be32((void *)&incin[3], 0);

	incin = (ulong *)0xf0300050;

	/*
	 * Inc a little
	 */
	for (i=0; i<10000; i++) {
		switch (i & 0x03) {
		case 0:
			out_8(DIGEN, 0x02);
			break;
		case 1:
			out_8(DIGEN, 0x03);
			break;
		case 2:
			out_8(DIGEN, 0x01);
			break;
		case 3:
			out_8(DIGEN, 0x00);
			break;
		}
		udelay(10);
	}

	printf("Inc 0 = %d\n", in_be32((void *)&incin[0]));
	printf("Inc 1 = %d\n", in_be32((void *)&incin[1]));
	printf("Inc 2 = %d\n", in_be32((void *)&incin[2]));
	printf("Inc 3 = %d\n", in_be32((void *)&incin[3]));

	out_be16((void *)0xf03000e0, 0x0c80-1); /* set counter */
	out_be16((void *)0xf03000ec,
		 in_be16((void *)0xf03000ec) | 0x0800); /* enable int */
	irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL);
	printf("counter=%d\n", counter);

	return 0;
}
U_BOOT_CMD(
	inctest,	3,	1,	do_inctest,
	"Test incremental encoder inputs",
	""
);
#endif
Commit	Line	Data
153d511e	1	/*
8b1ccd86	2	* (C) Copyright 2001-2004
153d511e WD	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include "ar405.h"
	26	#include <asm/processor.h>
049216f0	27	#include <asm/io.h>
153d511e	28	#include <command.h>
153d511e	29
d87080b7 WD	30	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	31
8bde7f77	32	/cmd_boot.c/
54841ab5	33	extern int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char const argv[]);
8b1ccd86	34	extern void lxt971_no_sleep(void);
153d511e WD	35
	36	/* ------------------------------------------------------------------------- */
	37
	38	#if 0
	39	#define FPGA_DEBUG
	40	#endif
	41
	42	/* fpga configuration data - generated by bin2cc */
	43	const unsigned char fpgadata[] = {
	44	#include "fpgadata.c"
	45	};
	46
8b1ccd86 SR	47	const unsigned char fpgadata_xl30[] = {
	48	#include "fpgadata_xl30.c"
	49	};
	50
153d511e WD	51	/*
	52	* include common fpga code (for esd boards)
	53	*/
	54	#include "../common/fpga.c"
	55
	56
c837dcb1	57	int board_early_init_f (void)
153d511e	58	{
153d511e WD	59	int index, len, i;
	60	int status;
	61
	62	#ifdef FPGA_DEBUG
	63	/* set up serial port with default baudrate */
	64	(void) get_clocks ();
	65	gd->baudrate = CONFIG_BAUDRATE;
	66	serial_init ();
	67	console_init_f ();
	68	#endif
	69
	70	/*
	71	* Boot onboard FPGA
	72	*/
8b1ccd86 SR	73	/* first try 40er image */
8b1ccd86 SR	74	gd->board_type = 40;
153d511e WD	75	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
153d511e WD	76	if (status != 0) {
8b1ccd86 SR	77	/* try xl30er image */
	78	gd->board_type = 30;
	79	status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
	80	if (status != 0) {
	81	/* booting FPGA failed */
153d511e	82	#ifndef FPGA_DEBUG
8b1ccd86 SR	83	/* set up serial port with default baudrate */
	84	(void) get_clocks ();
	85	gd->baudrate = CONFIG_BAUDRATE;
	86	serial_init ();
	87	console_init_f ();
153d511e	88	#endif
8b1ccd86 SR	89	printf ("\nFPGA: Booting failed ");
	90	switch (status) {
	91	case ERROR_FPGA_PRG_INIT_LOW:
	92	printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
	93	break;
	94	case ERROR_FPGA_PRG_INIT_HIGH:
	95	printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
	96	break;
	97	case ERROR_FPGA_PRG_DONE:
	98	printf ("(Timeout: DONE not high after programming FPGA)\n ");
	99	break;
	100	}
	101
	102	/* display infos on fpgaimage */
	103	index = 15;
	104	for (i = 0; i < 4; i++) {
	105	len = fpgadata[index];
	106	printf ("FPGA: %s\n", &(fpgadata[index + 1]));
	107	index += len + 3;
	108	}
	109	putc ('\n');
	110	/* delayed reboot */
	111	for (i = 20; i > 0; i--) {
	112	printf ("Rebooting in %2d seconds \r", i);
	113	for (index = 0; index < 1000; index++)
	114	udelay (1000);
	115	}
	116	putc ('\n');
	117	do_reset (NULL, 0, 0, NULL);
153d511e	118	}
153d511e WD	119	}
	120
	121	/*
	122	* IRQ 0-15 405GP internally generated; active high; level sensitive
	123	* IRQ 16 405GP internally generated; active low; level sensitive
	124	* IRQ 17-24 RESERVED
	125	* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	126	* IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
	127	* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
	128	* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
	129	* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
	130	* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
	131	* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	132	*/
952e7760 SR	133	mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
	134	mtdcr (UIC0ER, 0x00000000); /* disable all ints */
	135	mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
	136	mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
	137	mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
	138	mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
	139	mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
153d511e	140
049216f0	141	out_be16((void )0xf03000ec, 0x0fff); / enable interrupts in fpga */
153d511e WD	142
	143	return 0;
	144	}
	145
153d511e WD	146	/*
	147	* Check Board Identity:
	148	*/
153d511e WD	149	int checkboard (void)
	150	{
	151	int index;
	152	int len;
77ddac94	153	char str[64];
cdb74977	154	int i = getenv_f("serial#", str, sizeof (str));
8b1ccd86	155	const unsigned char *fpga;
153d511e WD	156
	157	puts ("Board: ");
	158
8b1ccd86 SR	159	if (i == -1) {
	160	puts ("### No HW ID - assuming AR405");
	161	} else {
	162	puts(str);
153d511e WD	163	}
153d511e WD	164
153d511e WD	165	puts ("\nFPGA: ");
	166
	167	/* display infos on fpgaimage */
8b1ccd86 SR	168	if (gd->board_type == 30) {
	169	fpga = fpgadata_xl30;
	170	} else {
	171	fpga = fpgadata;
	172	}
153d511e WD	173	index = 15;
153d511e WD	174	for (i = 0; i < 4; i++) {
8b1ccd86 SR	175	len = fpga[index];
8b1ccd86 SR	176	printf ("%s ", &(fpga[index + 1]));
153d511e WD	177	index += len + 3;
	178	}
	179
	180	putc ('\n');
	181
8b1ccd86 SR	182	/*
	183	* Disable sleep mode in LXT971
	184	*/
	185	lxt971_no_sleep();
	186
153d511e WD	187	return 0;
	188	}
	189
8d3efe4e SR	190
8d3efe4e SR	191	#if 1 /* test-only: some internal test routines... */
049216f0 MF	192	#define DIGEN ((void )0xf03000b4) / u8 */
	193	#define DIGOUT ((void )0xf03000b0) / u16 */
	194	#define DIGIN ((void )0xf03000a0) / u16 */
	195
8d3efe4e SR	196	/*
	197	* Some test routines
	198	*/
54841ab5	199	int do_digtest(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
8d3efe4e	200	{
8d3efe4e SR	201	int i;
	202	int k;
	203	int start;
	204	int end;
	205
	206	if (argc != 3) {
	207	puts("Usage: digtest n_start n_end (digtest 0 7)\n");
	208	return 0;
	209	}
	210
	211	start = simple_strtol (argv[1], NULL, 10);
	212	end = simple_strtol (argv[2], NULL, 10);
	213
	214	/*
	215	* Enable digital outputs
	216	*/
049216f0	217	out_8(DIGEN, 0x08);
8d3efe4e SR	218
	219	printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n",
	220	start, end);
	221
	222	/*
	223	* Set outputs one by one
	224	*/
	225	for (;;) {
	226	for (i=start; i<=end; i++) {
049216f0	227	out_be16(DIGOUT, 0x0001 << i);
8d3efe4e SR	228	for (k=0; k<200; k++)
	229	udelay(1000);
	230
049216f0 MF	231	if (in_be16(DIGIN) != (0x0001 << i)) {
	232	printf("ERROR: OUT=0x%04X, IN=0x%04X\n",
	233	0x0001 << i, in_be16(DIGIN));
8d3efe4e SR	234	return 0;
	235	}
	236
	237	/* Abort if ctrl-c was pressed */
	238	if (ctrlc()) {
	239	puts("\nAbort\n");
	240	return 0;
	241	}
	242	}
	243	}
	244
	245	return 0;
	246	}
	247	U_BOOT_CMD(
	248	digtest, 3, 1, do_digtest,
2fb2604d	249	"Test digital in-/output",
a89c33db WD	250	""
a89c33db WD	251	);
8d3efe4e SR	252
	253	#define ERROR_DELTA 256
	254
	255	struct io {
049216f0	256	short val;
8d3efe4e SR	257	short dummy;
	258	};
	259
54841ab5	260	int do_anatest(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
8d3efe4e	261	{
049216f0	262	short val;
8d3efe4e SR	263	int i;
	264	int volt;
	265	struct io *out;
	266	struct io *in;
	267
	268	out = (struct io *)0xf0300090;
	269	in = (struct io *)0xf0300000;
	270
	271	i = simple_strtol (argv[1], NULL, 10);
	272
	273	volt = 0;
	274	printf("Setting Channel %d to %dV...\n", i, volt);
049216f0	275	out_be16((void )&(out[i].val), (volt 0x7fff) / 10);
8d3efe4e	276	udelay(10000);
049216f0	277	val = in_be16((void )&(in[i2].val));
8d3efe4e SR	278	printf("-> InChannel %d: 0x%04x=%dV\n", i2, val, (val 4000) / 0x7fff);
	279	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) \|\|
	280	(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
	281	printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
	282	((volt * 0x7fff) / 40) + ERROR_DELTA);
	283	return -1;
	284	}
049216f0	285	val = in_be16((void )&(in[i2+1].val));
8d3efe4e SR	286	printf("-> InChannel %d: 0x%04x=%dV\n", i2+1, val, (val 4000) / 0x7fff);
	287	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) \|\|
	288	(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
	289	printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
	290	((volt * 0x7fff) / 40) + ERROR_DELTA);
	291	return -1;
	292	}
	293
	294	volt = 5;
	295	printf("Setting Channel %d to %dV...\n", i, volt);
049216f0	296	out_be16((void )&(out[i].val), (volt 0x7fff) / 10);
8d3efe4e	297	udelay(10000);
049216f0	298	val = in_be16((void )&(in[i2].val));
8d3efe4e SR	299	printf("-> InChannel %d: 0x%04x=%dV\n", i2, val, (val 4000) / 0x7fff);
	300	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) \|\|
	301	(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
	302	printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
	303	((volt * 0x7fff) / 40) + ERROR_DELTA);
	304	return -1;
	305	}
049216f0	306	val = in_be16((void )&(in[i2+1].val));
8d3efe4e SR	307	printf("-> InChannel %d: 0x%04x=%dV\n", i2+1, val, (val 4000) / 0x7fff);
	308	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) \|\|
	309	(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
	310	printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
	311	((volt * 0x7fff) / 40) + ERROR_DELTA);
	312	return -1;
	313	}
	314
	315	volt = 10;
	316	printf("Setting Channel %d to %dV...\n", i, volt);
049216f0	317	out_be16((void )&(out[i].val), (volt 0x7fff) / 10);
8d3efe4e	318	udelay(10000);
049216f0	319	val = in_be16((void )&(in[i2].val));
8d3efe4e SR	320	printf("-> InChannel %d: 0x%04x=%dV\n", i2, val, (val 4000) / 0x7fff);
	321	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) \|\|
	322	(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
	323	printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
	324	((volt * 0x7fff) / 40) + ERROR_DELTA);
	325	return -1;
	326	}
049216f0	327	val = in_be16((void )&(in[i2+1].val));
8d3efe4e SR	328	printf("-> InChannel %d: 0x%04x=%dV\n", i2+1, val, (val 4000) / 0x7fff);
	329	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) \|\|
	330	(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
	331	printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
	332	((volt * 0x7fff) / 40) + ERROR_DELTA);
	333	return -1;
	334	}
	335
	336	printf("Channel %d OK!\n", i);
	337
	338	return 0;
	339	}
	340	U_BOOT_CMD(
	341	anatest, 2, 1, do_anatest,
2fb2604d	342	"Test analog in-/output",
a89c33db WD	343	""
a89c33db WD	344	);
8d3efe4e SR	345
	346
	347	int counter = 0;
	348
	349	void cyclicInt(void *ptr)
	350	{
049216f0	351	out_be16((void )0xf03000e8, 0x0800); / ack int */
8d3efe4e SR	352	counter++;
	353	}
	354
	355
54841ab5	356	int do_inctest(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
8d3efe4e	357	{
049216f0	358	ulong *incin;
8d3efe4e SR	359	int i;
8d3efe4e SR	360
049216f0	361	incin = (ulong *)0xf0300040;
8d3efe4e SR	362
	363	/*
	364	* Clear inc counter
	365	*/
049216f0 MF	366	out_be32((void *)&incin[0], 0);
	367	out_be32((void *)&incin[1], 0);
	368	out_be32((void *)&incin[2], 0);
	369	out_be32((void *)&incin[3], 0);
8d3efe4e	370
049216f0	371	incin = (ulong *)0xf0300050;
8d3efe4e SR	372
	373	/*
	374	* Inc a little
	375	*/
	376	for (i=0; i<10000; i++) {
	377	switch (i & 0x03) {
	378	case 0:
049216f0	379	out_8(DIGEN, 0x02);
8d3efe4e SR	380	break;
8d3efe4e SR	381	case 1:
049216f0	382	out_8(DIGEN, 0x03);
8d3efe4e SR	383	break;
8d3efe4e SR	384	case 2:
049216f0	385	out_8(DIGEN, 0x01);
8d3efe4e SR	386	break;
8d3efe4e SR	387	case 3:
049216f0	388	out_8(DIGEN, 0x00);
8d3efe4e SR	389	break;
	390	}
	391	udelay(10);
	392	}
	393
049216f0 MF	394	printf("Inc 0 = %d\n", in_be32((void *)&incin[0]));
	395	printf("Inc 1 = %d\n", in_be32((void *)&incin[1]));
	396	printf("Inc 2 = %d\n", in_be32((void *)&incin[2]));
	397	printf("Inc 3 = %d\n", in_be32((void *)&incin[3]));
8d3efe4e	398
049216f0 MF	399	out_be16((void )0xf03000e0, 0x0c80-1); / set counter */
	400	out_be16((void *)0xf03000ec,
	401	in_be16((void )0xf03000ec) \| 0x0800); / enable int */
8d3efe4e SR	402	irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL);
	403	printf("counter=%d\n", counter);
	404
	405	return 0;
	406	}
	407	U_BOOT_CMD(
	408	inctest, 3, 1, do_inctest,
2fb2604d	409	"Test incremental encoder inputs",
a89c33db WD	410	""
a89c33db WD	411	);
8d3efe4e	412	#endif