[people/ms/u-boot.git] / board / esd / ash405 / ash405.c

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>

/* ------------------------------------------------------------------------- */

#if 0
#define FPGA_DEBUG
#endif

extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);

/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
{
#include "fpgadata.c"
};

/*
 * include common fpga code (for esd boards)
 */
#include "../common/fpga.c"


/* Prototypes */
int gunzip(void *, int, unsigned char *, int *);


int board_pre_init (void)
{
	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	 */
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
	mtdcr(uicer, 0x00000000);       /* disable all ints */
	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
	mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */

	/*
	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	 */
	mtebc (epcr, 0xa8400000); /* ebc always driven */

	return 0;
}


/* ------------------------------------------------------------------------- */

int misc_init_f (void)
{
	return 0;  /* dummy implementation */
}


int misc_init_r (void)
{
	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
	volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
	volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4);
	unsigned char *dst;
	ulong len = sizeof(fpgadata);
	int status;
	int index;
	int i;

	dst = malloc(CFG_FPGA_MAX_SIZE);
	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
		printf ("GUNZIP ERROR - must RESET board to recover\n");
		do_reset (NULL, 0, 0, NULL);
	}

	status = fpga_boot(dst, len);
	if (status != 0) {
		printf("\nFPGA: Booting failed ");
		switch (status) {
		case ERROR_FPGA_PRG_INIT_LOW:
			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_INIT_HIGH:
			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_DONE:
			printf("(Timeout: DONE not high after programming FPGA)\n ");
			break;
		}

		/* display infos on fpgaimage */
		index = 15;
		for (i=0; i<4; i++) {
			len = dst[index];
			printf("FPGA: %s\n", &(dst[index+1]));
			index += len+3;
		}
		putc ('\n');
		/* delayed reboot */
		for (i=20; i>0; i--) {
			printf("Rebooting in %2d seconds \r",i);
			for (index=0;index<1000;index++)
				udelay(1000);
		}
		putc ('\n');
		do_reset(NULL, 0, 0, NULL);
	}

	puts("FPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i=0; i<4; i++) {
		len = dst[index];
		printf("%s ", &(dst[index+1]));
		index += len+3;
	}
	putc ('\n');

	free(dst);

	/*
	 * Reset FPGA via FPGA_DATA pin
	 */
	SET_FPGA(FPGA_PRG | FPGA_CLK);
	udelay(1000); /* wait 1ms */
	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
	udelay(1000); /* wait 1ms */

	/*
	 * Reset external DUARTs
	 */
	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
	udelay(10); /* wait 10us */
	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
	udelay(1000); /* wait 1ms */

	/*
	 * Set NAND-FLASH GPIO signals to default
	 */
	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);

	/*
	 * Enable interrupts in exar duart mcr[3]
	 */
	*duart0_mcr = 0x08;
	*duart1_mcr = 0x08;
	*duart2_mcr = 0x08;
	*duart3_mcr = 0x08;

	return (0);
}


/*
 * Check Board Identity:
 */

int checkboard (void)
{
	unsigned char str[64];
	int i = getenv_r ("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming ASH405");
	} else {
		puts(str);
	}

	putc ('\n');

	return 0;
}

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
	unsigned long val;

	mtdcr(memcfga, mem_mb0cf);
	val = mfdcr(memcfgd);

#if 0
	printf("\nmb0cf=%x\n", val); /* test-only */
	printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif

	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}

/* ------------------------------------------------------------------------- */

int testdram (void)
{
	/* TODO: XXX XXX XXX */
	printf ("test: 16 MB - ok\n");

	return (0);
}

/* ------------------------------------------------------------------------- */

#if (CONFIG_COMMANDS & CFG_CMD_NAND)

void nand_init(void)
{
	unsigned long totlen = nand_probe(CFG_NAND_BASE);

	printf ("%4lu MB\n", totlen >> 20);
}
#endif
Commit	Line	Data
c93f7096 SR	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <command.h>
c93f7096 SR	27	#include <malloc.h>
	28
	29	/* ------------------------------------------------------------------------- */
	30
	31	#if 0
	32	#define FPGA_DEBUG
	33	#endif
	34
8bde7f77 WD	35	extern int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[]);
8bde7f77 WD	36
c93f7096 SR	37	/* fpga configuration data - gzip compressed and generated by bin2c */
	38	const unsigned char fpgadata[] =
	39	{
	40	#include "fpgadata.c"
	41	};
	42
	43	/*
	44	* include common fpga code (for esd boards)
	45	*/
	46	#include "../common/fpga.c"
	47
	48
	49	/* Prototypes */
	50	int gunzip(void , int, unsigned char , int *);
	51
	52
	53	int board_pre_init (void)
	54	{
	55	/*
	56	* IRQ 0-15 405GP internally generated; active high; level sensitive
	57	* IRQ 16 405GP internally generated; active low; level sensitive
	58	* IRQ 17-24 RESERVED
	59	* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	60	* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	61	* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	62	* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	63	* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	64	* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	65	* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	66	*/
	67	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	68	mtdcr(uicer, 0x00000000); /* disable all ints */
	69	mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
5b8b6525	70	mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */
c93f7096 SR	71	mtdcr(uictr, 0x10000000); /* set int trigger levels */
	72	mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
	73	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	74
	75	/*
	76	* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	77	*/
	78	mtebc (epcr, 0xa8400000); /* ebc always driven */
	79
	80	return 0;
	81	}
	82
	83
	84	/* ------------------------------------------------------------------------- */
	85
	86	int misc_init_f (void)
	87	{
	88	return 0; /* dummy implementation */
	89	}
	90
	91
	92	int misc_init_r (void)
	93	{
	94	volatile unsigned char duart0_mcr = (unsigned char )((ulong)DUART0_BA + 4);
	95	volatile unsigned char duart1_mcr = (unsigned char )((ulong)DUART1_BA + 4);
	96	volatile unsigned char duart2_mcr = (unsigned char )((ulong)DUART2_BA + 4);
	97	volatile unsigned char duart3_mcr = (unsigned char )((ulong)DUART3_BA + 4);
	98	unsigned char *dst;
	99	ulong len = sizeof(fpgadata);
	100	int status;
	101	int index;
	102	int i;
	103
	104	dst = malloc(CFG_FPGA_MAX_SIZE);
	105	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar )fpgadata, (int )&len) != 0) {
	106	printf ("GUNZIP ERROR - must RESET board to recover\n");
	107	do_reset (NULL, 0, 0, NULL);
	108	}
	109
	110	status = fpga_boot(dst, len);
	111	if (status != 0) {
	112	printf("\nFPGA: Booting failed ");
	113	switch (status) {
	114	case ERROR_FPGA_PRG_INIT_LOW:
	115	printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
	116	break;
	117	case ERROR_FPGA_PRG_INIT_HIGH:
	118	printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
	119	break;
	120	case ERROR_FPGA_PRG_DONE:
	121	printf("(Timeout: DONE not high after programming FPGA)\n ");
	122	break;
	123	}
	124
	125	/* display infos on fpgaimage */
	126	index = 15;
	127	for (i=0; i<4; i++) {
	128	len = dst[index];
	129	printf("FPGA: %s\n", &(dst[index+1]));
	130	index += len+3;
	131	}
	132	putc ('\n');
	133	/* delayed reboot */
	134	for (i=20; i>0; i--) {
135	printf("Rebooting in %2d seconds \r",i);
136	for (index=0;index<1000;index++)
137	udelay(1000);
138	}
139	putc ('\n');
140	do_reset(NULL, 0, 0, NULL);
141	}
142
143	puts("FPGA: ");
144
145	/* display infos on fpgaimage */
146	index = 15;
147	for (i=0; i<4; i++) {
148	len = dst[index];
149	printf("%s ", &(dst[index+1]));
150	index += len+3;
151	}
152	putc ('\n');
153
154	free(dst);
155
156	/*
157	* Reset FPGA via FPGA_DATA pin
158	*/
159	SET_FPGA(FPGA_PRG \| FPGA_CLK);
160	udelay(1000); /* wait 1ms */
161	SET_FPGA(FPGA_PRG \| FPGA_CLK \| FPGA_DATA);
162	udelay(1000); /* wait 1ms */
163
164	/*
165	* Reset external DUARTs
166	*/
167	out32(GPIO0_OR, in32(GPIO0_OR) \| CFG_DUART_RST); /* set reset to high */
168	udelay(10); /* wait 10us */
169	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
170	udelay(1000); /* wait 1ms */
171
172	/*
173	* Set NAND-FLASH GPIO signals to default
174	*/
175	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE \| CFG_NAND_ALE));
176	out32(GPIO0_OR, in32(GPIO0_OR) \| CFG_NAND_CE);
177
178	/*
179	* Enable interrupts in exar duart mcr[3]
180	*/
181	*duart0_mcr = 0x08;
182	*duart1_mcr = 0x08;
183	*duart2_mcr = 0x08;
184	*duart3_mcr = 0x08;
185
186	return (0);
187	}
188
189
190	/*
191	* Check Board Identity:
192	*/
193
194	int checkboard (void)
195	{
196	unsigned char str[64];
197	int i = getenv_r ("serial#", str, sizeof(str));
198
199	puts ("Board: ");
200
201	if (i == -1) {
202	puts ("### No HW ID - assuming ASH405");
203	} else {
204	puts(str);
205	}
206
207	putc ('\n');
208
209	return 0;
210	}
211
212	/* ------------------------------------------------------------------------- */
213
214	long int initdram (int board_type)
215	{
216	unsigned long val;
217
218	mtdcr(memcfga, mem_mb0cf);
219	val = mfdcr(memcfgd);
220
221	#if 0
222	printf("\nmb0cf=%x\n", val); /* test-only */
223	printf("strap=%x\n", mfdcr(strap)); /* test-only */
224	#endif
225
226	return (410241024 << ((val & 0x000e0000) >> 17));
227	}
228
229	/* ------------------------------------------------------------------------- */
230
231	int testdram (void)
232	{
233	/* TODO: XXX XXX XXX */
234	printf ("test: 16 MB - ok\n");
235
236	return (0);
237	}
238
239	/* ------------------------------------------------------------------------- */
240
241	#if (CONFIG_COMMANDS & CFG_CMD_NAND)
e118e233	242
c93f7096 SR	243	void nand_init(void)
c93f7096 SR	244	{
a43278a4 WD	245	unsigned long totlen = nand_probe(CFG_NAND_BASE);
	246
	247	printf ("%4lu MB\n", totlen >> 20);
c93f7096 SR	248	}
c93f7096 SR	249	#endif