projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| e09f7ab5 MF |
1 | /* |
| 2 | * (C) Copyright 2007 | |
| 3 | * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com | |
| 4 | * | |
| 1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| e09f7ab5 MF |
6 | */ |
| 7 | ||
| 8 | #include <common.h> | |
| 9 | ||
| b706d635 | 10 | #if defined(CONFIG_CMD_NAND) |
| e09f7ab5 MF |
11 | #include <asm/io.h> |
| 12 | #include <nand.h> | |
| 13 | ||
| 14 | /* | |
| 15 | * hardware specific access to control-lines | |
| 16 | */ | |
| cfa460ad | 17 | static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
| e09f7ab5 | 18 | { |
| 17cb4b8f | 19 | struct nand_chip *this = mtd_to_nand(mtd); |
| 5e1dae5c | 20 | if (ctrl & NAND_CTRL_CHANGE) { |
| cfa460ad | 21 | if ( ctrl & NAND_CLE ) |
| 6d0f6bcf | 22 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE); |
| cfa460ad | 23 | else |
| 6d0f6bcf | 24 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE); |
| cfa460ad | 25 | if ( ctrl & NAND_ALE ) |
| 6d0f6bcf | 26 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE); |
| cfa460ad | 27 | else |
| 6d0f6bcf | 28 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE); |
| cfa460ad | 29 | if ( ctrl & NAND_NCE ) |
| 6d0f6bcf | 30 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE); |
| cfa460ad | 31 | else |
| 6d0f6bcf | 32 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE); |
| e09f7ab5 | 33 | } |
| cfa460ad | 34 | |
| 5e1dae5c | 35 | if (cmd != NAND_CMD_NONE) |
| cfa460ad | 36 | writeb(cmd, this->IO_ADDR_W); |
| e09f7ab5 MF |
37 | } |
| 38 | ||
| 39 | ||
| 40 | /* | |
| 41 | * read device ready pin | |
| 42 | */ | |
| 43 | static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo) | |
| 44 | { | |
| 6d0f6bcf | 45 | if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY) |
| e09f7ab5 MF |
46 | return 1; |
| 47 | return 0; | |
| 48 | } | |
| 49 | ||
| 50 | ||
| 51 | int board_nand_init(struct nand_chip *nand) | |
| 52 | { | |
| 53 | /* | |
| 54 | * Set NAND-FLASH GPIO signals to defaults | |
| 55 | */ | |
| 6d0f6bcf JCPV |
56 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); |
| 57 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE); | |
| e09f7ab5 MF |
58 | |
| 59 | /* | |
| 60 | * Initialize nand_chip structure | |
| 61 | */ | |
| cfa460ad | 62 | nand->cmd_ctrl = esd405ep_nand_hwcontrol; |
| e09f7ab5 | 63 | nand->dev_ready = esd405ep_nand_device_ready; |
| cfa460ad | 64 | nand->ecc.mode = NAND_ECC_SOFT; |
| e09f7ab5 MF |
65 | nand->chip_delay = NAND_BIG_DELAY_US; |
| 66 | nand->options = NAND_SAMSUNG_LP_OPTIONS; | |
| 67 | return 0; | |
| 68 | } | |
| b706d635 | 69 | #endif |