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Commit | Line | Data |
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0621f6f9 | 1 | /* |
f3ee2585 | 2 | * Copyright (c) 2000,2001 Epson Research and Development, Inc. |
0621f6f9 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
0621f6f9 | 5 | * |
f3ee2585 MF |
6 | * Generic Header information generated by 13704CFG.EXE (Build 10) |
7 | * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz) | |
0621f6f9 SR |
8 | */ |
9 | ||
10 | static S1D_REGS regs_13705_320_240_8bpp[] = | |
11 | { | |
12 | { 0x00, 0x00 }, /* Revision Code Register */ | |
13 | { 0x01, 0x23 }, /* Mode Register 0 Register */ | |
14 | { 0x02, 0xE0 }, /* Mode Register 1 Register */ | |
15 | { 0x03, 0x03 }, /* Mode Register 2 Register - bit7 is LUT bypass */ | |
16 | { 0x04, 0x27 }, /* Horizontal Panel Size Register */ | |
17 | { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */ | |
18 | { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */ | |
19 | { 0x07, 0x00 }, /* FPLINE Start Position Register */ | |
20 | { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */ | |
21 | { 0x09, 0x01 }, /* FPFRAME Start Position Register */ | |
22 | { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */ | |
23 | { 0x0B, 0x00 }, /* MOD Rate Register */ | |
24 | { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */ | |
25 | { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */ | |
26 | { 0x0E, 0x00 }, /* Not Used */ | |
27 | { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */ | |
28 | { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */ | |
29 | { 0x11, 0x00 }, /* Not Used */ | |
30 | { 0x12, 0x00 }, /* Memory Address Offset Register */ | |
31 | { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */ | |
32 | { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */ | |
33 | { 0x15, 0x00 }, /* Look-Up Table Address Register */ | |
34 | { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */ | |
35 | { 0x17, 0x00 }, /* Look-Up Table Data Register */ | |
36 | { 0x18, 0x01 }, /* GPIO Configuration Control Register */ | |
37 | { 0x19, 0x01 }, /* GPIO Status/Control Register */ | |
38 | { 0x1A, 0x00 }, /* Scratch Pad Register */ | |
39 | { 0x1B, 0x00 }, /* SwivelView Mode Register */ | |
40 | { 0x1C, 0xFF }, /* Line Byte Count Register */ | |
41 | { 0x1D, 0x00 }, /* Not Used */ | |
42 | { 0x1E, 0x00 }, /* Not Used */ | |
43 | { 0x1F, 0x00 }, /* Not Used */ | |
44 | }; |