projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0621f6f9 | 1 | /* |
| f3ee2585 | 2 | * Copyright (c) 2000,2001 Epson Research and Development, Inc. |
| 0621f6f9 | 3 | * |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| f3ee2585 MF |
5 | * |
| 6 | * File generated by S1D13806CFG.EXE | |
| 0621f6f9 SR |
7 | * Panel: (active) 320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz) |
| 8 | * Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz) | |
| 0621f6f9 SR |
9 | */ |
| 10 | ||
| 11 | static S1D_REGS regs_13806_320_240_4bpp[] = | |
| 12 | { | |
| 13 | {0x0001,0x00}, /* Miscellaneous Register */ | |
| 14 | {0x01FC,0x00}, /* Display Mode Register */ | |
| 15 | {0x0004,0x08}, /* General IO Pins Configuration Register 0 */ | |
| 16 | {0x0005,0x08}, /* General IO Pins Configuration Register 1 */ | |
| 17 | {0x0008,0x08}, /* General IO Pins Control Register 0 */ | |
| 18 | {0x0009,0x00}, /* General IO Pins Control Register 1 */ | |
| 19 | {0x0010,0x00}, /* Memory Clock Configuration Register */ | |
| 20 | {0x0014,0x32}, /* LCD Pixel Clock Configuration Register */ | |
| 21 | {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */ | |
| 22 | {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ | |
| 23 | {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ | |
| 24 | {0x0021,0x03}, /* DRAM Refresh Rate Register */ | |
| 25 | {0x002A,0x00}, /* DRAM Timings Control Register 0 */ | |
| 26 | {0x002B,0x01}, /* DRAM Timings Control Register 1 */ | |
| 27 | {0x0020,0x80}, /* Memory Configuration Register */ | |
| 28 | {0x0030,0x00}, /* Panel Type Register */ | |
| 29 | {0x0031,0x00}, /* MOD Rate Register */ | |
| 30 | {0x0032,0x27}, /* LCD Horizontal Display Width Register */ | |
| 31 | {0x0034,0x03}, /* LCD Horizontal Non-Display Period Register */ | |
| 32 | {0x0035,0x01}, /* TFT FPLINE Start Position Register */ | |
| 33 | {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ | |
| 34 | {0x0038,0xEF}, /* LCD Vertical Display Height Register 0 */ | |
| 35 | {0x0039,0x00}, /* LCD Vertical Display Height Register 1 */ | |
| 36 | {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ | |
| 37 | {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ | |
| 38 | {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ | |
| 39 | {0x0040,0x02}, /* LCD Display Mode Register */ | |
| 40 | {0x0041,0x00}, /* LCD Miscellaneous Register */ | |
| 41 | {0x0042,0x00}, /* LCD Display Start Address Register 0 */ | |
| 42 | {0x0043,0x00}, /* LCD Display Start Address Register 1 */ | |
| 43 | {0x0044,0x00}, /* LCD Display Start Address Register 2 */ | |
| 44 | {0x0046,0x50}, /* LCD Memory Address Offset Register 0 */ | |
| 45 | {0x0047,0x00}, /* LCD Memory Address Offset Register 1 */ | |
| 46 | {0x0048,0x00}, /* LCD Pixel Panning Register */ | |
| 47 | {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ | |
| 48 | {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ | |
| 49 | {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ | |
| 50 | {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ | |
| 51 | {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ | |
| 52 | {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ | |
| 53 | {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ | |
| 54 | {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ | |
| 55 | {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ | |
| 56 | {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ | |
| 57 | {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ | |
| 58 | {0x005B,0x10}, /* TV Output Control Register */ | |
| 59 | {0x0060,0x03}, /* CRT/TV Display Mode Register */ | |
| 60 | {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ | |
| 61 | {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ | |
| 62 | {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ | |
| 63 | {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ | |
| 64 | {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ | |
| 65 | {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ | |
| 66 | {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ | |
| 67 | {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ | |
| 68 | {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ | |
| 69 | {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ | |
| 70 | {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ | |
| 71 | {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ | |
| 72 | {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ | |
| 73 | {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ | |
| 74 | {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ | |
| 75 | {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ | |
| 76 | {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ | |
| 77 | {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ | |
| 78 | {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ | |
| 79 | {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ | |
| 80 | {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ | |
| 81 | {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ | |
| 82 | {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ | |
| 83 | {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ | |
| 84 | {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ | |
| 85 | {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ | |
| 86 | {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ | |
| 87 | {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ | |
| 88 | {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ | |
| 89 | {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ | |
| 90 | {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ | |
| 91 | {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ | |
| 92 | {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ | |
| 93 | {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ | |
| 94 | {0x0100,0x00}, /* BitBlt Control Register 0 */ | |
| 95 | {0x0101,0x00}, /* BitBlt Control Register 1 */ | |
| 96 | {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ | |
| 97 | {0x0103,0x00}, /* BitBlt Operation Register */ | |
| 98 | {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ | |
| 99 | {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ | |
| 100 | {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ | |
| 101 | {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ | |
| 102 | {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ | |
| 103 | {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ | |
| 104 | {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ | |
| 105 | {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ | |
| 106 | {0x0110,0x00}, /* BitBlt Width Register 0 */ | |
| 107 | {0x0111,0x00}, /* BitBlt Width Register 1 */ | |
| 108 | {0x0112,0x00}, /* BitBlt Height Register 0 */ | |
| 109 | {0x0113,0x00}, /* BitBlt Height Register 1 */ | |
| 110 | {0x0114,0x00}, /* BitBlt Background Color Register 0 */ | |
| 111 | {0x0115,0x00}, /* BitBlt Background Color Register 1 */ | |
| 112 | {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ | |
| 113 | {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ | |
| 114 | {0x01E0,0x00}, /* Look-Up Table Mode Register */ | |
| 115 | {0x01E2,0x00}, /* Look-Up Table Address Register */ | |
| 116 | {0x01F0,0x10}, /* Power Save Configuration Register */ | |
| 117 | {0x01F1,0x00}, /* Power Save Status Register */ | |
| 118 | {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ | |
| 119 | {0x01FC,0x01}, /* Display Mode Register */ | |
| 120 | }; |