[people/ms/u-boot.git] / board / esd / cpci2dp / cpci2dp.c

/*
 * (C) Copyright 2005
 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f (void)
{
	unsigned long CPC0_CR0Reg;

	/*
	 * Setup GPIO pins
	 */
	CPC0_CR0Reg = mfdcr(CPC0_CR0);
	mtdcr(CPC0_CR0, CPC0_CR0Reg |
	      ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED |
		CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));

	/* set output pins to high */
	out_be32((void *)GPIO0_OR,  CONFIG_SYS_EEPROM_WP);
	/* setup for output (LED=off) */
	out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) unused
	 */
	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical*/
	mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */

	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority*/
	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */

	return 0;
}

int misc_init_r (void)
{
	unsigned long CPC0_CR0Reg;

	/* adjust flash start and offset */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/*
	 * Select cts (and not dsr) on uart1
	 */
	CPC0_CR0Reg = mfdcr(CPC0_CR0);
	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);

	return (0);
}


/*
 * Check Board Identity:
 */
int checkboard (void)
{
	char str[64];
	int i = getenv_f("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming CPCI2DP");
	} else {
		puts(str);
	}

	printf(" (Ver 1.0)");

	putc ('\n');

	return 0;
}

#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr>  I2C address of EEPROM device to enable.
 *	   <state>     -1: deliver current state
 *		       0: disable write
 *		       1: enable write
 *  Returns:	       -1: wrong device address
 *			0: dis-/en- able done
 *		     0/1: current state if <state> was -1.
 */
int eeprom_write_enable (unsigned dev_addr, int state) {
	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
		return -1;
	} else {
		switch (state) {
		case 1:
			/* Enable write access, clear bit GPIO_SINT2. */
			out_be32((void *)GPIO0_OR,
				 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
			state = 0;
			break;
		case 0:
			/* Disable write access, set bit GPIO_SINT2. */
			out_be32((void *)GPIO0_OR,
				 in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
			state = 0;
			break;
		default:
			/* Read current status back. */
			state = (0 == (in_be32((void *)GPIO0_OR) &
				       CONFIG_SYS_EEPROM_WP));
			break;
		}
	}
	return state;
}
#endif

#if defined(CONFIG_SYS_EEPROM_WREN)
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	int query = argc == 1;
	int state = 0;

	if (query) {
		/* Query write access state. */
		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
		if (state < 0) {
			puts ("Query of write access state failed.\n");
		} else {
			printf ("Write access for device 0x%0x is %sabled.\n",
				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
			state = 0;
		}
	} else {
		if ('0' == argv[1][0]) {
			/* Disable write access. */
			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
		} else {
			/* Enable write access. */
			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
		}
		if (state < 0) {
			puts ("Setup of write access state failed.\n");
		}
	}

	return state;
}

U_BOOT_CMD(
	eepwren,	2,	0,	do_eep_wren,
	"Enable / disable / query EEPROM write access",
	""
);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
Commit	Line	Data
7644f16f SR	1	/*
	2	* (C) Copyright 2005
	3	* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
7644f16f SR	6	*/
	7
	8	#include <common.h>
	9	#include <asm/processor.h>
049216f0	10	#include <asm/io.h>
7644f16f SR	11	#include <command.h>
	12	#include <malloc.h>
	13
d87080b7 WD	14	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	15
7644f16f SR	16	int board_early_init_f (void)
7644f16f SR	17	{
d1c3b275	18	unsigned long CPC0_CR0Reg;
7644f16f SR	19
7644f16f SR	20	/*
2076d0a1	21	* Setup GPIO pins
7644f16f	22	*/
d1c3b275 SR	23	CPC0_CR0Reg = mfdcr(CPC0_CR0);
d1c3b275 SR	24	mtdcr(CPC0_CR0, CPC0_CR0Reg \|
049216f0 MF	25	((CONFIG_SYS_EEPROM_WP \| CONFIG_SYS_PB_LED \|
049216f0 MF	26	CONFIG_SYS_SELF_RST \| CONFIG_SYS_INTA_FAKE) << 5));
7644f16f	27
bfc81252	28	/* set output pins to high */
049216f0	29	out_be32((void *)GPIO0_OR, CONFIG_SYS_EEPROM_WP);
bfc81252	30	/* setup for output (LED=off) */
049216f0	31	out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP \| CONFIG_SYS_PB_LED);
7644f16f SR	32
	33	/*
	34	* IRQ 0-15 405GP internally generated; active high; level sensitive
	35	* IRQ 16 405GP internally generated; active low; level sensitive
	36	* IRQ 17-24 RESERVED
	37	* IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
	38	* IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
	39	* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
	40	* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
	41	* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
	42	* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
	43	* IRQ 31 (EXT IRQ 6) unused
	44	*/
952e7760 SR	45	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
	46	mtdcr(UIC0ER, 0x00000000); /* disable all ints */
	47	mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
	48	mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
	49
	50	mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
	51	mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
	52	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
7644f16f SR	53
	54	return 0;
	55	}
	56
7644f16f SR	57	int misc_init_r (void)
7644f16f SR	58	{
d1c3b275	59	unsigned long CPC0_CR0Reg;
7644f16f SR	60
	61	/* adjust flash start and offset */
	62	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	63	gd->bd->bi_flashoffset = 0;
	64
	65	/*
	66	* Select cts (and not dsr) on uart1
	67	*/
d1c3b275 SR	68	CPC0_CR0Reg = mfdcr(CPC0_CR0);
d1c3b275 SR	69	mtdcr(CPC0_CR0, CPC0_CR0Reg \| 0x00001000);
7644f16f SR	70
	71	return (0);
	72	}
	73
	74
	75	/*
	76	* Check Board Identity:
	77	*/
	78	int checkboard (void)
	79	{
77ddac94	80	char str[64];
cdb74977	81	int i = getenv_f("serial#", str, sizeof(str));
7644f16f SR	82
	83	puts ("Board: ");
	84
	85	if (i == -1) {
	86	puts ("### No HW ID - assuming CPCI2DP");
	87	} else {
	88	puts(str);
	89	}
	90
	91	printf(" (Ver 1.0)");
	92
	93	putc ('\n');
	94
	95	return 0;
	96	}
	97
6d0f6bcf	98	#if defined(CONFIG_SYS_EEPROM_WREN)
7644f16f	99	/* Input: <dev_addr> I2C address of EEPROM device to enable.
f013dacf WD	100	* <state> -1: deliver current state
f013dacf WD	101	* 0: disable write
7644f16f	102	* 1: enable write
f013dacf WD	103	* Returns: -1: wrong device address
f013dacf WD	104	* 0: dis-/en- able done
7644f16f SR	105	* 0/1: current state if <state> was -1.
	106	*/
	107	int eeprom_write_enable (unsigned dev_addr, int state) {
6d0f6bcf	108	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
7644f16f	109	return -1;
f013dacf	110	} else {
7644f16f SR	111	switch (state) {
	112	case 1:
	113	/* Enable write access, clear bit GPIO_SINT2. */
049216f0 MF	114	out_be32((void *)GPIO0_OR,
049216f0 MF	115	in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
7644f16f SR	116	state = 0;
	117	break;
	118	case 0:
	119	/* Disable write access, set bit GPIO_SINT2. */
049216f0 MF	120	out_be32((void *)GPIO0_OR,
049216f0 MF	121	in_be32((void *)GPIO0_OR) \| CONFIG_SYS_EEPROM_WP);
7644f16f SR	122	state = 0;
	123	break;
	124	default:
	125	/* Read current status back. */
049216f0 MF	126	state = (0 == (in_be32((void *)GPIO0_OR) &
049216f0 MF	127	CONFIG_SYS_EEPROM_WP));
7644f16f SR	128	break;
	129	}
	130	}
	131	return state;
	132	}
	133	#endif
	134
6d0f6bcf	135	#if defined(CONFIG_SYS_EEPROM_WREN)
54841ab5	136	int do_eep_wren (cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
7644f16f SR	137	{
	138	int query = argc == 1;
	139	int state = 0;
	140
	141	if (query) {
	142	/* Query write access state. */
6d0f6bcf	143	state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
7644f16f SR	144	if (state < 0) {
7644f16f SR	145	puts ("Query of write access state failed.\n");
f013dacf	146	} else {
7644f16f	147	printf ("Write access for device 0x%0x is %sabled.\n",
6d0f6bcf	148	CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
7644f16f SR	149	state = 0;
7644f16f SR	150	}
f013dacf	151	} else {
7644f16f SR	152	if ('0' == argv[1][0]) {
7644f16f SR	153	/* Disable write access. */
6d0f6bcf	154	state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
f013dacf	155	} else {
7644f16f	156	/* Enable write access. */
6d0f6bcf	157	state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
7644f16f SR	158	}
	159	if (state < 0) {
	160	puts ("Setup of write access state failed.\n");
	161	}
	162	}
	163
	164	return state;
	165	}
	166
	167	U_BOOT_CMD(
2076d0a1	168	eepwren, 2, 0, do_eep_wren,
2fb2604d	169	"Enable / disable / query EEPROM write access",
a89c33db WD	170	""
a89c33db WD	171	);
6d0f6bcf	172	#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */