[people/ms/u-boot.git] / board / esd / cpci2dp / cpci2dp.c

/*
 * (C) Copyright 2005
 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>

int board_early_init_f (void)
{
	unsigned long cntrl0Reg;

	/*
	 * Setup GPIO pins
	 */
	cntrl0Reg = mfdcr(cntrl0);
	mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5));

	/* set output pins to high */
	out32(GPIO0_OR,  CFG_EEPROM_WP);
	/* setup for output (LED=off) */
	out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED);

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) unused
	 */
	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
	mtdcr(uicer, 0x00000000);	/* disable all ints */
	mtdcr(uiccr, 0x00000000);	/* set all to be non-critical*/
	mtdcr(uicpr, 0xFFFFFF81);	/* set int polarities */

	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority*/
	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */

	return 0;
}


int misc_init_f (void)
{
	return 0;  /* dummy implementation */
}


int misc_init_r (void)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned long cntrl0Reg;

	/* adjust flash start and offset */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/*
	 * Select cts (and not dsr) on uart1
	 */
	cntrl0Reg = mfdcr(cntrl0);
	mtdcr(cntrl0, cntrl0Reg | 0x00001000);

	return (0);
}


/*
 * Check Board Identity:
 */
int checkboard (void)
{
	char str[64];
	int i = getenv_r ("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming CPCI2DP");
	} else {
		puts(str);
	}

	printf(" (Ver 1.0)");

	putc ('\n');

	return 0;
}

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
	unsigned long val;

	mtdcr(memcfga, mem_mb0cf);
	val = mfdcr(memcfgd);

	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}

/* ------------------------------------------------------------------------- */

#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr>  I2C address of EEPROM device to enable.
 *	   <state>     -1: deliver current state
 *		       0: disable write
 *		       1: enable write
 *  Returns:	       -1: wrong device address
 *			0: dis-/en- able done
 *		     0/1: current state if <state> was -1.
 */
int eeprom_write_enable (unsigned dev_addr, int state) {
	if (CFG_I2C_EEPROM_ADDR != dev_addr) {
		return -1;
	} else {
		switch (state) {
		case 1:
			/* Enable write access, clear bit GPIO_SINT2. */
			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
			state = 0;
			break;
		case 0:
			/* Disable write access, set bit GPIO_SINT2. */
			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
			state = 0;
			break;
		default:
			/* Read current status back. */
			state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
			break;
		}
	}
	return state;
}
#endif

#if defined(CFG_EEPROM_WREN)
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	int query = argc == 1;
	int state = 0;

	if (query) {
		/* Query write access state. */
		state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
		if (state < 0) {
			puts ("Query of write access state failed.\n");
		} else {
			printf ("Write access for device 0x%0x is %sabled.\n",
				CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
			state = 0;
		}
	} else {
		if ('0' == argv[1][0]) {
			/* Disable write access. */
			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
		} else {
			/* Enable write access. */
			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
		}
		if (state < 0) {
			puts ("Setup of write access state failed.\n");
		}
	}

	return state;
}

U_BOOT_CMD(
	eepwren,	2,	0,	do_eep_wren,
	"eepwren - Enable / disable / query EEPROM write access\n",
	NULL
	);
#endif /* #if defined(CFG_EEPROM_WREN) */
Commit	Line	Data
7644f16f SR	1	/*
	2	* (C) Copyright 2005
	3	* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
f013dacf	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7644f16f SR	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <command.h>
	27	#include <malloc.h>
	28
	29	int board_early_init_f (void)
	30	{
	31	unsigned long cntrl0Reg;
	32
	33	/*
2076d0a1	34	* Setup GPIO pins
7644f16f SR	35	*/
7644f16f SR	36	cntrl0Reg = mfdcr(cntrl0);
2076d0a1	37	mtdcr(cntrl0, cntrl0Reg \| ((CFG_EEPROM_WP \| CFG_PB_LED \| CFG_SELF_RST \| CFG_INTA_FAKE) << 5));
7644f16f	38
bfc81252	39	/* set output pins to high */
2076d0a1	40	out32(GPIO0_OR, CFG_EEPROM_WP);
bfc81252	41	/* setup for output (LED=off) */
2076d0a1	42	out32(GPIO0_TCR, CFG_EEPROM_WP \| CFG_PB_LED);
7644f16f SR	43
	44	/*
	45	* IRQ 0-15 405GP internally generated; active high; level sensitive
	46	* IRQ 16 405GP internally generated; active low; level sensitive
	47	* IRQ 17-24 RESERVED
	48	* IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
	49	* IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
	50	* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
	51	* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
	52	* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
	53	* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
	54	* IRQ 31 (EXT IRQ 6) unused
	55	*/
f013dacf WD	56	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	57	mtdcr(uicer, 0x00000000); /* disable all ints */
	58	mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
	59	mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
7644f16f	60
f013dacf WD	61	mtdcr(uictr, 0x10000000); /* set int trigger levels */
	62	mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
	63	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
7644f16f SR	64
	65	return 0;
	66	}
	67
	68
	69	int misc_init_f (void)
	70	{
	71	return 0; /* dummy implementation */
	72	}
	73
	74
	75	int misc_init_r (void)
	76	{
	77	DECLARE_GLOBAL_DATA_PTR;
	78	unsigned long cntrl0Reg;
	79
	80	/* adjust flash start and offset */
	81	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	82	gd->bd->bi_flashoffset = 0;
	83
	84	/*
	85	* Select cts (and not dsr) on uart1
	86	*/
	87	cntrl0Reg = mfdcr(cntrl0);
	88	mtdcr(cntrl0, cntrl0Reg \| 0x00001000);
	89
	90	return (0);
	91	}
	92
	93
	94	/*
	95	* Check Board Identity:
	96	*/
	97	int checkboard (void)
	98	{
77ddac94	99	char str[64];
7644f16f SR	100	int i = getenv_r ("serial#", str, sizeof(str));
	101
	102	puts ("Board: ");
	103
	104	if (i == -1) {
	105	puts ("### No HW ID - assuming CPCI2DP");
	106	} else {
	107	puts(str);
	108	}
	109
	110	printf(" (Ver 1.0)");
	111
	112	putc ('\n');
	113
	114	return 0;
	115	}
	116
	117	/* ------------------------------------------------------------------------- */
	118
	119	long int initdram (int board_type)
	120	{
	121	unsigned long val;
	122
	123	mtdcr(memcfga, mem_mb0cf);
	124	val = mfdcr(memcfgd);
	125
	126	return (410241024 << ((val & 0x000e0000) >> 17));
	127	}
	128
	129	/* ------------------------------------------------------------------------- */
	130
7644f16f SR	131	#if defined(CFG_EEPROM_WREN)
7644f16f SR	132	/* Input: <dev_addr> I2C address of EEPROM device to enable.
f013dacf WD	133	* <state> -1: deliver current state
f013dacf WD	134	* 0: disable write
7644f16f	135	* 1: enable write
f013dacf WD	136	* Returns: -1: wrong device address
f013dacf WD	137	* 0: dis-/en- able done
7644f16f SR	138	* 0/1: current state if <state> was -1.
	139	*/
	140	int eeprom_write_enable (unsigned dev_addr, int state) {
	141	if (CFG_I2C_EEPROM_ADDR != dev_addr) {
	142	return -1;
f013dacf	143	} else {
7644f16f SR	144	switch (state) {
	145	case 1:
	146	/* Enable write access, clear bit GPIO_SINT2. */
	147	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
	148	state = 0;
	149	break;
	150	case 0:
	151	/* Disable write access, set bit GPIO_SINT2. */
	152	out32(GPIO0_OR, in32(GPIO0_OR) \| CFG_EEPROM_WP);
	153	state = 0;
	154	break;
	155	default:
	156	/* Read current status back. */
	157	state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
	158	break;
	159	}
	160	}
	161	return state;
	162	}
	163	#endif
	164
	165	#if defined(CFG_EEPROM_WREN)
	166	int do_eep_wren (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	167	{
	168	int query = argc == 1;
	169	int state = 0;
	170
	171	if (query) {
	172	/* Query write access state. */
	173	state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
	174	if (state < 0) {
	175	puts ("Query of write access state failed.\n");
f013dacf	176	} else {
7644f16f SR	177	printf ("Write access for device 0x%0x is %sabled.\n",
	178	CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
	179	state = 0;
	180	}
f013dacf	181	} else {
7644f16f SR	182	if ('0' == argv[1][0]) {
	183	/* Disable write access. */
	184	state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
f013dacf	185	} else {
7644f16f SR	186	/* Enable write access. */
	187	state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
	188	}
	189	if (state < 0) {
	190	puts ("Setup of write access state failed.\n");
	191	}
	192	}
	193
	194	return state;
	195	}
	196
	197	U_BOOT_CMD(
2076d0a1 SR	198	eepwren, 2, 0, do_eep_wren,
	199	"eepwren - Enable / disable / query EEPROM write access\n",
	200	NULL
	201	);
7644f16f	202	#endif /* #if defined(CFG_EEPROM_WREN) */