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Commit | Line | Data |
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c609719b | 1 | /* |
6f4474e8 | 2 | * (C) Copyright 2001-2003 |
c609719b WD |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b | 6 | */ |
c609719b | 7 | #include <common.h> |
600fe46f MF |
8 | #include <libfdt.h> |
9 | #include <fdt_support.h> | |
c609719b | 10 | #include <asm/processor.h> |
6f35c531 | 11 | #include <asm/io.h> |
c609719b | 12 | #include <command.h> |
c609719b | 13 | #include <malloc.h> |
87663b1c | 14 | #include <net.h> |
6f35c531 | 15 | #include <pci.h> |
c609719b | 16 | |
d87080b7 WD |
17 | DECLARE_GLOBAL_DATA_PTR; |
18 | ||
f6a1f490 MF |
19 | extern void __ft_board_setup(void *blob, bd_t *bd); |
20 | ||
21 | #undef FPGA_DEBUG | |
c609719b WD |
22 | |
23 | /* fpga configuration data - generated by bin2cc */ | |
24 | const unsigned char fpgadata[] = | |
25 | { | |
f6a1f490 MF |
26 | #if defined(CONFIG_CPCI405_VER2) |
27 | # if defined(CONFIG_CPCI405AB) | |
d4629c8c SR |
28 | # include "fpgadata_cpci405ab.c" |
29 | # else | |
30 | # include "fpgadata_cpci4052.c" | |
31 | # endif | |
c609719b WD |
32 | #else |
33 | # include "fpgadata_cpci405.c" | |
34 | #endif | |
35 | }; | |
36 | ||
37 | /* | |
38 | * include common fpga code (for esd boards) | |
39 | */ | |
40 | #include "../common/fpga.c" | |
87663b1c SR |
41 | #include "../common/auto_update.h" |
42 | ||
f6a1f490 | 43 | #if defined(CONFIG_CPCI405AB) |
87663b1c SR |
44 | au_image_t au_image[] = { |
45 | {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT}, | |
46 | {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR}, | |
47 | {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR}, | |
48 | {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, | |
49 | {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT}, | |
50 | }; | |
51 | #else | |
f6a1f490 | 52 | #if defined(CONFIG_CPCI405_VER2) |
87663b1c SR |
53 | au_image_t au_image[] = { |
54 | {"cpci4052/preinst.img", 0, -1, AU_SCRIPT}, | |
55 | {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR}, | |
56 | {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR}, | |
57 | {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE}, | |
58 | {"cpci4052/postinst.img", 0, 0, AU_SCRIPT}, | |
59 | }; | |
60 | #else | |
61 | au_image_t au_image[] = { | |
62 | {"cpci405/preinst.img", 0, -1, AU_SCRIPT}, | |
63 | {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR}, | |
64 | {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR}, | |
65 | {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE}, | |
66 | {"cpci405/postinst.img", 0, 0, AU_SCRIPT}, | |
67 | }; | |
68 | #endif | |
69 | #endif | |
70 | ||
71 | int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); | |
72 | ||
c609719b | 73 | /* Prototypes */ |
6f4474e8 | 74 | int cpci405_version(void); |
87663b1c | 75 | void lxt971_no_sleep(void); |
c609719b | 76 | |
f6a1f490 | 77 | int board_early_init_f(void) |
c609719b WD |
78 | { |
79 | #ifndef CONFIG_CPCI405_VER2 | |
80 | int index, len, i; | |
81 | int status; | |
82 | #endif | |
83 | ||
84 | #ifdef FPGA_DEBUG | |
c609719b | 85 | /* set up serial port with default baudrate */ |
f6a1f490 | 86 | (void)get_clocks(); |
c609719b | 87 | gd->baudrate = CONFIG_BAUDRATE; |
f6a1f490 | 88 | serial_init(); |
c609719b WD |
89 | console_init_f(); |
90 | #endif | |
91 | ||
92 | /* | |
f6a1f490 MF |
93 | * First pull fpga-prg pin low, |
94 | * to disable fpga logic (on version 2 board) | |
c609719b | 95 | */ |
049216f0 MF |
96 | out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */ |
97 | out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ | |
98 | out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ | |
99 | out_be32((void *)GPIO0_OR, 0); /* pull prg low */ | |
c609719b WD |
100 | |
101 | /* | |
102 | * Boot onboard FPGA | |
103 | */ | |
104 | #ifndef CONFIG_CPCI405_VER2 | |
6f4474e8 | 105 | if (cpci405_version() == 1) { |
c609719b WD |
106 | status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata)); |
107 | if (status != 0) { | |
108 | /* booting FPGA failed */ | |
109 | #ifndef FPGA_DEBUG | |
c609719b | 110 | /* set up serial port with default baudrate */ |
f6a1f490 | 111 | (void)get_clocks(); |
c609719b | 112 | gd->baudrate = CONFIG_BAUDRATE; |
f6a1f490 | 113 | serial_init(); |
c609719b WD |
114 | console_init_f(); |
115 | #endif | |
116 | printf("\nFPGA: Booting failed "); | |
117 | switch (status) { | |
118 | case ERROR_FPGA_PRG_INIT_LOW: | |
f6a1f490 MF |
119 | printf("(Timeout: INIT not low after " |
120 | "asserting PROGRAM*)\n "); | |
c609719b WD |
121 | break; |
122 | case ERROR_FPGA_PRG_INIT_HIGH: | |
f6a1f490 MF |
123 | printf("(Timeout: INIT not high after " |
124 | "deasserting PROGRAM*)\n "); | |
c609719b WD |
125 | break; |
126 | case ERROR_FPGA_PRG_DONE: | |
f6a1f490 MF |
127 | printf("(Timeout: DONE not high after " |
128 | "programming FPGA)\n "); | |
c609719b WD |
129 | break; |
130 | } | |
131 | ||
132 | /* display infos on fpgaimage */ | |
133 | index = 15; | |
f6a1f490 | 134 | for (i = 0; i < 4; i++) { |
c609719b | 135 | len = fpgadata[index]; |
f6a1f490 MF |
136 | printf("FPGA: %s\n", &(fpgadata[index + 1])); |
137 | index += len + 3; | |
c609719b | 138 | } |
f6a1f490 | 139 | putc('\n'); |
c609719b | 140 | /* delayed reboot */ |
f6a1f490 | 141 | for (i = 20; i > 0; i--) { |
c609719b | 142 | printf("Rebooting in %2d seconds \r",i); |
f6a1f490 | 143 | for (index = 0; index < 1000; index++) |
c609719b WD |
144 | udelay(1000); |
145 | } | |
f6a1f490 | 146 | putc('\n'); |
c609719b WD |
147 | do_reset(NULL, 0, 0, NULL); |
148 | } | |
149 | } | |
150 | #endif /* !CONFIG_CPCI405_VER2 */ | |
151 | ||
152 | /* | |
153 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
154 | * IRQ 16 405GP internally generated; active low; level sensitive | |
155 | * IRQ 17-24 RESERVED | |
156 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive | |
f6a1f490 | 157 | * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens. |
c609719b WD |
158 | * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive |
159 | * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive | |
160 | * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
161 | * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive | |
162 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive | |
163 | */ | |
952e7760 SR |
164 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
165 | mtdcr(UIC0ER, 0x00000000); /* disable all ints */ | |
166 | mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ | |
f6a1f490 | 167 | #if defined(CONFIG_CPCI405_6U) |
6f4474e8 | 168 | if (cpci405_version() == 3) { |
952e7760 | 169 | mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */ |
6f4474e8 | 170 | } else { |
952e7760 | 171 | mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ |
6f4474e8 | 172 | } |
6f35c531 | 173 | #else |
952e7760 | 174 | mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ |
6f35c531 | 175 | #endif |
952e7760 SR |
176 | mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ |
177 | mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, | |
f6a1f490 | 178 | * INT0 highest priority */ |
952e7760 | 179 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
c609719b WD |
180 | |
181 | return 0; | |
182 | } | |
183 | ||
c609719b WD |
184 | int ctermm2(void) |
185 | { | |
f6a1f490 | 186 | #if defined(CONFIG_CPCI405_VER2) |
4ef218f6 | 187 | return 0; /* no, board is cpci405 */ |
c609719b | 188 | #else |
f6a1f490 MF |
189 | if ((in_8((void*)0xf0000400) == 0x00) && |
190 | (in_8((void*)0xf0000401) == 0x01)) | |
4ef218f6 | 191 | return 0; /* no, board is cpci405 */ |
c609719b | 192 | else |
4ef218f6 | 193 | return -1; /* yes, board is cterm-m2 */ |
c609719b WD |
194 | #endif |
195 | } | |
196 | ||
c609719b WD |
197 | int cpci405_host(void) |
198 | { | |
d1c3b275 | 199 | if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN) |
4ef218f6 | 200 | return -1; /* yes, board is cpci405 host */ |
c609719b | 201 | else |
4ef218f6 | 202 | return 0; /* no, board is cpci405 adapter */ |
c609719b WD |
203 | } |
204 | ||
6f4474e8 | 205 | int cpci405_version(void) |
c609719b | 206 | { |
d1c3b275 | 207 | unsigned long CPC0_CR0Reg; |
c609719b WD |
208 | unsigned long value; |
209 | ||
210 | /* | |
6f4474e8 | 211 | * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) |
c609719b | 212 | */ |
d1c3b275 SR |
213 | CPC0_CR0Reg = mfdcr(CPC0_CR0); |
214 | mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); | |
6f35c531 MF |
215 | out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); |
216 | out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); | |
f6a1f490 MF |
217 | udelay(1000); /* wait some time before reading input */ |
218 | value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ | |
c609719b WD |
219 | |
220 | /* | |
6f4474e8 | 221 | * Restore GPIO settings |
c609719b | 222 | */ |
d1c3b275 | 223 | mtdcr(CPC0_CR0, CPC0_CR0Reg); |
c609719b | 224 | |
6f4474e8 SR |
225 | switch (value) { |
226 | case 0x00180000: | |
227 | /* CS2==1 && CS3==1 -> version 1 */ | |
228 | return 1; | |
229 | case 0x00080000: | |
230 | /* CS2==0 && CS3==1 -> version 2 */ | |
231 | return 2; | |
232 | case 0x00100000: | |
6f35c531 | 233 | /* CS2==1 && CS3==0 -> version 3 or 6U board */ |
6f4474e8 SR |
234 | return 3; |
235 | case 0x00000000: | |
236 | /* CS2==0 && CS3==0 -> version 4 */ | |
237 | return 4; | |
238 | default: | |
239 | /* should not be reached! */ | |
240 | return 2; | |
241 | } | |
c609719b WD |
242 | } |
243 | ||
c609719b WD |
244 | int misc_init_r (void) |
245 | { | |
d1c3b275 | 246 | unsigned long CPC0_CR0Reg; |
c609719b | 247 | |
87663b1c SR |
248 | /* adjust flash start and offset */ |
249 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
250 | gd->bd->bi_flashoffset = 0; | |
251 | ||
f6a1f490 | 252 | #if defined(CONFIG_CPCI405_VER2) |
87663b1c | 253 | { |
c609719b WD |
254 | unsigned char *dst; |
255 | ulong len = sizeof(fpgadata); | |
256 | int status; | |
257 | int index; | |
258 | int i; | |
c609719b WD |
259 | |
260 | /* | |
261 | * On CPCI-405 version 2 the environment is saved in eeprom! | |
262 | * FPGA can be gzip compressed (malloc) and booted this late. | |
263 | */ | |
6f4474e8 | 264 | if (cpci405_version() >= 2) { |
c609719b WD |
265 | /* |
266 | * Setup GPIO pins (CS6+CS7 as GPIO) | |
267 | */ | |
d1c3b275 SR |
268 | CPC0_CR0Reg = mfdcr(CPC0_CR0); |
269 | mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); | |
c609719b | 270 | |
6d0f6bcf | 271 | dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); |
f6a1f490 MF |
272 | if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, |
273 | (uchar *)fpgadata, &len) != 0) { | |
274 | printf("GUNZIP ERROR - must RESET board to recover\n"); | |
275 | do_reset(NULL, 0, 0, NULL); | |
c609719b WD |
276 | } |
277 | ||
278 | status = fpga_boot(dst, len); | |
279 | if (status != 0) { | |
280 | printf("\nFPGA: Booting failed "); | |
281 | switch (status) { | |
282 | case ERROR_FPGA_PRG_INIT_LOW: | |
f6a1f490 MF |
283 | printf("(Timeout: INIT not low after " |
284 | "asserting PROGRAM*)\n "); | |
c609719b WD |
285 | break; |
286 | case ERROR_FPGA_PRG_INIT_HIGH: | |
f6a1f490 MF |
287 | printf("(Timeout: INIT not high after " |
288 | "deasserting PROGRAM*)\n "); | |
c609719b WD |
289 | break; |
290 | case ERROR_FPGA_PRG_DONE: | |
f6a1f490 MF |
291 | printf("(Timeout: DONE not high after " |
292 | "programming FPGA)\n "); | |
c609719b WD |
293 | break; |
294 | } | |
295 | ||
296 | /* display infos on fpgaimage */ | |
297 | index = 15; | |
f6a1f490 | 298 | for (i = 0; i < 4; i++) { |
c609719b | 299 | len = dst[index]; |
f6a1f490 MF |
300 | printf("FPGA: %s\n", &(dst[index + 1])); |
301 | index += len + 3; | |
c609719b | 302 | } |
f6a1f490 | 303 | putc('\n'); |
c609719b | 304 | /* delayed reboot */ |
f6a1f490 MF |
305 | for (i = 20; i > 0; i--) { |
306 | printf("Rebooting in %2d seconds \r", i); | |
307 | for (index = 0; index < 1000; index++) | |
c609719b WD |
308 | udelay(1000); |
309 | } | |
f6a1f490 | 310 | putc('\n'); |
c609719b WD |
311 | do_reset(NULL, 0, 0, NULL); |
312 | } | |
313 | ||
314 | /* restore gpio/cs settings */ | |
d1c3b275 | 315 | mtdcr(CPC0_CR0, CPC0_CR0Reg); |
c609719b WD |
316 | |
317 | puts("FPGA: "); | |
318 | ||
319 | /* display infos on fpgaimage */ | |
320 | index = 15; | |
f6a1f490 | 321 | for (i = 0; i < 4; i++) { |
c609719b | 322 | len = dst[index]; |
f6a1f490 MF |
323 | printf("%s ", &(dst[index + 1])); |
324 | index += len + 3; | |
c609719b | 325 | } |
f6a1f490 | 326 | putc('\n'); |
c609719b WD |
327 | |
328 | free(dst); | |
6f4474e8 SR |
329 | |
330 | /* | |
331 | * Reset FPGA via FPGA_DATA pin | |
332 | */ | |
333 | SET_FPGA(FPGA_PRG | FPGA_CLK); | |
334 | udelay(1000); /* wait 1ms */ | |
335 | SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); | |
336 | udelay(1000); /* wait 1ms */ | |
337 | ||
f6a1f490 MF |
338 | #if defined(CONFIG_CPCI405_6U) |
339 | #error HIER GETH ES WEITER MIT IO ACCESSORS | |
6f4474e8 | 340 | if (cpci405_version() == 3) { |
6f4474e8 SR |
341 | /* |
342 | * Enable outputs in fpga on version 3 board | |
343 | */ | |
f6a1f490 MF |
344 | out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, |
345 | in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | | |
346 | CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT); | |
6f4474e8 SR |
347 | |
348 | /* | |
349 | * Set outputs to 0 | |
350 | */ | |
f6a1f490 | 351 | out_8((void*)CONFIG_SYS_LED_ADDR, 0x00); |
6f4474e8 SR |
352 | |
353 | /* | |
354 | * Reset external DUART | |
355 | */ | |
f6a1f490 MF |
356 | out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, |
357 | in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | | |
358 | CONFIG_SYS_FPGA_MODE_DUART_RESET); | |
6f4474e8 | 359 | udelay(100); |
f6a1f490 MF |
360 | out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, |
361 | in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) & | |
362 | ~CONFIG_SYS_FPGA_MODE_DUART_RESET); | |
6f4474e8 | 363 | } |
6f35c531 | 364 | #endif |
c609719b WD |
365 | } |
366 | else { | |
6f4474e8 SR |
367 | puts("\n*** U-Boot Version does not match Board Version!\n"); |
368 | puts("*** CPCI-405 Version 1.x detected!\n"); | |
f6a1f490 MF |
369 | puts("*** Please use correct U-Boot version " |
370 | "(CPCI405 instead of CPCI4052)!\n\n"); | |
c609719b | 371 | } |
87663b1c | 372 | } |
c609719b | 373 | #else /* CONFIG_CPCI405_VER2 */ |
6f4474e8 SR |
374 | if (cpci405_version() >= 2) { |
375 | puts("\n*** U-Boot Version does not match Board Version!\n"); | |
376 | puts("*** CPCI-405 Board Version 2.x detected!\n"); | |
f6a1f490 MF |
377 | puts("*** Please use correct U-Boot version " |
378 | "(CPCI4052 instead of CPCI405)!\n\n"); | |
c609719b | 379 | } |
c609719b WD |
380 | #endif /* CONFIG_CPCI405_VER2 */ |
381 | ||
afcc4a74 SR |
382 | /* |
383 | * Select cts (and not dsr) on uart1 | |
384 | */ | |
d1c3b275 SR |
385 | CPC0_CR0Reg = mfdcr(CPC0_CR0); |
386 | mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); | |
afcc4a74 | 387 | |
f6a1f490 | 388 | return 0; |
c609719b WD |
389 | } |
390 | ||
c609719b WD |
391 | /* |
392 | * Check Board Identity: | |
393 | */ | |
394 | ||
f6a1f490 | 395 | int checkboard(void) |
c609719b WD |
396 | { |
397 | #ifndef CONFIG_CPCI405_VER2 | |
398 | int index; | |
399 | int len; | |
400 | #endif | |
77ddac94 | 401 | char str[64]; |
cdb74977 | 402 | int i = getenv_f("serial#", str, sizeof(str)); |
6f4474e8 | 403 | unsigned short ver; |
c609719b | 404 | |
f6a1f490 | 405 | puts("Board: "); |
c609719b | 406 | |
f6a1f490 MF |
407 | if (i == -1) |
408 | puts("### No HW ID - assuming CPCI405"); | |
409 | else | |
c609719b | 410 | puts(str); |
c609719b | 411 | |
6f4474e8 SR |
412 | ver = cpci405_version(); |
413 | printf(" (Ver %d.x, ", ver); | |
c609719b | 414 | |
c609719b | 415 | if (ctermm2()) { |
77ddac94 | 416 | char str[4]; |
1b554406 SR |
417 | |
418 | /* | |
419 | * Read board-id and save in env-variable | |
420 | */ | |
421 | sprintf(str, "%d", *(unsigned char *)0xf0000400); | |
422 | setenv("boardid", str); | |
423 | printf("CTERM-M2 - Id=%s)", str); | |
c609719b | 424 | } else { |
f6a1f490 MF |
425 | if (cpci405_host()) |
426 | puts("PCI Host Version)"); | |
427 | else | |
428 | puts("PCI Adapter Version)"); | |
c609719b WD |
429 | } |
430 | ||
431 | #ifndef CONFIG_CPCI405_VER2 | |
f6a1f490 | 432 | puts("\nFPGA: "); |
c609719b WD |
433 | |
434 | /* display infos on fpgaimage */ | |
435 | index = 15; | |
f6a1f490 | 436 | for (i = 0; i < 4; i++) { |
c609719b | 437 | len = fpgadata[index]; |
f6a1f490 MF |
438 | printf("%s ", &(fpgadata[index + 1])); |
439 | index += len + 3; | |
c609719b WD |
440 | } |
441 | #endif | |
442 | ||
f6a1f490 | 443 | putc('\n'); |
c609719b WD |
444 | return 0; |
445 | } | |
446 | ||
6f35c531 | 447 | void reset_phy(void) |
c609719b | 448 | { |
f6a1f490 | 449 | #if defined(CONFIG_LXT971_NO_SLEEP) |
c609719b | 450 | |
6f35c531 MF |
451 | /* |
452 | * Disable sleep mode in LXT971 | |
453 | */ | |
454 | lxt971_no_sleep(); | |
455 | #endif | |
c609719b WD |
456 | } |
457 | ||
f6a1f490 | 458 | #if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET) |
c609719b WD |
459 | void ide_set_reset(int on) |
460 | { | |
c609719b WD |
461 | /* |
462 | * Assert or deassert CompactFlash Reset Pin | |
463 | */ | |
f6a1f490 MF |
464 | if (on) { /* assert RESET */ |
465 | out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, | |
466 | in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) & | |
467 | ~CONFIG_SYS_FPGA_MODE_CF_RESET); | |
468 | } else { /* release RESET */ | |
469 | out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, | |
470 | in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | | |
471 | CONFIG_SYS_FPGA_MODE_CF_RESET); | |
c609719b WD |
472 | } |
473 | } | |
474 | ||
f6a1f490 | 475 | #endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */ |
c609719b | 476 | |
466fff1a | 477 | #if defined(CONFIG_PCI) |
6f35c531 MF |
478 | void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) |
479 | { | |
480 | unsigned char int_line = 0xff; | |
481 | ||
482 | /* | |
483 | * Write pci interrupt line register (cpci405 specific) | |
484 | */ | |
485 | switch (PCI_DEV(dev) & 0x03) { | |
486 | case 0: | |
487 | int_line = 27 + 2; | |
488 | break; | |
489 | case 1: | |
490 | int_line = 27 + 3; | |
491 | break; | |
492 | case 2: | |
493 | int_line = 27 + 0; | |
494 | break; | |
495 | case 3: | |
496 | int_line = 27 + 1; | |
497 | break; | |
498 | } | |
499 | ||
500 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); | |
501 | } | |
502 | ||
503 | int pci_pre_init(struct pci_controller *hose) | |
504 | { | |
505 | hose->fixup_irq = cpci405_pci_fixup_irq; | |
506 | return 1; | |
507 | } | |
466fff1a | 508 | #endif /* defined(CONFIG_PCI) */ |
6f35c531 | 509 | |
600fe46f MF |
510 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
511 | void ft_board_setup(void *blob, bd_t *bd) | |
512 | { | |
513 | int rc; | |
514 | ||
515 | __ft_board_setup(blob, bd); | |
516 | ||
517 | /* | |
518 | * Disable PCI in adapter mode. | |
519 | */ | |
520 | if (!cpci405_host()) { | |
521 | rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status", | |
522 | "disabled", sizeof("disabled"), 1); | |
523 | if (rc) { | |
524 | printf("Unable to update property status in PCI node, " | |
525 | "err=%s\n", | |
526 | fdt_strerror(rc)); | |
527 | } | |
528 | } | |
529 | } | |
530 | #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ | |
531 | ||
f6a1f490 MF |
532 | #if defined(CONFIG_CPCI405AB) |
533 | #define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ | |
534 | CONFIG_SYS_FPGA_MODE), \ | |
535 | in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ | |
536 | CONFIG_SYS_FPGA_MODE)) | \ | |
537 | CONFIG_SYS_FPGA_MODE_1WIRE_DIR) | |
6f35c531 | 538 | |
f6a1f490 MF |
539 | #define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ |
540 | CONFIG_SYS_FPGA_MODE), \ | |
541 | in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ | |
542 | CONFIG_SYS_FPGA_MODE)) & \ | |
543 | ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR) | |
1b554406 | 544 | |
f6a1f490 MF |
545 | #define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ |
546 | CONFIG_SYS_FPGA_STATUS)) & \ | |
547 | CONFIG_SYS_FPGA_MODE_1WIRE) | |
1b554406 SR |
548 | |
549 | /* | |
550 | * Generate a 1-wire reset, return 1 if no presence detect was found, | |
551 | * return 0 otherwise. | |
552 | * (NOTE: Does not handle alarm presence from DS2404/DS1994) | |
553 | */ | |
554 | int OWTouchReset(void) | |
d4629c8c | 555 | { |
1b554406 SR |
556 | int result; |
557 | ||
558 | ONE_WIRE_CLEAR; | |
559 | udelay(480); | |
560 | ONE_WIRE_SET; | |
561 | udelay(70); | |
562 | ||
563 | result = ONE_WIRE_GET; | |
564 | ||
565 | udelay(410); | |
566 | return result; | |
567 | } | |
568 | ||
1b554406 SR |
569 | /* |
570 | * Send 1 a 1-wire write bit. | |
571 | * Provide 10us recovery time. | |
572 | */ | |
573 | void OWWriteBit(int bit) | |
574 | { | |
575 | if (bit) { | |
576 | /* | |
577 | * write '1' bit | |
578 | */ | |
579 | ONE_WIRE_CLEAR; | |
580 | udelay(6); | |
581 | ONE_WIRE_SET; | |
582 | udelay(64); | |
583 | } else { | |
584 | /* | |
585 | * write '0' bit | |
586 | */ | |
587 | ONE_WIRE_CLEAR; | |
588 | udelay(60); | |
589 | ONE_WIRE_SET; | |
590 | udelay(10); | |
d4629c8c | 591 | } |
1b554406 SR |
592 | } |
593 | ||
1b554406 SR |
594 | /* |
595 | * Read a bit from the 1-wire bus and return it. | |
596 | * Provide 10us recovery time. | |
597 | */ | |
598 | int OWReadBit(void) | |
599 | { | |
600 | int result; | |
601 | ||
602 | ONE_WIRE_CLEAR; | |
603 | udelay(6); | |
604 | ONE_WIRE_SET; | |
605 | udelay(9); | |
606 | ||
607 | result = ONE_WIRE_GET; | |
608 | ||
609 | udelay(55); | |
610 | return result; | |
d4629c8c SR |
611 | } |
612 | ||
1b554406 SR |
613 | void OWWriteByte(int data) |
614 | { | |
615 | int loop; | |
616 | ||
f6a1f490 | 617 | for (loop = 0; loop < 8; loop++) { |
1b554406 SR |
618 | OWWriteBit(data & 0x01); |
619 | data >>= 1; | |
620 | } | |
621 | } | |
622 | ||
1b554406 | 623 | int OWReadByte(void) |
d4629c8c | 624 | { |
1b554406 SR |
625 | int loop, result = 0; |
626 | ||
f6a1f490 | 627 | for (loop = 0; loop < 8; loop++) { |
1b554406 | 628 | result >>= 1; |
f6a1f490 | 629 | if (OWReadBit()) |
1b554406 | 630 | result |= 0x80; |
d4629c8c | 631 | } |
1b554406 SR |
632 | |
633 | return result; | |
d4629c8c SR |
634 | } |
635 | ||
54841ab5 | 636 | int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
1b554406 | 637 | { |
f6a1f490 | 638 | unsigned short val; |
1b554406 SR |
639 | int result; |
640 | int i; | |
641 | unsigned char ow_id[6]; | |
77ddac94 | 642 | char str[32]; |
1b554406 SR |
643 | |
644 | /* | |
645 | * Clear 1-wire bit (open drain with pull-up) | |
646 | */ | |
f6a1f490 MF |
647 | val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + |
648 | CONFIG_SYS_FPGA_MODE)); | |
649 | val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */ | |
650 | out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + | |
651 | CONFIG_SYS_FPGA_MODE), val); | |
1b554406 SR |
652 | |
653 | result = OWTouchReset(); | |
f6a1f490 | 654 | if (result != 0) |
1b554406 | 655 | puts("No 1-wire device detected!\n"); |
1b554406 SR |
656 | |
657 | OWWriteByte(0x33); /* send read rom command */ | |
658 | OWReadByte(); /* skip family code ( == 0x01) */ | |
f6a1f490 | 659 | for (i = 0; i < 6; i++) |
1b554406 | 660 | ow_id[i] = OWReadByte(); |
1affd5c1 | 661 | OWReadByte(); /* read crc */ |
1b554406 | 662 | |
1affd5c1 MF |
663 | sprintf(str, "%02X%02X%02X%02X%02X%02X", |
664 | ow_id[0], ow_id[1], ow_id[2], ow_id[3], ow_id[4], ow_id[5]); | |
1b554406 SR |
665 | printf("Setting environment variable 'ow_id' to %s\n", str); |
666 | setenv("ow_id", str); | |
667 | ||
668 | return 0; | |
669 | } | |
670 | U_BOOT_CMD( | |
671 | onewire, 1, 1, do_onewire, | |
2fb2604d | 672 | "Read 1-write ID", |
a89c33db WD |
673 | "" |
674 | ); | |
1b554406 | 675 | |
f6a1f490 MF |
676 | #define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */ |
677 | #define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */ | |
87663b1c SR |
678 | |
679 | /* | |
680 | * Write backplane ip-address... | |
681 | */ | |
54841ab5 | 682 | int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
87663b1c | 683 | { |
87663b1c SR |
684 | char *buf; |
685 | ulong crc; | |
686 | char str[32]; | |
687 | char *ptr; | |
688 | IPaddr_t ipaddr; | |
689 | ||
0e8d1586 | 690 | buf = malloc(CONFIG_ENV_SIZE_2); |
f6a1f490 MF |
691 | if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, |
692 | (uchar *)buf, CONFIG_ENV_SIZE_2)) | |
87663b1c | 693 | puts("\nError reading backplane EEPROM!\n"); |
f6a1f490 MF |
694 | else { |
695 | crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4); | |
87663b1c | 696 | if (crc != *(ulong *)buf) { |
f6a1f490 MF |
697 | printf("ERROR: crc mismatch %08lx %08lx\n", |
698 | crc, *(ulong *)buf); | |
87663b1c SR |
699 | return -1; |
700 | } | |
701 | ||
702 | /* | |
703 | * Find bp_ip | |
704 | */ | |
705 | ptr = strstr(buf+4, "bp_ip="); | |
706 | if (ptr == NULL) { | |
707 | printf("ERROR: bp_ip not found!\n"); | |
708 | return -1; | |
709 | } | |
710 | ptr += 6; | |
711 | ipaddr = string_to_ip(ptr); | |
712 | ||
713 | /* | |
714 | * Update whole ip-addr | |
715 | */ | |
9aabb2f8 | 716 | sprintf(str, "%pI4", &ipaddr); |
87663b1c SR |
717 | setenv("ipaddr", str); |
718 | printf("Updated ip_addr from bp_eeprom to %s!\n", str); | |
719 | } | |
720 | ||
721 | free(buf); | |
722 | ||
723 | return 0; | |
724 | } | |
725 | U_BOOT_CMD( | |
726 | getbpip, 1, 1, do_get_bpip, | |
2fb2604d | 727 | "Update IP-Address with Backplane IP-Address", |
a89c33db WD |
728 | "" |
729 | ); | |
87663b1c SR |
730 | |
731 | /* | |
732 | * Set and print backplane ip... | |
733 | */ | |
54841ab5 | 734 | int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
87663b1c SR |
735 | { |
736 | char *buf; | |
77ddac94 | 737 | char str[32]; |
87663b1c SR |
738 | ulong crc; |
739 | ||
740 | if (argc < 2) { | |
741 | puts("ERROR!\n"); | |
742 | return -1; | |
743 | } | |
744 | ||
745 | printf("Setting bp_ip to %s\n", argv[1]); | |
0e8d1586 JCPV |
746 | buf = malloc(CONFIG_ENV_SIZE_2); |
747 | memset(buf, 0, CONFIG_ENV_SIZE_2); | |
87663b1c SR |
748 | sprintf(str, "bp_ip=%s", argv[1]); |
749 | strcpy(buf+4, str); | |
f6a1f490 | 750 | crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4); |
87663b1c SR |
751 | *(ulong *)buf = crc; |
752 | ||
f6a1f490 MF |
753 | if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, |
754 | 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) | |
87663b1c | 755 | puts("\nError writing backplane EEPROM!\n"); |
87663b1c SR |
756 | |
757 | free(buf); | |
758 | ||
759 | return 0; | |
760 | } | |
761 | U_BOOT_CMD( | |
762 | setbpip, 2, 1, do_set_bpip, | |
2fb2604d | 763 | "Write Backplane IP-Address", |
a89c33db WD |
764 | "" |
765 | ); | |
87663b1c | 766 | |
1b554406 | 767 | #endif /* CONFIG_CPCI405AB */ |