[people/ms/u-boot.git] / board / esd / cpci405 / flash.c

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/processor.h>

/*
 * include common flash code (for esd boards)
 */
#include "../common/flash.c"

/*-----------------------------------------------------------------------
 * Functions
 */
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
static void flash_get_offsets (ulong base, flash_info_t * info);

/*-----------------------------------------------------------------------
 */

unsigned long calc_size(unsigned long size)
{
	switch (size) {
	case 1 << 20:
		return 0;
	case 2 << 20:
		return 1;
	case 4 << 20:
		return 2;
	case 8 << 20:
		return 3;
	case 16 << 20:
		return 4;
	default:
		return 0;
	}
}


unsigned long flash_init (void)
{
	unsigned long size_b0, size_b1;
	int i;
	uint pbcr;
	unsigned long base_b0, base_b1;

	/* Init: no FLASHes known */
	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
		flash_info[i].flash_id = FLASH_UNKNOWN;
	}

	/* Static FLASH Bank configuration here - FIXME XXX */

	base_b0 = FLASH_BASE0_PRELIM;
	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);

	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
				size_b0, size_b0 << 20);
	}

	base_b1 = FLASH_BASE1_PRELIM;
	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);

	/* Re-do sizing to get full correct info */

	if (size_b1) {
		if (size_b1 < (1 << 20)) {
			/* minimum CS size on PPC405GP is 1MB !!! */
			size_b1 = 1 << 20;
		}
		base_b1 = -size_b1;
		mtdcr (EBC0_CFGADDR, PB0CR);
		pbcr = mfdcr (EBC0_CFGDATA);
		mtdcr (EBC0_CFGADDR, PB0CR);
		pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17);
		mtdcr (EBC0_CFGDATA, pbcr);
#if 0 /* test-only */
		printf("size_b1=%x base_b1=%x PB1CR = %x\n",
		       size_b1, base_b1, pbcr); /* test-only */
#endif
	}

	if (size_b0) {
		if (size_b0 < (1 << 20)) {
			/* minimum CS size on PPC405GP is 1MB !!! */
			size_b0 = 1 << 20;
		}
		base_b0 = base_b1 - size_b0;
		mtdcr (EBC0_CFGADDR, PB1CR);
		pbcr = mfdcr (EBC0_CFGDATA);
		mtdcr (EBC0_CFGADDR, PB1CR);
		pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17);
		mtdcr (EBC0_CFGDATA, pbcr);
#if 0 /* test-only */
		printf("size_b0=%x base_b0=%x PB0CR = %x\n",
		       size_b0, base_b0, pbcr); /* test-only */
#endif
	}

	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);

	flash_get_offsets (base_b0, &flash_info[0]);

	/* monitor protection ON by default */
	flash_protect (FLAG_PROTECT_SET,
			base_b0 + size_b0 - monitor_flash_len,
			base_b0 + size_b0 - 1, &flash_info[0]);

	if (size_b1) {
		/* Re-do sizing to get full correct info */
		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);

		flash_get_offsets (base_b1, &flash_info[1]);

		/* monitor protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
				base_b1 + size_b1 - monitor_flash_len,
				base_b1 + size_b1 - 1, &flash_info[1]);
		/* monitor protection OFF by default (one is enough) */
		flash_protect (FLAG_PROTECT_CLEAR,
				base_b0 + size_b0 - monitor_flash_len,
				base_b0 + size_b0 - 1, &flash_info[0]);
	} else {
		flash_info[1].flash_id = FLASH_UNKNOWN;
		flash_info[1].sector_count = -1;
	}

	flash_info[0].size = size_b0;
	flash_info[1].size = size_b1;

	return (size_b0 + size_b1);
}
Commit	Line	Data
affae2bf	1	/*
6f4474e8	2	* (C) Copyright 2001-2003
affae2bf WD	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
affae2bf WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
affae2bf WD	6	*/
	7
	8	#include <common.h>
b36df561	9	#include <asm/ppc4xx.h>
affae2bf WD	10	#include <asm/processor.h>
	11
	12	/*
	13	* include common flash code (for esd boards)
	14	*/
	15	#include "../common/flash.c"
	16
	17	/*-----------------------------------------------------------------------
	18	* Functions
	19	*/
	20	static ulong flash_get_size (vu_long * addr, flash_info_t * info);
	21	static void flash_get_offsets (ulong base, flash_info_t * info);
	22
	23	/*-----------------------------------------------------------------------
	24	*/
	25
6f4474e8 SR	26	unsigned long calc_size(unsigned long size)
	27	{
	28	switch (size) {
	29	case 1 << 20:
	30	return 0;
	31	case 2 << 20:
	32	return 1;
	33	case 4 << 20:
	34	return 2;
	35	case 8 << 20:
	36	return 3;
	37	case 16 << 20:
	38	return 4;
	39	default:
	40	return 0;
	41	}
	42	}
	43
	44
affae2bf WD	45	unsigned long flash_init (void)
	46	{
	47	unsigned long size_b0, size_b1;
	48	int i;
	49	uint pbcr;
	50	unsigned long base_b0, base_b1;
affae2bf WD	51
affae2bf WD	52	/* Init: no FLASHes known */
6d0f6bcf	53	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
affae2bf WD	54	flash_info[i].flash_id = FLASH_UNKNOWN;
	55	}
	56
	57	/* Static FLASH Bank configuration here - FIXME XXX */
	58
	59	base_b0 = FLASH_BASE0_PRELIM;
	60	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
	61
	62	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
	63	printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
	64	size_b0, size_b0 << 20);
	65	}
	66
	67	base_b1 = FLASH_BASE1_PRELIM;
	68	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
	69
	70	/* Re-do sizing to get full correct info */
	71
	72	if (size_b1) {
6f4474e8 SR	73	if (size_b1 < (1 << 20)) {
	74	/* minimum CS size on PPC405GP is 1MB !!! */
	75	size_b1 = 1 << 20;
	76	}
d4629c8c	77	base_b1 = -size_b1;
d1c3b275 SR	78	mtdcr (EBC0_CFGADDR, PB0CR);
	79	pbcr = mfdcr (EBC0_CFGDATA);
	80	mtdcr (EBC0_CFGADDR, PB0CR);
6f4474e8	81	pbcr = (pbcr & 0x0001ffff) \| base_b1 \| (calc_size(size_b1) << 17);
d1c3b275	82	mtdcr (EBC0_CFGDATA, pbcr);
6f4474e8	83	#if 0 /* test-only */
d1c3b275	84	printf("size_b1=%x base_b1=%x PB1CR = %x\n",
6f4474e8 SR	85	size_b1, base_b1, pbcr); /* test-only */
6f4474e8 SR	86	#endif
affae2bf WD	87	}
	88
	89	if (size_b0) {
6f4474e8 SR	90	if (size_b0 < (1 << 20)) {
	91	/* minimum CS size on PPC405GP is 1MB !!! */
	92	size_b0 = 1 << 20;
	93	}
d4629c8c	94	base_b0 = base_b1 - size_b0;
d1c3b275 SR	95	mtdcr (EBC0_CFGADDR, PB1CR);
	96	pbcr = mfdcr (EBC0_CFGDATA);
	97	mtdcr (EBC0_CFGADDR, PB1CR);
6f4474e8	98	pbcr = (pbcr & 0x0001ffff) \| base_b0 \| (calc_size(size_b0) << 17);
d1c3b275	99	mtdcr (EBC0_CFGDATA, pbcr);
6f4474e8	100	#if 0 /* test-only */
d1c3b275	101	printf("size_b0=%x base_b0=%x PB0CR = %x\n",
6f4474e8 SR	102	size_b0, base_b0, pbcr); /* test-only */
6f4474e8 SR	103	#endif
affae2bf WD	104	}
	105
	106	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
	107
	108	flash_get_offsets (base_b0, &flash_info[0]);
	109
	110	/* monitor protection ON by default */
	111	flash_protect (FLAG_PROTECT_SET,
3b57fe0a	112	base_b0 + size_b0 - monitor_flash_len,
affae2bf WD	113	base_b0 + size_b0 - 1, &flash_info[0]);
	114
	115	if (size_b1) {
	116	/* Re-do sizing to get full correct info */
	117	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
	118
	119	flash_get_offsets (base_b1, &flash_info[1]);
	120
	121	/* monitor protection ON by default */
	122	flash_protect (FLAG_PROTECT_SET,
3b57fe0a	123	base_b1 + size_b1 - monitor_flash_len,
affae2bf WD	124	base_b1 + size_b1 - 1, &flash_info[1]);
	125	/* monitor protection OFF by default (one is enough) */
	126	flash_protect (FLAG_PROTECT_CLEAR,
3b57fe0a	127	base_b0 + size_b0 - monitor_flash_len,
affae2bf WD	128	base_b0 + size_b0 - 1, &flash_info[0]);
	129	} else {
	130	flash_info[1].flash_id = FLASH_UNKNOWN;
	131	flash_info[1].sector_count = -1;
	132	}
	133
	134	flash_info[0].size = size_b0;
	135	flash_info[1].size = size_b1;
	136
	137	return (size_b0 + size_b1);
	138	}