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c609719b WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | ||
25 | #include <common.h> | |
26 | #include <asm/processor.h> | |
27 | ||
28 | ||
29 | long int fixed_sdram( void ); | |
30 | ||
31 | int board_pre_init (void) | |
32 | { | |
33 | uint reg; | |
34 | ||
35 | /*-------------------------------------------------------------------- | |
36 | * Setup the external bus controller/chip selects | |
37 | *-------------------------------------------------------------------*/ | |
38 | mtdcr( ebccfga, xbcfg ); | |
39 | reg = mfdcr( ebccfgd ); | |
40 | mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */ | |
41 | ||
42 | mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */ | |
43 | mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */ | |
44 | /* test-only: other regs still missing... */ | |
45 | ||
46 | /*-------------------------------------------------------------------- | |
47 | * Setup the interrupt controller polarities, triggers, etc. | |
48 | *-------------------------------------------------------------------*/ | |
49 | mtdcr( uic0sr, 0xffffffff ); /* clear all */ | |
50 | mtdcr( uic0er, 0x00000000 ); /* disable all */ | |
51 | mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */ | |
52 | mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */ | |
53 | mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */ | |
54 | mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */ | |
55 | mtdcr( uic0sr, 0xffffffff ); /* clear all */ | |
56 | ||
57 | mtdcr( uic1sr, 0xffffffff ); /* clear all */ | |
58 | mtdcr( uic1er, 0x00000000 ); /* disable all */ | |
59 | mtdcr( uic1cr, 0x00000000 ); /* all non-critical */ | |
60 | mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */ | |
61 | mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */ | |
62 | mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */ | |
63 | mtdcr( uic1sr, 0xffffffff ); /* clear all */ | |
64 | ||
65 | return 0; | |
66 | } | |
67 | ||
68 | ||
c609719b WD |
69 | int checkboard (void) |
70 | { | |
71 | sys_info_t sysinfo; | |
72 | get_sys_info(&sysinfo); | |
73 | ||
74 | printf("Board: esd CPCI-440\n"); | |
75 | printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000); | |
76 | printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000); | |
77 | printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000); | |
78 | printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000); | |
79 | printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000); | |
80 | return (0); | |
81 | } | |
82 | ||
83 | ||
84 | long int initdram (int board_type) | |
85 | { | |
86 | long dram_size = 0; | |
87 | ||
88 | dram_size = fixed_sdram(); | |
89 | return dram_size; | |
90 | } | |
91 | ||
92 | ||
93 | /************************************************************************* | |
94 | * fixed sdram init -- doesn't use serial presence detect. | |
95 | * | |
96 | * Assumes: 64 MB, non-ECC, non-registered | |
97 | * PLB @ 133 MHz | |
98 | * | |
99 | ************************************************************************/ | |
100 | long int fixed_sdram( void ) | |
101 | { | |
102 | uint reg; | |
103 | ||
104 | /*-------------------------------------------------------------------- | |
105 | * Setup some default | |
106 | *------------------------------------------------------------------*/ | |
107 | mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */ | |
108 | mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */ | |
109 | mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */ | |
110 | mtsdram( mem_wddctr,0x40000000 ); /* wrcp=0 dcd=0 */ | |
111 | mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */ | |
112 | ||
113 | /*-------------------------------------------------------------------- | |
114 | * Setup for board-specific specific mem | |
115 | *------------------------------------------------------------------*/ | |
116 | /* | |
117 | * Following for CAS Latency = 2.5 @ 133 MHz PLB | |
118 | */ | |
119 | mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/ | |
120 | mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ | |
121 | /* RA=10 RD=3 */ | |
122 | mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ | |
123 | mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */ | |
124 | mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */ | |
125 | udelay( 400 ); /* Delay 200 usecs (min) */ | |
126 | ||
127 | /*-------------------------------------------------------------------- | |
128 | * Enable the controller, then wait for DCEN to complete | |
129 | *------------------------------------------------------------------*/ | |
130 | mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */ | |
131 | for(;;) | |
132 | { | |
133 | mfsdram( mem_mcsts, reg ); | |
134 | if( reg & 0x80000000 ) | |
135 | break; | |
136 | } | |
137 | ||
138 | return( 64 * 1024 * 1024 ); /* 64 MB */ | |
139 | } |