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Commit | Line | Data |
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37bd321e WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
37bd321e WD |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include "cpciiser4.h" | |
10 | #include <asm/processor.h> | |
11 | #include <command.h> | |
8bde7f77 | 12 | |
d87080b7 WD |
13 | DECLARE_GLOBAL_DATA_PTR; |
14 | ||
20aacbf0 | 15 | extern void lxt971_no_sleep(void); |
8bde7f77 | 16 | |
37bd321e WD |
17 | |
18 | /* ------------------------------------------------------------------------- */ | |
19 | ||
20 | #if 0 | |
21 | #define FPGA_DEBUG | |
22 | #endif | |
23 | ||
24 | #if 0 | |
25 | #define FPGA_DEBUG2 | |
26 | #endif | |
27 | ||
28 | /* fpga configuration data - generated by bin2cc */ | |
29 | const unsigned char fpgadata[] = { | |
30 | #include "fpgadata.c" | |
31 | }; | |
32 | ||
33 | /* | |
34 | * include common fpga code (for esd boards) | |
35 | */ | |
36 | #include "../common/fpga.c" | |
37 | ||
38 | ||
c837dcb1 | 39 | int board_early_init_f (void) |
37bd321e | 40 | { |
37bd321e | 41 | int index, len, i; |
37bd321e WD |
42 | int status; |
43 | ||
44 | #ifdef FPGA_DEBUG | |
45 | /* set up serial port with default baudrate */ | |
46 | (void) get_clocks (); | |
47 | gd->baudrate = CONFIG_BAUDRATE; | |
48 | serial_init (); | |
49 | console_init_f (); | |
50 | #endif | |
51 | ||
52 | /* | |
53 | * Boot onboard FPGA | |
54 | */ | |
55 | status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); | |
56 | if (status != 0) { | |
57 | /* booting FPGA failed */ | |
58 | #ifndef FPGA_DEBUG | |
59 | /* set up serial port with default baudrate */ | |
60 | (void) get_clocks (); | |
61 | gd->baudrate = CONFIG_BAUDRATE; | |
62 | serial_init (); | |
63 | console_init_f (); | |
64 | #endif | |
65 | printf ("\nFPGA: Booting failed "); | |
66 | switch (status) { | |
67 | case ERROR_FPGA_PRG_INIT_LOW: | |
68 | printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); | |
69 | break; | |
70 | case ERROR_FPGA_PRG_INIT_HIGH: | |
71 | printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); | |
72 | break; | |
73 | case ERROR_FPGA_PRG_DONE: | |
74 | printf ("(Timeout: DONE not high after programming FPGA)\n "); | |
75 | break; | |
76 | } | |
77 | ||
78 | /* display infos on fpgaimage */ | |
79 | index = 15; | |
80 | for (i = 0; i < 4; i++) { | |
81 | len = fpgadata[index]; | |
82 | printf ("FPGA: %s\n", &(fpgadata[index + 1])); | |
83 | index += len + 3; | |
84 | } | |
85 | putc ('\n'); | |
86 | /* delayed reboot */ | |
87 | for (i = 20; i > 0; i--) { | |
88 | printf ("Rebooting in %2d seconds \r", i); | |
89 | for (index = 0; index < 1000; index++) | |
90 | udelay (1000); | |
91 | } | |
92 | putc ('\n'); | |
93 | do_reset (NULL, 0, 0, NULL); | |
94 | } | |
95 | ||
96 | /* | |
97 | * Init FPGA via RESET (read access on CS3) | |
98 | */ | |
049216f0 | 99 | in_8((void *)0xf0200000); |
37bd321e WD |
100 | |
101 | /* | |
102 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
103 | * IRQ 16 405GP internally generated; active low; level sensitive | |
104 | * IRQ 17-24 RESERVED | |
105 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive | |
106 | * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive | |
107 | * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive | |
108 | * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive | |
109 | * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
110 | * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive | |
111 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive | |
112 | */ | |
952e7760 SR |
113 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
114 | mtdcr (UIC0ER, 0x00000000); /* disable all ints */ | |
115 | mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ | |
116 | /* mtdcr(UIC0PR, 0xFFFFFF81); / set int polarities */ | |
117 | mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ | |
118 | mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ | |
119 | mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ | |
120 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ | |
37bd321e WD |
121 | |
122 | return 0; | |
123 | } | |
124 | ||
125 | ||
126 | /* ------------------------------------------------------------------------- */ | |
127 | ||
128 | /* | |
129 | * Check Board Identity: | |
130 | */ | |
131 | ||
132 | int checkboard (void) | |
133 | { | |
134 | int index; | |
135 | int len; | |
77ddac94 | 136 | char str[64]; |
cdb74977 | 137 | int i = getenv_f("serial#", str, sizeof (str)); |
37bd321e WD |
138 | |
139 | puts ("Board: "); | |
140 | ||
20aacbf0 SR |
141 | if (i == -1) { |
142 | puts ("### No HW ID - assuming AR405"); | |
143 | } else { | |
144 | puts(str); | |
37bd321e WD |
145 | } |
146 | ||
37bd321e WD |
147 | puts ("\nFPGA: "); |
148 | ||
149 | /* display infos on fpgaimage */ | |
150 | index = 15; | |
151 | for (i = 0; i < 4; i++) { | |
152 | len = fpgadata[index]; | |
153 | printf ("%s ", &(fpgadata[index + 1])); | |
154 | index += len + 3; | |
155 | } | |
156 | ||
157 | putc ('\n'); | |
158 | ||
20aacbf0 SR |
159 | /* |
160 | * Disable sleep mode in LXT971 | |
161 | */ | |
162 | lxt971_no_sleep(); | |
163 | ||
37bd321e WD |
164 | return 0; |
165 | } |