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affae2bf WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <command.h> | |
27 | #include <pci.h> | |
049216f0 | 28 | #include <asm/io.h> |
affae2bf WD |
29 | |
30 | #define OK 0 | |
31 | #define ERROR (-1) | |
32 | ||
33 | #define TRUE 1 | |
34 | #define FALSE 0 | |
35 | ||
36 | ||
37 | extern u_long pci9054_iobase; | |
38 | ||
39 | ||
40 | /*************************************************************************** | |
41 | * | |
42 | * Routines for PLX PCI9054 eeprom access | |
43 | * | |
44 | */ | |
45 | ||
8bde7f77 | 46 | static unsigned int PciEepromReadLongVPD (int offs) |
affae2bf | 47 | { |
8bde7f77 WD |
48 | unsigned int value; |
49 | unsigned int ret; | |
50 | int count; | |
51 | ||
6d0f6bcf | 52 | pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, |
8bde7f77 WD |
53 | (offs << 16) | 0x0003); |
54 | count = 0; | |
55 | ||
56 | for (;;) { | |
57 | udelay (10 * 1000); | |
6d0f6bcf | 58 | pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret); |
8bde7f77 WD |
59 | if ((ret & 0x80000000) != 0) { |
60 | break; | |
61 | } else { | |
62 | count++; | |
63 | if (count > 10) { | |
64 | printf ("\nTimeout: ret=%08x - Please try again!\n", ret); | |
65 | break; | |
66 | } | |
67 | } | |
68 | } | |
69 | ||
6d0f6bcf | 70 | pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value); |
8bde7f77 WD |
71 | |
72 | return value; | |
affae2bf WD |
73 | } |
74 | ||
75 | ||
8bde7f77 | 76 | static int PciEepromWriteLongVPD (int offs, unsigned int value) |
affae2bf | 77 | { |
8bde7f77 WD |
78 | unsigned int ret; |
79 | int count; | |
80 | ||
6d0f6bcf JCPV |
81 | pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value); |
82 | pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, | |
8bde7f77 WD |
83 | (offs << 16) | 0x80000003); |
84 | count = 0; | |
85 | ||
86 | for (;;) { | |
87 | udelay (10 * 1000); | |
6d0f6bcf | 88 | pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret); |
8bde7f77 WD |
89 | if ((ret & 0x80000000) == 0) { |
90 | break; | |
91 | } else { | |
92 | count++; | |
93 | if (count > 10) { | |
94 | printf ("\nTimeout: ret=%08x - Please try again!\n", ret); | |
95 | break; | |
96 | } | |
97 | } | |
98 | } | |
99 | ||
100 | return TRUE; | |
affae2bf WD |
101 | } |
102 | ||
103 | ||
8bde7f77 | 104 | static void showPci9054 (void) |
affae2bf | 105 | { |
8bde7f77 WD |
106 | int val; |
107 | int l, i; | |
108 | ||
109 | /* read 9054-values */ | |
110 | for (l = 0; l < 6; l++) { | |
111 | printf ("%02x: ", l * 0x10); | |
112 | for (i = 0; i < 4; i++) { | |
6d0f6bcf | 113 | pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, |
8bde7f77 | 114 | l * 16 + i * 4, |
77ddac94 | 115 | (unsigned int *)&val); |
8bde7f77 WD |
116 | printf ("%08x ", val); |
117 | } | |
118 | printf ("\n"); | |
119 | } | |
120 | printf ("\n"); | |
121 | ||
122 | for (l = 0; l < 7; l++) { | |
123 | printf ("%02x: ", l * 0x10); | |
124 | for (i = 0; i < 4; i++) | |
125 | printf ("%08x ", | |
126 | PciEepromReadLongVPD ((i + l * 4) * 4)); | |
127 | printf ("\n"); | |
128 | } | |
129 | printf ("\n"); | |
affae2bf WD |
130 | } |
131 | ||
132 | ||
8bde7f77 | 133 | static void updatePci9054 (void) |
affae2bf | 134 | { |
8bde7f77 | 135 | int val; |
affae2bf | 136 | |
8bde7f77 WD |
137 | /* |
138 | * Set EEPROM write-protect register to 0 | |
139 | */ | |
049216f0 MF |
140 | out_be32 ((void *)(pci9054_iobase + 0x0c), |
141 | in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff); | |
affae2bf | 142 | |
8bde7f77 WD |
143 | /* Long Serial EEPROM Load Registers... */ |
144 | val = PciEepromWriteLongVPD (0x00, 0x905410b5); | |
145 | val = PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */ | |
146 | val = PciEepromWriteLongVPD (0x08, 0x28140100); | |
affae2bf | 147 | |
8bde7f77 WD |
148 | val = PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */ |
149 | val = PciEepromWriteLongVPD (0x10, 0x00000000); | |
affae2bf | 150 | |
8bde7f77 WD |
151 | /* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */ |
152 | val = PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */ | |
153 | val = PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */ | |
affae2bf | 154 | |
8bde7f77 WD |
155 | val = PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */ |
156 | val = PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */ | |
affae2bf | 157 | |
8bde7f77 WD |
158 | val = PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */ |
159 | val = PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */ | |
affae2bf | 160 | |
8bde7f77 | 161 | val = PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */ |
affae2bf | 162 | |
8bde7f77 WD |
163 | val = PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */ |
164 | val = PciEepromWriteLongVPD (0x34, 0x00000000); | |
165 | val = PciEepromWriteLongVPD (0x38, 0x00000000); | |
affae2bf | 166 | |
8bde7f77 WD |
167 | val = PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */ |
168 | val = PciEepromWriteLongVPD (0x40, 0x00000000); | |
affae2bf | 169 | |
8bde7f77 WD |
170 | /* Extra Long Serial EEPROM Load Registers... */ |
171 | val = PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */ | |
affae2bf | 172 | |
8bde7f77 WD |
173 | /* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */ |
174 | /* Offset to LAS1: Group 1: 0x00040000 */ | |
175 | /* Group 2: 0x00080000 */ | |
176 | /* Group 3: 0x000c0000 */ | |
177 | val = PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */ | |
178 | val = PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */ | |
179 | val = PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */ | |
affae2bf | 180 | |
8bde7f77 | 181 | val = PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */ |
affae2bf | 182 | |
8bde7f77 | 183 | printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n"); |
affae2bf WD |
184 | } |
185 | ||
186 | ||
8bde7f77 | 187 | static void clearPci9054 (void) |
affae2bf | 188 | { |
8bde7f77 | 189 | int val; |
affae2bf | 190 | |
8bde7f77 WD |
191 | /* |
192 | * Set EEPROM write-protect register to 0 | |
193 | */ | |
049216f0 MF |
194 | out_be32 ((void *)(pci9054_iobase + 0x0c), |
195 | in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff); | |
affae2bf | 196 | |
8bde7f77 WD |
197 | /* Long Serial EEPROM Load Registers... */ |
198 | val = PciEepromWriteLongVPD (0x00, 0xffffffff); | |
199 | val = PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */ | |
affae2bf | 200 | |
8bde7f77 | 201 | printf ("Finished clearing PLX PCI9054 EEPROM!\n"); |
affae2bf WD |
202 | } |
203 | ||
204 | ||
205 | /* ------------------------------------------------------------------------- */ | |
8bde7f77 | 206 | int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc, |
54841ab5 | 207 | char * const argv[]) |
affae2bf | 208 | { |
8bde7f77 WD |
209 | if (strcmp (argv[1], "info") == 0) { |
210 | showPci9054 (); | |
211 | return 0; | |
212 | } | |
213 | ||
214 | if (strcmp (argv[1], "update") == 0) { | |
215 | updatePci9054 (); | |
216 | return 0; | |
217 | } | |
218 | ||
219 | if (strcmp (argv[1], "clear") == 0) { | |
220 | clearPci9054 (); | |
221 | return 0; | |
222 | } | |
223 | ||
47e26b1b | 224 | return cmd_usage(cmdtp); |
affae2bf WD |
225 | } |
226 | ||
0d498393 WD |
227 | U_BOOT_CMD( |
228 | pci9054, 3, 1, do_pci9054, | |
2fb2604d | 229 | "PLX PCI9054 EEPROM access", |
8bde7f77 | 230 | "pci9054 info - print EEPROM values\n" |
a89c33db | 231 | "pci9054 update - updates EEPROM with default values" |
8bde7f77 WD |
232 | ); |
233 | ||
affae2bf | 234 | /* ------------------------------------------------------------------------- */ |