[people/ms/u-boot.git] / board / esd / dasa_sim / dasa_sim.c

/*
 * (C) Copyright 2001
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <netdev.h>
#include "dasa_sim.h"

/* ------------------------------------------------------------------------- */

#undef FPGA_DEBUG

#define	_NOT_USED_	0xFFFFFFFF

/* ------------------------------------------------------------------------- */

/* fpga configuration data - generated by bit2inc */
static unsigned char fpgadata[] = {
#include "fpgadata.c"
};

#define FPGA_PRG_SLEEP         32	/* fpga program sleep-time */
#define LOAD_LONG(a)           a


/******************************************************************************
 *
 * sysFpgaBoot - Load fpga-image into fpga
 *
 */
static int fpgaBoot (void)
{
	int i, j, index, len;
	unsigned char b;
	int imageSize;

	imageSize = sizeof (fpgadata);

	/* display infos on fpgaimage */
	index = 15;
	for (i = 0; i < 4; i++) {
		len = fpgadata[index];
		index += len + 3;
	}

	/* search for preamble 0xFF2X */
	for (index = 0; index < imageSize - 1; index++) {
		if ((fpgadata[index] == 0xff)
			&& ((fpgadata[index + 1] & 0xf0) == 0x20))
			break;
	}

	/* enable cs1 instead of user0... */
	*(unsigned long *) 0x50000084 &= ~0x00000002;

#ifdef FPGA_DEBUG
	printf ("%s\n",
		((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
		"NOT DONE" : "DONE");
#endif

	/* init fpga by asserting and deasserting PROGRAM* (USER2)... */
	*(unsigned long *) 0x50000084 &= ~0x00000400;
	udelay (FPGA_PRG_SLEEP * 1000);

	*(unsigned long *) 0x50000084 |= 0x00000400;
	udelay (FPGA_PRG_SLEEP * 1000);

#ifdef FPGA_DEBUG
	printf ("%s\n",
		((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
		"NOT DONE" : "DONE");
#endif

	/* cs1: disable burst, disable ready */
	*(unsigned long *) 0x50000114 &= ~0x00000300;

	/* cs1: set write timing */
	*(unsigned long *) 0x50000118 |= 0x00010900;

	/* write configuration-data into fpga... */
	for (i = index; i < imageSize; i++) {
		b = fpgadata[i];
		for (j = 0; j < 8; j++) {
			*(unsigned long *) 0x30000000 =
				((b & 0x80) == 0x80)
				? LOAD_LONG (0x03030101)
				: LOAD_LONG (0x02020000);
			b <<= 1;
		}
	}

#ifdef FPGA_DEBUG
	printf ("%s\n",
		((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
		"NOT DONE" : "DONE");
#endif

	/* set cs1 to 32 bit data-width, disable burst, enable ready */
	*(unsigned long *) 0x50000114 |= 0x00000202;
	*(unsigned long *) 0x50000114 &= ~0x00000100;

	/* cs1: set iop access to little endian */
	*(unsigned long *) 0x50000114 &= ~0x00000010;

	/* cs1: set read and write timing */
	*(unsigned long *) 0x50000118 = 0x00010000;
	*(unsigned long *) 0x5000011c = 0x00010001;

#ifdef FPGA_DEBUG
	printf ("%s\n",
		((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
		"NOT DONE" : "DONE");
#endif

	/* wait for 30 ms... */
	udelay (30 * 1000);
	/* check if fpga's DONE signal - correctly booted ? */
	if ((*(unsigned long *) 0x50000084 & 0x00010000) == 0)
		return -1;

	return 0;
}


int board_early_init_f (void)
{
	/*
	 * Init pci regs
	 */
	*(unsigned long *) 0x50000304 = 0x02900007;	/* enable mem/io/master bits */
	*(unsigned long *) 0x500001b4 = 0x00000000;	/* disable pci interrupt output enable */
	*(unsigned long *) 0x50000354 = 0x00c05800;	/* disable emun interrupt output enable */
	*(unsigned long *) 0x50000344 = 0x00000000;	/* disable pme interrupt output enable */
	*(unsigned long *) 0x50000310 = 0x00000000;	/* pcibar0 */
	*(unsigned long *) 0x50000314 = 0x00000000;	/* pcibar1 */
	*(unsigned long *) 0x50000318 = 0x00000000;	/* pcibar2 */

	return 0;
}


/*
 * Check Board Identity:
 */

int checkboard (void)
{
	int index;
	int len;
	char str[64];
	int i = getenv_r ("serial#", str, sizeof (str));
	int fpga;
	unsigned short val;

	puts ("Board: ");

	/*
	 * Boot onboard FPGA
	 */
	fpga = fpgaBoot ();

	if (!i || strncmp (str, "DASA_SIM", 8)) {
		puts ("### No HW ID - assuming DASA_SIM");
	}

	puts (str);

	if (fpga == 0) {
		val = *(unsigned short *) 0x30000202;
		printf (" (Id=%d Version=%d Revision=%d)",
			(val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1);

		puts ("\nFPGA:  ");

		/* display infos on fpgaimage */
		index = 15;
		for (i = 0; i < 4; i++) {
			len = fpgadata[index];
			printf ("%s ", &(fpgadata[index + 1]));
			index += len + 3;
		}
	} else {
		puts ("\nFPGA:  Booting failed!");
	}

	putc ('\n');

	return 0;
}

phys_size_t initdram (int board_type)
{
	return (16 * 1024 * 1024);
}
Commit	Line	Data
16f21704 WD	1	/*
	2	* (C) Copyright 2001
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
8ca0b3f9	25	#include <netdev.h>
16f21704 WD	26	#include "dasa_sim.h"
	27
	28	/* ------------------------------------------------------------------------- */
	29
	30	#undef FPGA_DEBUG
	31
	32	#define _NOT_USED_ 0xFFFFFFFF
	33
	34	/* ------------------------------------------------------------------------- */
	35
	36	/* fpga configuration data - generated by bit2inc */
	37	static unsigned char fpgadata[] = {
	38	#include "fpgadata.c"
	39	};
	40
	41	#define FPGA_PRG_SLEEP 32 /* fpga program sleep-time */
	42	#define LOAD_LONG(a) a
	43
	44
	45	/******************************************************************************
	46	*
	47	* sysFpgaBoot - Load fpga-image into fpga
	48	*
	49	*/
	50	static int fpgaBoot (void)
	51	{
	52	int i, j, index, len;
	53	unsigned char b;
	54	int imageSize;
	55
	56	imageSize = sizeof (fpgadata);
	57
	58	/* display infos on fpgaimage */
	59	index = 15;
	60	for (i = 0; i < 4; i++) {
	61	len = fpgadata[index];
	62	index += len + 3;
	63	}
	64
	65	/* search for preamble 0xFF2X */
	66	for (index = 0; index < imageSize - 1; index++) {
	67	if ((fpgadata[index] == 0xff)
	68	&& ((fpgadata[index + 1] & 0xf0) == 0x20))
	69	break;
	70	}
	71
	72	/* enable cs1 instead of user0... */
	73	(unsigned long ) 0x50000084 &= ~0x00000002;
	74
	75	#ifdef FPGA_DEBUG
	76	printf ("%s\n",
049216f0 MF	77	((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
049216f0 MF	78	"NOT DONE" : "DONE");
16f21704 WD	79	#endif
	80
	81	/* init fpga by asserting and deasserting PROGRAM* (USER2)... */
	82	(unsigned long ) 0x50000084 &= ~0x00000400;
	83	udelay (FPGA_PRG_SLEEP * 1000);
	84
	85	(unsigned long ) 0x50000084 \|= 0x00000400;
	86	udelay (FPGA_PRG_SLEEP * 1000);
	87
	88	#ifdef FPGA_DEBUG
	89	printf ("%s\n",
049216f0 MF	90	((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
049216f0 MF	91	"NOT DONE" : "DONE");
16f21704 WD	92	#endif
	93
	94	/* cs1: disable burst, disable ready */
	95	(unsigned long ) 0x50000114 &= ~0x00000300;
	96
	97	/* cs1: set write timing */
	98	(unsigned long ) 0x50000118 \|= 0x00010900;
	99
	100	/* write configuration-data into fpga... */
	101	for (i = index; i < imageSize; i++) {
	102	b = fpgadata[i];
	103	for (j = 0; j < 8; j++) {
	104	(unsigned long ) 0x30000000 =
	105	((b & 0x80) == 0x80)
	106	? LOAD_LONG (0x03030101)
	107	: LOAD_LONG (0x02020000);
	108	b <<= 1;
	109	}
	110	}
	111
	112	#ifdef FPGA_DEBUG
	113	printf ("%s\n",
049216f0 MF	114	((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
049216f0 MF	115	"NOT DONE" : "DONE");
16f21704 WD	116	#endif
	117
	118	/* set cs1 to 32 bit data-width, disable burst, enable ready */
	119	(unsigned long ) 0x50000114 \|= 0x00000202;
	120	(unsigned long ) 0x50000114 &= ~0x00000100;
	121
	122	/* cs1: set iop access to little endian */
	123	(unsigned long ) 0x50000114 &= ~0x00000010;
	124
	125	/* cs1: set read and write timing */
	126	(unsigned long ) 0x50000118 = 0x00010000;
	127	(unsigned long ) 0x5000011c = 0x00010001;
	128
	129	#ifdef FPGA_DEBUG
	130	printf ("%s\n",
049216f0 MF	131	((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
049216f0 MF	132	"NOT DONE" : "DONE");
16f21704 WD	133	#endif
	134
	135	/* wait for 30 ms... */
	136	udelay (30 * 1000);
	137	/* check if fpga's DONE signal - correctly booted ? */
	138	if (((unsigned long ) 0x50000084 & 0x00010000) == 0)
	139	return -1;
	140
	141	return 0;
	142	}
	143
	144
c837dcb1	145	int board_early_init_f (void)
16f21704 WD	146	{
	147	/*
	148	* Init pci regs
	149	*/
	150	(unsigned long ) 0x50000304 = 0x02900007; /* enable mem/io/master bits */
	151	(unsigned long ) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */
	152	(unsigned long ) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */
	153	(unsigned long ) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */
	154	(unsigned long ) 0x50000310 = 0x00000000; /* pcibar0 */
	155	(unsigned long ) 0x50000314 = 0x00000000; /* pcibar1 */
	156	(unsigned long ) 0x50000318 = 0x00000000; /* pcibar2 */
	157
	158	return 0;
	159	}
	160
	161
	162	/*
	163	* Check Board Identity:
	164	*/
	165
	166	int checkboard (void)
	167	{
	168	int index;
	169	int len;
77ddac94	170	char str[64];
16f21704 WD	171	int i = getenv_r ("serial#", str, sizeof (str));
	172	int fpga;
	173	unsigned short val;
	174
	175	puts ("Board: ");
	176
	177	/*
	178	* Boot onboard FPGA
	179	*/
	180	fpga = fpgaBoot ();
	181
	182	if (!i \|\| strncmp (str, "DASA_SIM", 8)) {
	183	puts ("### No HW ID - assuming DASA_SIM");
	184	}
	185
	186	puts (str);
	187
	188	if (fpga == 0) {
	189	val = (unsigned short ) 0x30000202;
	190	printf (" (Id=%d Version=%d Revision=%d)",
	191	(val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1);
	192
	193	puts ("\nFPGA: ");
	194
	195	/* display infos on fpgaimage */
	196	index = 15;
	197	for (i = 0; i < 4; i++) {
	198	len = fpgadata[index];
	199	printf ("%s ", &(fpgadata[index + 1]));
	200	index += len + 3;
	201	}
	202	} else {
	203	puts ("\nFPGA: Booting failed!");
	204	}
	205
	206	putc ('\n');
	207
	208	return 0;
	209	}
	210
9973e3c6	211	phys_size_t initdram (int board_type)
16f21704 WD	212	{
	213	return (16 * 1024 * 1024);
	214	}