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5ce08eea SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <asm/processor.h> | |
26 | #include <command.h> | |
27 | #include <malloc.h> | |
28 | ||
d87080b7 | 29 | DECLARE_GLOBAL_DATA_PTR; |
5ce08eea SR |
30 | |
31 | /* fpga configuration data - not compressed, generated by bin2c */ | |
32 | const unsigned char fpgadata[] = | |
33 | { | |
34 | #include "fpgadata.c" | |
35 | }; | |
36 | int filesize = sizeof(fpgadata); | |
37 | ||
38 | ||
c837dcb1 | 39 | int board_early_init_f (void) |
5ce08eea SR |
40 | { |
41 | /* | |
42 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
43 | * IRQ 16 405GP internally generated; active low; level sensitive | |
44 | * IRQ 17-24 RESERVED | |
45 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive | |
46 | * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive | |
47 | * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive | |
48 | * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive | |
49 | * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive | |
50 | * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive | |
51 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive | |
52 | */ | |
53 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
54 | mtdcr(uicer, 0x00000000); /* disable all ints */ | |
55 | mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ | |
56 | mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ | |
57 | mtdcr(uictr, 0x10000000); /* set int trigger levels */ | |
58 | mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ | |
59 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
60 | ||
61 | /* | |
62 | * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us | |
63 | */ | |
64 | mtebc (epcr, 0xa8400000); /* ebc always driven */ | |
65 | ||
f2dfe44f SR |
66 | /* |
67 | * Reset CPLD via GPIO13 (CS4) pin | |
68 | */ | |
69 | out32(GPIO0_OR, in32(GPIO0_OR) & ~(0x80000000 >> 13)); | |
70 | udelay(1000); /* wait 1ms */ | |
71 | out32(GPIO0_OR, in32(GPIO0_OR) | (0x80000000 >> 13)); | |
72 | udelay(1000); /* wait 1ms */ | |
73 | ||
5ce08eea SR |
74 | return 0; |
75 | } | |
76 | ||
77 | ||
78 | /* ------------------------------------------------------------------------- */ | |
79 | ||
80 | int misc_init_f (void) | |
81 | { | |
82 | return 0; /* dummy implementation */ | |
83 | } | |
84 | ||
85 | ||
86 | int misc_init_r (void) | |
87 | { | |
f2dfe44f SR |
88 | /* adjust flash start and offset */ |
89 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
90 | gd->bd->bi_flashoffset = 0; | |
5ce08eea SR |
91 | |
92 | return (0); | |
93 | } | |
94 | ||
95 | ||
96 | /* | |
97 | * Check Board Identity: | |
98 | */ | |
99 | ||
100 | int checkboard (void) | |
101 | { | |
77ddac94 | 102 | char str[64]; |
5ce08eea SR |
103 | int i = getenv_r ("serial#", str, sizeof(str)); |
104 | unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe, | |
42d1f039 | 105 | 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf}; |
5ce08eea SR |
106 | unsigned char id1, id2; |
107 | ||
108 | puts ("Board: "); | |
109 | ||
110 | if (i == -1) { | |
111 | puts ("### No HW ID - assuming DP405"); | |
112 | } else { | |
113 | puts(str); | |
114 | } | |
115 | ||
116 | id1 = trans[(~(in32(GPIO0_IR) >> 5)) & 0x0000000f]; | |
117 | id2 = trans[(~(in32(GPIO0_IR) >> 9)) & 0x0000000f]; | |
f2dfe44f | 118 | printf(" (ID=0x%1X%1X, PLD=0x%02X)\n", id2, id1, in8(0xf0001000)); |
5ce08eea SR |
119 | |
120 | return 0; | |
121 | } | |
122 | ||
123 | /* ------------------------------------------------------------------------- */ | |
124 | ||
9973e3c6 | 125 | phys_size_t initdram (int board_type) |
5ce08eea SR |
126 | { |
127 | unsigned long val; | |
128 | ||
129 | mtdcr(memcfga, mem_mb0cf); | |
130 | val = mfdcr(memcfgd); | |
131 | ||
132 | #if 0 | |
133 | printf("\nmb0cf=%x\n", val); /* test-only */ | |
134 | printf("strap=%x\n", mfdcr(strap)); /* test-only */ | |
135 | #endif | |
136 | ||
137 | return (4*1024*1024 << ((val & 0x000e0000) >> 17)); | |
138 | } | |
139 | ||
140 | /* ------------------------------------------------------------------------- */ | |
141 | ||
142 | int testdram (void) | |
143 | { | |
144 | /* TODO: XXX XXX XXX */ | |
145 | printf ("test: 16 MB - ok\n"); | |
146 | ||
147 | return (0); | |
148 | } |