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15a08bc2 MF |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #include <common.h> | |
22 | #include <asm/processor.h> | |
23 | #include <asm/io.h> | |
24 | #include <asm/bitops.h> | |
25 | #include <command.h> | |
26 | #include <i2c.h> | |
b36df561 | 27 | #include <asm/ppc440.h> |
15a08bc2 MF |
28 | #include "du440.h" |
29 | ||
30 | DECLARE_GLOBAL_DATA_PTR; | |
31 | ||
6d0f6bcf | 32 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; |
15a08bc2 MF |
33 | extern ulong flash_get_size (ulong base, int banknum); |
34 | ||
35 | int usbhub_init(void); | |
36 | int dvi_init(void); | |
37 | int eeprom_write_enable (unsigned dev_addr, int state); | |
38 | int board_revision(void); | |
39 | ||
40 | static int du440_post_errors; | |
41 | ||
42 | int board_early_init_f(void) | |
43 | { | |
44 | u32 sdr0_cust0; | |
45 | u32 sdr0_pfc1, sdr0_pfc2; | |
46 | u32 reg; | |
47 | ||
d1c3b275 SR |
48 | mtdcr(EBC0_CFGADDR, EBC0_CFG); |
49 | mtdcr(EBC0_CFGDATA, 0xb8400000); | |
15a08bc2 MF |
50 | |
51 | /* | |
52 | * Setup the GPIO pins | |
53 | */ | |
6d0f6bcf JCPV |
54 | out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP); |
55 | out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP); | |
15a08bc2 | 56 | out_be32((void*)GPIO0_OSRL, 0x50055400); |
6a133d6a | 57 | out_be32((void*)GPIO0_OSRH, 0x55005000); |
15a08bc2 MF |
58 | out_be32((void*)GPIO0_TSRL, 0x50055400); |
59 | out_be32((void*)GPIO0_TSRH, 0x55005000); | |
60 | out_be32((void*)GPIO0_ISR1L, 0x50000000); | |
61 | out_be32((void*)GPIO0_ISR1H, 0x00000000); | |
62 | out_be32((void*)GPIO0_ISR2L, 0x00000000); | |
6a133d6a | 63 | out_be32((void*)GPIO0_ISR2H, 0x00000000); |
15a08bc2 MF |
64 | out_be32((void*)GPIO0_ISR3L, 0x00000000); |
65 | out_be32((void*)GPIO0_ISR3H, 0x00000000); | |
66 | ||
67 | out_be32((void*)GPIO1_OR, 0x00000000); | |
68 | out_be32((void*)GPIO1_TCR, 0xc2000000 | | |
6d0f6bcf JCPV |
69 | CONFIG_SYS_GPIO1_IORSTN | |
70 | CONFIG_SYS_GPIO1_IORST2N | | |
71 | CONFIG_SYS_GPIO1_LEDUSR1 | | |
72 | CONFIG_SYS_GPIO1_LEDUSR2 | | |
73 | CONFIG_SYS_GPIO1_LEDPOST | | |
74 | CONFIG_SYS_GPIO1_LEDDU); | |
75 | out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU); | |
6a133d6a | 76 | out_be32((void*)GPIO1_OSRL, 0x0c280000); |
15a08bc2 | 77 | out_be32((void*)GPIO1_OSRH, 0x00000000); |
6a133d6a | 78 | out_be32((void*)GPIO1_TSRL, 0xcc000000); |
15a08bc2 MF |
79 | out_be32((void*)GPIO1_TSRH, 0x00000000); |
80 | out_be32((void*)GPIO1_ISR1L, 0x00005550); | |
81 | out_be32((void*)GPIO1_ISR1H, 0x00000000); | |
82 | out_be32((void*)GPIO1_ISR2L, 0x00050000); | |
83 | out_be32((void*)GPIO1_ISR2H, 0x00000000); | |
84 | out_be32((void*)GPIO1_ISR3L, 0x01400000); | |
85 | out_be32((void*)GPIO1_ISR3H, 0x00000000); | |
86 | ||
87 | /* | |
88 | * Setup the interrupt controller polarities, triggers, etc. | |
89 | */ | |
952e7760 SR |
90 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
91 | mtdcr(UIC0ER, 0x00000000); /* disable all */ | |
92 | mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ | |
93 | mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ | |
94 | mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ | |
95 | mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ | |
96 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ | |
15a08bc2 MF |
97 | |
98 | /* | |
99 | * UIC1: | |
100 | * bit30: ext. Irq 1: PLD : int 32+30 | |
101 | */ | |
952e7760 SR |
102 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
103 | mtdcr(UIC1ER, 0x00000000); /* disable all */ | |
104 | mtdcr(UIC1CR, 0x00000000); /* all non-critical */ | |
105 | mtdcr(UIC1PR, 0xfffffffd); | |
106 | mtdcr(UIC1TR, 0x00000000); | |
107 | mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ | |
108 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ | |
15a08bc2 MF |
109 | |
110 | /* | |
111 | * UIC2 | |
112 | * bit3: ext. Irq 2: DCF77 : int 64+3 | |
113 | */ | |
952e7760 SR |
114 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ |
115 | mtdcr(UIC2ER, 0x00000000); /* disable all */ | |
116 | mtdcr(UIC2CR, 0x00000000); /* all non-critical */ | |
117 | mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ | |
118 | mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ | |
119 | mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ | |
120 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ | |
15a08bc2 MF |
121 | |
122 | /* select Ethernet pins */ | |
123 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
124 | mfsdr(SDR0_PFC2, sdr0_pfc2); | |
125 | ||
126 | /* setup EMAC bridge interface */ | |
127 | if (board_revision() == 0) { | |
128 | /* 1 x MII */ | |
129 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | | |
130 | SDR0_PFC1_SELECT_CONFIG_1_2; | |
131 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | | |
132 | SDR0_PFC2_SELECT_CONFIG_1_2; | |
133 | } else { | |
134 | /* 2 x SMII */ | |
135 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | | |
136 | SDR0_PFC1_SELECT_CONFIG_6; | |
137 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | | |
138 | SDR0_PFC2_SELECT_CONFIG_6; | |
139 | } | |
140 | ||
141 | /* enable 2nd IIC */ | |
142 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL; | |
143 | ||
144 | mtsdr(SDR0_PFC2, sdr0_pfc2); | |
145 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
146 | ||
147 | /* PCI arbiter enabled */ | |
d1c3b275 SR |
148 | mfsdr(SDR0_PCI0, reg); |
149 | mtsdr(SDR0_PCI0, 0x80000000 | reg); | |
15a08bc2 MF |
150 | |
151 | /* setup NAND FLASH */ | |
152 | mfsdr(SDR0_CUST0, sdr0_cust0); | |
153 | sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | | |
154 | SDR0_CUST0_NDFC_ENABLE | | |
155 | SDR0_CUST0_NDFC_BW_8_BIT | | |
156 | SDR0_CUST0_NDFC_ARE_MASK | | |
6d0f6bcf JCPV |
157 | (0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) | |
158 | (0x80000000 >> (28 + CONFIG_SYS_NAND1_CS)); | |
15a08bc2 MF |
159 | mtsdr(SDR0_CUST0, sdr0_cust0); |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
164 | int misc_init_r(void) | |
165 | { | |
166 | uint pbcr; | |
167 | int size_val = 0; | |
168 | u32 reg; | |
169 | unsigned long usb2d0cr = 0; | |
170 | unsigned long usb2phy0cr, usb2h0cr = 0; | |
171 | unsigned long sdr0_pfc1; | |
542b385a | 172 | unsigned long sdr0_srst0, sdr0_srst1; |
15a08bc2 MF |
173 | int i, j; |
174 | ||
175 | /* adjust flash start and offset */ | |
176 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
177 | gd->bd->bi_flashoffset = 0; | |
178 | ||
d1c3b275 SR |
179 | mtdcr(EBC0_CFGADDR, PB0CR); |
180 | pbcr = mfdcr(EBC0_CFGDATA); | |
15a08bc2 MF |
181 | size_val = ffs(gd->bd->bi_flashsize) - 21; |
182 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); | |
d1c3b275 SR |
183 | mtdcr(EBC0_CFGADDR, PB0CR); |
184 | mtdcr(EBC0_CFGDATA, pbcr); | |
15a08bc2 MF |
185 | |
186 | /* | |
187 | * Re-check to get correct base address | |
188 | */ | |
189 | flash_get_size(gd->bd->bi_flashstart, 0); | |
190 | ||
191 | /* | |
192 | * USB suff... | |
193 | */ | |
194 | /* SDR Setting */ | |
195 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
196 | mfsdr(SDR0_USB0, usb2d0cr); | |
197 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
198 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
199 | ||
200 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
201 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; | |
202 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; | |
203 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; | |
204 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; | |
205 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; | |
206 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; | |
207 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; | |
208 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; | |
209 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; | |
210 | ||
211 | /* An 8-bit/60MHz interface is the only possible alternative | |
212 | when connecting the Device to the PHY */ | |
213 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; | |
214 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; | |
215 | ||
216 | /* To enable the USB 2.0 Device function through the UTMI interface */ | |
217 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; | |
218 | ||
219 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; | |
220 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; | |
221 | ||
222 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
223 | mtsdr(SDR0_USB0, usb2d0cr); | |
224 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
225 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
226 | ||
542b385a MF |
227 | /* |
228 | * Take USB out of reset: | |
229 | * -Initial status = all cores are in reset | |
230 | * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores | |
231 | * -wait 1 ms | |
232 | * -deassert reset to PHY | |
233 | * -wait 1 ms | |
234 | * -deassert reset to HOST | |
235 | * -wait 4 ms | |
236 | * -deassert all other resets | |
237 | */ | |
238 | mfsdr(SDR0_SRST1, sdr0_srst1); | |
239 | sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \ | |
240 | SDR0_SRST1_P4OPB0 | \ | |
241 | SDR0_SRST1_OPBA2 | \ | |
242 | SDR0_SRST1_PLB42OPB1 | \ | |
243 | SDR0_SRST1_OPB2PLB40); | |
244 | mtsdr(SDR0_SRST1, sdr0_srst1); | |
245 | udelay(1000); | |
246 | ||
247 | mfsdr(SDR0_SRST1, sdr0_srst1); | |
248 | sdr0_srst1 &= ~SDR0_SRST1_USB20PHY; | |
249 | mtsdr(SDR0_SRST1, sdr0_srst1); | |
250 | udelay(1000); | |
251 | ||
252 | mfsdr(SDR0_SRST0, sdr0_srst0); | |
253 | sdr0_srst0 &= ~SDR0_SRST0_USB2H; | |
254 | mtsdr(SDR0_SRST0, sdr0_srst0); | |
255 | udelay(4000); | |
256 | ||
257 | /* finally all the other resets */ | |
15a08bc2 | 258 | mtsdr(SDR0_SRST1, 0x00000000); |
15a08bc2 MF |
259 | mtsdr(SDR0_SRST0, 0x00000000); |
260 | ||
261 | printf("USB: Host(int phy)\n"); | |
262 | ||
263 | /* | |
264 | * Clear PLB4A0_ACR[WRP] | |
265 | * This fix will make the MAL burst disabling patch for the Linux | |
266 | * EMAC driver obsolete. | |
267 | */ | |
5e7abce9 SR |
268 | reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; |
269 | mtdcr(PLB4A0_ACR, reg); | |
15a08bc2 MF |
270 | |
271 | /* | |
272 | * release IO-RST# | |
273 | * We have to wait at least 560ms until we may call usbhub_init | |
274 | */ | |
7c91f51a | 275 | out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | |
6d0f6bcf | 276 | CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N); |
15a08bc2 MF |
277 | |
278 | /* | |
279 | * flash USR1/2 LEDs (600ms) | |
280 | * This results in the necessary delay from IORST# until | |
281 | * calling usbhub_init will succeed | |
282 | */ | |
283 | for (j = 0; j < 3; j++) { | |
284 | out_be32((void*)GPIO1_OR, | |
6d0f6bcf JCPV |
285 | (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) | |
286 | CONFIG_SYS_GPIO1_LEDUSR1); | |
15a08bc2 MF |
287 | |
288 | for (i = 0; i < 100; i++) | |
289 | udelay(1000); | |
290 | ||
291 | out_be32((void*)GPIO1_OR, | |
6d0f6bcf JCPV |
292 | (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) | |
293 | CONFIG_SYS_GPIO1_LEDUSR2); | |
15a08bc2 MF |
294 | |
295 | for (i = 0; i < 100; i++) | |
296 | udelay(1000); | |
297 | } | |
298 | ||
299 | out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & | |
6d0f6bcf | 300 | ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2)); |
15a08bc2 MF |
301 | |
302 | if (usbhub_init()) | |
303 | du440_post_errors++; | |
304 | ||
305 | if (dvi_init()) | |
306 | du440_post_errors++; | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
311 | int pld_revision(void) | |
312 | { | |
bb57ad4b MF |
313 | out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00); |
314 | return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK); | |
15a08bc2 MF |
315 | } |
316 | ||
317 | int board_revision(void) | |
318 | { | |
6d0f6bcf JCPV |
319 | int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK) |
320 | >> CONFIG_SYS_GPIO1_HWVER_SHIFT); | |
15a08bc2 MF |
321 | |
322 | return ((rpins & 1) << 3) | ((rpins & 2) << 1) | | |
323 | ((rpins & 4) >> 1) | ((rpins & 8) >> 3); | |
324 | } | |
325 | ||
326 | #if defined(CONFIG_SHOW_ACTIVITY) | |
327 | void board_show_activity (ulong timestamp) | |
328 | { | |
329 | if ((timestamp % 100) == 0) | |
330 | out_be32((void*)GPIO1_OR, | |
6d0f6bcf | 331 | in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1); |
15a08bc2 MF |
332 | } |
333 | ||
334 | void show_activity(int arg) | |
335 | { | |
336 | } | |
337 | #endif /* CONFIG_SHOW_ACTIVITY */ | |
338 | ||
339 | int du440_phy_addr(int devnum) | |
340 | { | |
341 | if (board_revision() == 0) | |
342 | return devnum; | |
343 | ||
344 | return devnum + 1; | |
345 | } | |
346 | ||
347 | int checkboard(void) | |
348 | { | |
349 | char serno[32]; | |
350 | ||
351 | puts("Board: DU440"); | |
352 | ||
cdb74977 | 353 | if (getenv_f("serial#", serno, sizeof(serno)) > 0) { |
15a08bc2 MF |
354 | puts(", serial# "); |
355 | puts(serno); | |
356 | } | |
357 | ||
358 | printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n", | |
359 | board_revision(), pld_revision()); | |
360 | return (0); | |
361 | } | |
15a08bc2 | 362 | |
15a08bc2 MF |
363 | int last_stage_init(void) |
364 | { | |
365 | int e, i; | |
366 | ||
367 | /* everyting is ok: turn on POST-LED */ | |
6d0f6bcf | 368 | out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST); |
15a08bc2 MF |
369 | |
370 | /* slowly blink on errors and finally keep LED off */ | |
371 | for (e = 0; e < du440_post_errors; e++) { | |
372 | out_be32((void*)GPIO1_OR, | |
6d0f6bcf | 373 | in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST); |
15a08bc2 MF |
374 | |
375 | for (i = 0; i < 500; i++) | |
376 | udelay(1000); | |
377 | ||
378 | out_be32((void*)GPIO1_OR, | |
6d0f6bcf | 379 | in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST); |
15a08bc2 MF |
380 | |
381 | for (i = 0; i < 500; i++) | |
382 | udelay(1000); | |
383 | } | |
384 | ||
385 | return 0; | |
386 | } | |
387 | ||
15a08bc2 MF |
388 | /* |
389 | * read field strength from I2C ADC | |
390 | */ | |
391 | int dcf77_status(void) | |
392 | { | |
393 | unsigned int oldbus; | |
394 | uchar u[2]; | |
395 | int mv; | |
396 | ||
397 | oldbus = I2C_GET_BUS(); | |
398 | I2C_SET_BUS(1); | |
399 | ||
400 | if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) { | |
401 | I2C_SET_BUS(oldbus); | |
402 | return -1; | |
403 | } | |
404 | ||
405 | mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024; | |
406 | ||
407 | I2C_SET_BUS(oldbus); | |
408 | return mv; | |
409 | } | |
410 | ||
54841ab5 | 411 | int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
15a08bc2 MF |
412 | { |
413 | int mv; | |
414 | u32 pin, pinold; | |
415 | unsigned long long t1, t2; | |
416 | bd_t *bd = gd->bd; | |
417 | ||
418 | printf("DCF77: "); | |
419 | mv = dcf77_status(); | |
420 | if (mv > 0) | |
421 | printf("signal=%d mV\n", mv); | |
422 | else | |
423 | printf("ERROR - no signal\n"); | |
424 | ||
425 | t1 = t2 = 0; | |
6d0f6bcf | 426 | pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77; |
15a08bc2 | 427 | while (!ctrlc()) { |
6d0f6bcf | 428 | pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77; |
15a08bc2 MF |
429 | if (pin && !pinold) { /* bit start */ |
430 | t1 = get_ticks(); | |
431 | if (t2 && ((unsigned int)(t1 - t2) / | |
432 | (bd->bi_procfreq / 1000) >= 1800)) | |
433 | printf("Start of minute\n"); | |
434 | ||
435 | t2 = t1; | |
436 | } | |
437 | if (t1 && !pin && pinold) { /* bit end */ | |
438 | printf("%5d\n", (unsigned int)(get_ticks() - t1) / | |
439 | (bd->bi_procfreq / 1000)); | |
440 | } | |
441 | pinold = pin; | |
442 | } | |
443 | ||
444 | printf("Abort\n"); | |
445 | return 0; | |
446 | } | |
447 | U_BOOT_CMD( | |
448 | dcf77, 1, 1, do_dcf77, | |
2fb2604d | 449 | "Check DCF77 receiver", |
a89c33db WD |
450 | "" |
451 | ); | |
15a08bc2 MF |
452 | |
453 | /* | |
454 | * initialize USB hub via I2C1 | |
455 | */ | |
456 | int usbhub_init(void) | |
457 | { | |
458 | int reg; | |
459 | int ret = 0; | |
460 | unsigned int oldbus; | |
461 | uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3, | |
462 | 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64, | |
463 | 0x32}; | |
464 | uchar stcd; | |
465 | ||
466 | printf("Hub: "); | |
467 | ||
468 | oldbus = I2C_GET_BUS(); | |
469 | I2C_SET_BUS(1); | |
470 | ||
471 | for (reg = 0; reg < sizeof(u); reg++) | |
472 | if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) { | |
473 | ret = -1; | |
474 | break; | |
475 | } | |
476 | ||
477 | if (ret == 0) { | |
478 | stcd = 0x03; | |
479 | if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1)) | |
480 | ret = -1; | |
481 | } | |
482 | ||
483 | if (ret == 0) | |
484 | printf("initialized\n"); | |
485 | else | |
486 | printf("failed - cannot initialize USB hub\n"); | |
487 | ||
488 | I2C_SET_BUS(oldbus); | |
489 | return ret; | |
490 | } | |
491 | ||
54841ab5 | 492 | int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
15a08bc2 MF |
493 | { |
494 | usbhub_init(); | |
495 | return 0; | |
496 | } | |
497 | U_BOOT_CMD( | |
498 | hubinit, 1, 1, do_hubinit, | |
2fb2604d | 499 | "Initialize USB hub", |
a89c33db WD |
500 | "" |
501 | ); | |
15a08bc2 | 502 | |
6d0f6bcf | 503 | #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3 |
15a08bc2 MF |
504 | int boot_eeprom_write (unsigned dev_addr, |
505 | unsigned offset, | |
506 | uchar *buffer, | |
507 | unsigned cnt) | |
508 | { | |
509 | unsigned end = offset + cnt; | |
510 | unsigned blk_off; | |
511 | int rcode = 0; | |
512 | ||
6d0f6bcf | 513 | #if defined(CONFIG_SYS_EEPROM_WREN) |
15a08bc2 MF |
514 | eeprom_write_enable(dev_addr, 1); |
515 | #endif | |
516 | /* | |
517 | * Write data until done or would cross a write page boundary. | |
518 | * We must write the address again when changing pages | |
519 | * because the address counter only increments within a page. | |
520 | */ | |
521 | ||
522 | while (offset < end) { | |
523 | unsigned alen, len; | |
524 | unsigned maxlen; | |
525 | ||
526 | uchar addr[2]; | |
527 | ||
528 | blk_off = offset & 0xFF; /* block offset */ | |
529 | ||
530 | addr[0] = offset >> 8; /* block number */ | |
531 | addr[1] = blk_off; /* block offset */ | |
532 | alen = 2; | |
533 | addr[0] |= dev_addr; /* insert device address */ | |
534 | ||
535 | len = end - offset; | |
536 | ||
537 | /* | |
538 | * For a FRAM device there is no limit on the number of the | |
539 | * bytes that can be ccessed with the single read or write | |
540 | * operation. | |
541 | */ | |
6d0f6bcf | 542 | #if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS) |
15a08bc2 | 543 | |
6d0f6bcf | 544 | #define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS) |
15a08bc2 MF |
545 | #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1)) |
546 | ||
547 | maxlen = BOOT_EEPROM_PAGE_SIZE - | |
548 | BOOT_EEPROM_PAGE_OFFSET(blk_off); | |
549 | #else | |
550 | maxlen = 0x100 - blk_off; | |
551 | #endif | |
552 | if (maxlen > I2C_RXTX_LEN) | |
553 | maxlen = I2C_RXTX_LEN; | |
554 | ||
555 | if (len > maxlen) | |
556 | len = maxlen; | |
557 | ||
558 | if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0) | |
559 | rcode = 1; | |
560 | ||
561 | buffer += len; | |
562 | offset += len; | |
563 | ||
6d0f6bcf JCPV |
564 | #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) |
565 | udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); | |
15a08bc2 MF |
566 | #endif |
567 | } | |
6d0f6bcf | 568 | #if defined(CONFIG_SYS_EEPROM_WREN) |
15a08bc2 MF |
569 | eeprom_write_enable(dev_addr, 0); |
570 | #endif | |
571 | return rcode; | |
572 | } | |
573 | ||
54841ab5 | 574 | int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
15a08bc2 MF |
575 | { |
576 | ulong sdsdp[4]; | |
577 | ||
578 | if (argc > 1) { | |
579 | if (!strcmp(argv[1], "533")) { | |
580 | printf("Bootstrapping for 533MHz\n"); | |
581 | sdsdp[0] = 0x87788252; | |
582 | /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */ | |
583 | sdsdp[1] = 0x095fa030; | |
584 | sdsdp[2] = 0x40082350; | |
585 | sdsdp[3] = 0x0d050000; | |
586 | } else if (!strcmp(argv[1], "533-66")) { | |
587 | printf("Bootstrapping for 533MHz (66MHz PCI)\n"); | |
588 | sdsdp[0] = 0x87788252; | |
589 | /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */ | |
590 | sdsdp[1] = 0x0957a030; | |
591 | sdsdp[2] = 0x40082350; | |
592 | sdsdp[3] = 0x0d050000; | |
593 | } else if (!strcmp(argv[1], "667")) { | |
594 | printf("Bootstrapping for 667MHz\n"); | |
595 | sdsdp[0] = 0x8778a256; | |
596 | /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */ | |
597 | sdsdp[1] = 0x0947a030; | |
598 | /* PLB-PCI-divider = 3 : sync PCI clock=44MHz | |
599 | * -> not working when overclocking 533MHz chips | |
600 | * -> untested on 667MHz chips */ | |
601 | /* sdsdp[1]=0x095fa030; */ | |
602 | sdsdp[2] = 0x40082350; | |
603 | sdsdp[3] = 0x0d050000; | |
df8c1ce1 MF |
604 | } else if (!strcmp(argv[1], "667-166")) { |
605 | printf("Bootstrapping for 667-166MHz\n"); | |
606 | sdsdp[0] = 0x8778a252; | |
607 | sdsdp[1] = 0x09d7a030; | |
608 | sdsdp[2] = 0x40082350; | |
609 | sdsdp[3] = 0x0d050000; | |
15a08bc2 MF |
610 | } |
611 | } else { | |
612 | printf("Bootstrapping for 533MHz (default)\n"); | |
613 | sdsdp[0] = 0x87788252; | |
614 | /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */ | |
615 | sdsdp[1] = 0x095fa030; | |
616 | sdsdp[2] = 0x40082350; | |
617 | sdsdp[3] = 0x0d050000; | |
618 | } | |
619 | ||
620 | printf("Writing boot EEPROM ...\n"); | |
6d0f6bcf | 621 | if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, |
15a08bc2 MF |
622 | 0, (uchar*)sdsdp, 16) != 0) |
623 | printf("boot_eeprom_write failed\n"); | |
624 | else | |
625 | printf("done (dump via 'i2c md 52 0.1 10')\n"); | |
626 | ||
627 | return 0; | |
628 | } | |
629 | U_BOOT_CMD( | |
630 | sbe, 2, 0, do_setup_boot_eeprom, | |
2fb2604d | 631 | "setup boot eeprom", |
a89c33db WD |
632 | "" |
633 | ); | |
15a08bc2 | 634 | |
6d0f6bcf | 635 | #if defined(CONFIG_SYS_EEPROM_WREN) |
15a08bc2 MF |
636 | /* |
637 | * Input: <dev_addr> I2C address of EEPROM device to enable. | |
638 | * <state> -1: deliver current state | |
639 | * 0: disable write | |
640 | * 1: enable write | |
641 | * Returns: -1: wrong device address | |
642 | * 0: dis-/en- able done | |
643 | * 0/1: current state if <state> was -1. | |
644 | */ | |
645 | int eeprom_write_enable (unsigned dev_addr, int state) | |
646 | { | |
6d0f6bcf JCPV |
647 | if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) && |
648 | (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) | |
15a08bc2 MF |
649 | return -1; |
650 | else { | |
651 | switch (state) { | |
652 | case 1: | |
653 | /* Enable write access, clear bit GPIO_SINT2. */ | |
654 | out_be32((void*)GPIO0_OR, | |
6d0f6bcf | 655 | in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP); |
15a08bc2 MF |
656 | state = 0; |
657 | break; | |
658 | case 0: | |
659 | /* Disable write access, set bit GPIO_SINT2. */ | |
660 | out_be32((void*)GPIO0_OR, | |
6d0f6bcf | 661 | in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP); |
15a08bc2 MF |
662 | state = 0; |
663 | break; | |
664 | default: | |
665 | /* Read current status back. */ | |
666 | state = (0 == (in_be32((void*)GPIO0_OR) & | |
6d0f6bcf | 667 | CONFIG_SYS_GPIO0_EP_EEP)); |
15a08bc2 MF |
668 | break; |
669 | } | |
670 | } | |
671 | return state; | |
672 | } | |
673 | ||
54841ab5 | 674 | int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
15a08bc2 MF |
675 | { |
676 | int query = argc == 1; | |
677 | int state = 0; | |
678 | ||
679 | if (query) { | |
680 | /* Query write access state. */ | |
6d0f6bcf | 681 | state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1); |
15a08bc2 MF |
682 | if (state < 0) |
683 | puts ("Query of write access state failed.\n"); | |
684 | else { | |
685 | printf ("Write access for device 0x%0x is %sabled.\n", | |
6d0f6bcf | 686 | CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); |
15a08bc2 MF |
687 | state = 0; |
688 | } | |
689 | } else { | |
690 | if ('0' == argv[1][0]) { | |
691 | /* Disable write access. */ | |
6d0f6bcf | 692 | state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0); |
15a08bc2 MF |
693 | } else { |
694 | /* Enable write access. */ | |
6d0f6bcf | 695 | state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1); |
15a08bc2 MF |
696 | } |
697 | if (state < 0) | |
698 | puts ("Setup of write access state failed.\n"); | |
699 | } | |
700 | ||
701 | return state; | |
702 | } | |
703 | ||
704 | U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, | |
a89c33db WD |
705 | "Enable / disable / query EEPROM write access", |
706 | "" | |
707 | ); | |
6d0f6bcf | 708 | #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ |
15a08bc2 MF |
709 | |
710 | static int got_pldirq; | |
711 | ||
712 | static int pld_interrupt(u32 arg) | |
713 | { | |
714 | int rc = -1; /* not for us */ | |
bb57ad4b | 715 | u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE); |
15a08bc2 MF |
716 | |
717 | /* check for PLD interrupt */ | |
718 | if (status & PWR_INT_FLAG) { | |
719 | /* reset this int */ | |
bb57ad4b | 720 | out_8((void *)CONFIG_SYS_CPLD_BASE, 0); |
15a08bc2 MF |
721 | rc = 0; |
722 | got_pldirq = 1; /* trigger backend */ | |
723 | } | |
724 | ||
725 | return rc; | |
726 | } | |
727 | ||
54841ab5 | 728 | int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
15a08bc2 MF |
729 | { |
730 | got_pldirq = 0; | |
731 | ||
732 | /* clear any pending interrupt */ | |
bb57ad4b | 733 | out_8((void *)CONFIG_SYS_CPLD_BASE, 0); |
15a08bc2 MF |
734 | |
735 | irq_install_handler(CPLD_IRQ, | |
736 | (interrupt_handler_t *)pld_interrupt, 0); | |
737 | ||
738 | printf("Waiting ...\n"); | |
739 | while(!got_pldirq) { | |
740 | /* Abort if ctrl-c was pressed */ | |
741 | if (ctrlc()) { | |
742 | puts("\nAbort\n"); | |
743 | break; | |
744 | } | |
745 | } | |
746 | if (got_pldirq) { | |
747 | printf("Got interrupt!\n"); | |
748 | printf("Power %sready!\n", | |
bb57ad4b MF |
749 | in_8((void *)CONFIG_SYS_CPLD_BASE) & |
750 | PWR_RDY ? "":"NOT "); | |
15a08bc2 MF |
751 | } |
752 | ||
753 | irq_free_handler(CPLD_IRQ); | |
754 | return 0; | |
755 | } | |
756 | U_BOOT_CMD( | |
757 | wpi, 1, 1, do_waitpwrirq, | |
2fb2604d | 758 | "Wait for power change interrupt", |
a89c33db WD |
759 | "" |
760 | ); | |
15a08bc2 MF |
761 | |
762 | /* | |
763 | * initialize DVI panellink transmitter | |
764 | */ | |
765 | int dvi_init(void) | |
766 | { | |
767 | int i; | |
768 | int ret = 0; | |
769 | unsigned int oldbus; | |
770 | uchar u[] = {0x08, 0x34, | |
771 | 0x09, 0x20, | |
772 | 0x0a, 0x90, | |
773 | 0x0c, 0x89, | |
774 | 0x08, 0x35}; | |
775 | ||
776 | printf("DVI: "); | |
777 | ||
778 | oldbus = I2C_GET_BUS(); | |
779 | I2C_SET_BUS(0); | |
780 | ||
781 | for (i = 0; i < sizeof(u); i += 2) | |
782 | if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) { | |
783 | ret = -1; | |
784 | break; | |
785 | } | |
786 | ||
787 | if (ret == 0) | |
788 | printf("initialized\n"); | |
789 | else | |
790 | printf("failed - cannot initialize DVI transmitter\n"); | |
791 | ||
792 | I2C_SET_BUS(oldbus); | |
793 | return ret; | |
794 | } | |
795 | ||
54841ab5 | 796 | int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
15a08bc2 MF |
797 | { |
798 | dvi_init(); | |
799 | return 0; | |
800 | } | |
801 | U_BOOT_CMD( | |
802 | dviinit, 1, 1, do_dviinit, | |
2fb2604d | 803 | "Initialize DVI Panellink transmitter", |
a89c33db WD |
804 | "" |
805 | ); | |
15a08bc2 MF |
806 | |
807 | /* | |
808 | * TODO: 'time' command might be useful for others as well. | |
809 | * Move to 'common' directory. | |
810 | */ | |
54841ab5 | 811 | int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
15a08bc2 MF |
812 | { |
813 | unsigned long long start, end; | |
6d0f6bcf | 814 | char c, cmd[CONFIG_SYS_CBSIZE]; |
15a08bc2 MF |
815 | char *p, *d = cmd; |
816 | int ret, i; | |
817 | ulong us; | |
818 | ||
819 | for (i = 1; i < argc; i++) { | |
820 | p = argv[i]; | |
821 | ||
822 | if (i > 1) | |
823 | *d++ = ' '; | |
824 | ||
825 | while ((c = *p++) != '\0') { | |
826 | *d++ = c; | |
827 | } | |
828 | } | |
829 | *d = '\0'; | |
830 | ||
831 | start = get_ticks(); | |
53071532 | 832 | ret = run_command(cmd, 0); |
15a08bc2 MF |
833 | end = get_ticks(); |
834 | ||
b002144e | 835 | printf("ticks=%ld\n", (ulong)(end - start)); |
15a08bc2 | 836 | us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000)); |
b002144e | 837 | printf("usec=%ld\n", us); |
15a08bc2 MF |
838 | |
839 | return ret; | |
840 | } | |
841 | U_BOOT_CMD( | |
6d0f6bcf | 842 | time, CONFIG_SYS_MAXARGS, 1, do_time, |
2fb2604d | 843 | "run command and output execution time", |
a89c33db WD |
844 | "" |
845 | ); | |
15a08bc2 MF |
846 | |
847 | extern void video_hw_rectfill ( | |
848 | unsigned int bpp, /* bytes per pixel */ | |
849 | unsigned int dst_x, /* dest pos x */ | |
850 | unsigned int dst_y, /* dest pos y */ | |
851 | unsigned int dim_x, /* frame width */ | |
852 | unsigned int dim_y, /* frame height */ | |
853 | unsigned int color /* fill color */ | |
854 | ); | |
855 | ||
856 | /* | |
857 | * graphics demo | |
858 | * draw rectangles using pseudorandom number generator | |
859 | * (see http://www.embedded.com/columns/technicalinsights/20900500) | |
860 | */ | |
861 | unsigned int rprime = 9972; | |
862 | static unsigned int r; | |
863 | static unsigned int Y; | |
864 | ||
865 | unsigned int prng(unsigned int max) | |
866 | { | |
867 | if (r == 0 || r == 1 || r == -1) | |
868 | r = rprime; /* keep from getting stuck */ | |
869 | ||
870 | r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */ | |
871 | Y = (r >> 16) % max; /* choose upper bits and reduce */ | |
872 | return Y; | |
873 | } | |
874 | ||
54841ab5 | 875 | int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
15a08bc2 MF |
876 | { |
877 | unsigned int color; | |
878 | unsigned int x, y, dx, dy; | |
879 | ||
880 | while (!ctrlc()) { | |
881 | x = prng(1280 - 1); | |
882 | y = prng(1024 - 1); | |
883 | dx = prng(1280- x - 1); | |
884 | dy = prng(1024 - y - 1); | |
885 | color = prng(0x10000); | |
886 | video_hw_rectfill(2, x, y, dx, dy, color); | |
887 | } | |
888 | ||
889 | return 0; | |
890 | } | |
891 | U_BOOT_CMD( | |
6d0f6bcf | 892 | gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo, |
2fb2604d | 893 | "demo", |
a89c33db WD |
894 | "" |
895 | ); |