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Commit | Line | Data |
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a65cb682 SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
a65cb682 SR |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <asm/processor.h> | |
bb57ad4b | 10 | #include <asm/io.h> |
a65cb682 SR |
11 | #include <command.h> |
12 | #include <malloc.h> | |
13 | ||
d87080b7 | 14 | DECLARE_GLOBAL_DATA_PTR; |
31193c2c SR |
15 | |
16 | extern void lxt971_no_sleep(void); | |
a65cb682 | 17 | |
47b1e3d7 SR |
18 | int board_revision(void) |
19 | { | |
20 | unsigned long osrl_reg; | |
21 | unsigned long isr1l_reg; | |
22 | unsigned long tcr_reg; | |
23 | unsigned long value; | |
24 | ||
25 | /* | |
26 | * Get version of HUB405 board from GPIO's | |
27 | */ | |
28 | ||
29 | /* | |
30 | * Setup GPIO pin(s) (IRQ6/GPIO23) | |
31 | */ | |
bb57ad4b MF |
32 | osrl_reg = in_be32((void *)GPIO0_OSRH); |
33 | isr1l_reg = in_be32((void *)GPIO0_ISR1H); | |
34 | tcr_reg = in_be32((void *)GPIO0_TCR); | |
35 | out_be32((void *)GPIO0_OSRH, osrl_reg & ~0x00030000); /* output select */ | |
36 | out_be32((void *)GPIO0_ISR1H, isr1l_reg | 0x00030000); /* input select */ | |
37 | out_be32((void *)GPIO0_TCR, tcr_reg & ~0x00000100); /* select input */ | |
47b1e3d7 SR |
38 | |
39 | udelay(1000); /* wait some time before reading input */ | |
bb57ad4b | 40 | value = in_be32((void *)GPIO0_IR) & 0x00000100; /* get config bits */ |
47b1e3d7 SR |
41 | |
42 | /* | |
43 | * Restore GPIO settings | |
44 | */ | |
bb57ad4b MF |
45 | out_be32((void *)GPIO0_OSRH, osrl_reg); /* output select */ |
46 | out_be32((void *)GPIO0_ISR1H, isr1l_reg); /* input select */ | |
47 | out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */ | |
47b1e3d7 SR |
48 | |
49 | if (value & 0x00000100) { | |
50 | /* Revision 1.1 or 1.2 detected */ | |
51 | return 1; | |
52 | } | |
53 | ||
54 | /* Revision 1.0 */ | |
55 | return 0; | |
56 | } | |
57 | ||
58 | ||
c837dcb1 | 59 | int board_early_init_f (void) |
a65cb682 SR |
60 | { |
61 | /* | |
62 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
63 | * IRQ 16 405GP internally generated; active low; level sensitive | |
64 | * IRQ 17-24 RESERVED | |
65 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive | |
66 | * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive | |
67 | * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive | |
68 | * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive | |
69 | * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive | |
70 | * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive | |
71 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive | |
72 | */ | |
952e7760 SR |
73 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
74 | mtdcr(UIC0ER, 0x00000000); /* disable all ints */ | |
75 | mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ | |
76 | mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */ | |
77 | mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ | |
78 | mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ | |
79 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ | |
a65cb682 SR |
80 | |
81 | /* | |
82 | * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us | |
83 | */ | |
d1c3b275 | 84 | mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ |
a65cb682 SR |
85 | |
86 | return 0; | |
87 | } | |
88 | ||
bb57ad4b | 89 | #define LED_REG (DUART0_BA + 0x20) |
a65cb682 SR |
90 | int misc_init_r (void) |
91 | { | |
31193c2c SR |
92 | unsigned long val; |
93 | int delay, flashcnt; | |
94 | char *str; | |
47b1e3d7 | 95 | char hw_rev[4]; |
a65cb682 SR |
96 | |
97 | /* | |
98 | * Enable interrupts in exar duart mcr[3] | |
99 | */ | |
bb57ad4b MF |
100 | out_8((void *)(DUART0_BA + 4), 0x08); |
101 | out_8((void *)(DUART1_BA + 4), 0x08); | |
102 | out_8((void *)(DUART2_BA + 4), 0x08); | |
103 | out_8((void *)(DUART3_BA + 4), 0x08); | |
a65cb682 | 104 | |
efe2a4d5 | 105 | /* |
31193c2c SR |
106 | * Set RS232/RS422 control (RS232 = high on GPIO) |
107 | */ | |
bb57ad4b MF |
108 | val = in_be32((void *)GPIO0_OR); |
109 | val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 | | |
110 | CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232); | |
31193c2c SR |
111 | |
112 | str = getenv("phys0"); | |
113 | if (!str || (str && (str[0] == '0'))) | |
6d0f6bcf | 114 | val |= CONFIG_SYS_UART2_RS232; |
31193c2c SR |
115 | |
116 | str = getenv("phys1"); | |
117 | if (!str || (str && (str[0] == '0'))) | |
6d0f6bcf | 118 | val |= CONFIG_SYS_UART3_RS232; |
31193c2c SR |
119 | |
120 | str = getenv("phys2"); | |
121 | if (!str || (str && (str[0] == '0'))) | |
6d0f6bcf | 122 | val |= CONFIG_SYS_UART4_RS232; |
31193c2c SR |
123 | |
124 | str = getenv("phys3"); | |
125 | if (!str || (str && (str[0] == '0'))) | |
6d0f6bcf | 126 | val |= CONFIG_SYS_UART5_RS232; |
31193c2c | 127 | |
bb57ad4b | 128 | out_be32((void *)GPIO0_OR, val); |
31193c2c | 129 | |
31193c2c SR |
130 | /* |
131 | * check board type and setup AP power | |
132 | */ | |
133 | str = getenv("bd_type"); /* this is only set on non prototype hardware */ | |
134 | if (str != NULL) { | |
47b1e3d7 | 135 | if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) { |
31193c2c SR |
136 | unsigned char led_reg_default = 0; |
137 | str = getenv("ap_pwr"); | |
138 | if (!str || (str && (str[0] == '1'))) | |
139 | led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */ | |
140 | ||
141 | /* | |
47b1e3d7 | 142 | * Flash LEDs |
31193c2c SR |
143 | */ |
144 | for (flashcnt = 0; flashcnt < 3; flashcnt++) { | |
bb57ad4b MF |
145 | /* LED_A..D off */ |
146 | out_8((void *)LED_REG, led_reg_default); | |
31193c2c SR |
147 | for (delay = 0; delay < 100; delay++) |
148 | udelay(1000); | |
bb57ad4b MF |
149 | /* LED_A..D on */ |
150 | out_8((void *)LED_REG, led_reg_default | 0xf0); | |
31193c2c SR |
151 | for (delay = 0; delay < 50; delay++) |
152 | udelay(1000); | |
153 | } | |
bb57ad4b | 154 | out_8((void *)LED_REG, led_reg_default); |
31193c2c SR |
155 | } |
156 | } | |
157 | ||
158 | /* | |
159 | * Reset external DUARTs | |
160 | */ | |
bb57ad4b MF |
161 | out_be32((void *)GPIO0_OR, |
162 | in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */ | |
31193c2c | 163 | udelay(10); /* wait 10us */ |
bb57ad4b MF |
164 | out_be32((void *)GPIO0_OR, |
165 | in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */ | |
31193c2c SR |
166 | udelay(1000); /* wait 1ms */ |
167 | ||
47b1e3d7 SR |
168 | /* |
169 | * Store hardware revision in environment for further processing | |
170 | */ | |
171 | sprintf(hw_rev, "1.%ld", gd->board_type); | |
172 | setenv("hw_rev", hw_rev); | |
a65cb682 SR |
173 | return (0); |
174 | } | |
175 | ||
176 | ||
177 | /* | |
178 | * Check Board Identity: | |
179 | */ | |
a65cb682 SR |
180 | int checkboard (void) |
181 | { | |
77ddac94 | 182 | char str[64]; |
cdb74977 | 183 | int i = getenv_f("serial#", str, sizeof(str)); |
a65cb682 SR |
184 | |
185 | puts ("Board: "); | |
186 | ||
187 | if (i == -1) { | |
188 | puts ("### No HW ID - assuming HUB405"); | |
189 | } else { | |
190 | puts(str); | |
191 | } | |
192 | ||
cdb74977 | 193 | if (getenv_f("bd_type", str, sizeof(str)) != -1) { |
47b1e3d7 SR |
194 | printf(" (%s", str); |
195 | } else { | |
196 | puts(" (Missing bd_type!"); | |
197 | } | |
198 | ||
199 | gd->board_type = board_revision(); | |
200 | printf(", Rev 1.%ld)\n", gd->board_type); | |
a65cb682 | 201 | |
31193c2c SR |
202 | /* |
203 | * Disable sleep mode in LXT971 | |
204 | */ | |
205 | lxt971_no_sleep(); | |
206 | ||
a65cb682 SR |
207 | return 0; |
208 | } |