[people/ms/u-boot.git] / board / esd / hub405 / hub405.c

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>


extern void lxt971_no_sleep(void);


int board_revision(void)
{
	unsigned long osrl_reg;
	unsigned long isr1l_reg;
	unsigned long tcr_reg;
	unsigned long value;

	/*
	 * Get version of HUB405 board from GPIO's
	 */

	/*
	 * Setup GPIO pin(s) (IRQ6/GPIO23)
	 */
	osrl_reg = in32(GPIO0_OSRH);
	isr1l_reg = in32(GPIO0_ISR1H);
	tcr_reg = in32(GPIO0_TCR);
	out32(GPIO0_OSRH, osrl_reg & ~0x00030000);     /* output select */
	out32(GPIO0_ISR1H, isr1l_reg | 0x00030000);    /* input select  */
	out32(GPIO0_TCR, tcr_reg & ~0x00000100);       /* select input  */

	udelay(1000);            /* wait some time before reading input */
	value = in32(GPIO0_IR) & 0x00000100;         /* get config bits */

	/*
	 * Restore GPIO settings
	 */
	out32(GPIO0_OSRH, osrl_reg);                   /* output select */
	out32(GPIO0_ISR1H, isr1l_reg);                 /* input select  */
	out32(GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */

	if (value & 0x00000100) {
		/* Revision 1.1 or 1.2 detected */
		return 1;
	}

	/* Revision 1.0 */
	return 0;
}


int board_early_init_f (void)
{
	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	 */
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
	mtdcr(uicer, 0x00000000);       /* disable all ints */
	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
	mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */

	/*
	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	 */
	mtebc (epcr, 0xa8400000); /* ebc always driven */

	return 0;
}


int misc_init_f (void)
{
	return 0;  /* dummy implementation */
}


int misc_init_r (void)
{
	DECLARE_GLOBAL_DATA_PTR;

	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
	volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
	volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4);
	volatile unsigned char *led_reg    = (unsigned char *)((ulong)DUART0_BA + 0x20);
	unsigned long val;
	int delay, flashcnt;
	char *str;
	char hw_rev[4];

	/*
	 * Enable interrupts in exar duart mcr[3]
	 */
	*duart0_mcr = 0x08;
	*duart1_mcr = 0x08;
	*duart2_mcr = 0x08;
	*duart3_mcr = 0x08;

	/*
	 * Set RS232/RS422 control (RS232 = high on GPIO)
	 */
	val = in32(GPIO0_OR);
	val &= ~(CFG_UART2_RS232 | CFG_UART3_RS232 | CFG_UART4_RS232 | CFG_UART5_RS232);

	str = getenv("phys0");
	if (!str || (str && (str[0] == '0')))
		val |= CFG_UART2_RS232;

	str = getenv("phys1");
	if (!str || (str && (str[0] == '0')))
		val |= CFG_UART3_RS232;

	str = getenv("phys2");
	if (!str || (str && (str[0] == '0')))
		val |= CFG_UART4_RS232;

	str = getenv("phys3");
	if (!str || (str && (str[0] == '0')))
		val |= CFG_UART5_RS232;

	out32(GPIO0_OR, val);

	/*
	 * Set NAND-FLASH GPIO signals to default
	 */
	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);

	/*
	 * check board type and setup AP power
	 */
	str = getenv("bd_type"); /* this is only set on non prototype hardware */
	if (str != NULL) {
		if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) {
			unsigned char led_reg_default = 0;
			str = getenv("ap_pwr");
			if (!str || (str && (str[0] == '1')))
				led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */

			/*
			 * Flash LEDs
			 */
			for (flashcnt = 0; flashcnt < 3; flashcnt++) {
				*led_reg = led_reg_default;        /* LED_A..D off */
				for (delay = 0; delay < 100; delay++)
					udelay(1000);
				*led_reg = led_reg_default | 0xf0; /* LED_A..D on */
				for (delay = 0; delay < 50; delay++)
					udelay(1000);
			}
			*led_reg = led_reg_default;
		}
	}

	/*
	 * Reset external DUARTs
	 */
	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
	udelay(10); /* wait 10us */
	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
	udelay(1000); /* wait 1ms */

	/*
	 * Store hardware revision in environment for further processing
	 */
	sprintf(hw_rev, "1.%ld", gd->board_type);
	setenv("hw_rev", hw_rev);
	return (0);
}


/*
 * Check Board Identity:
 */
int checkboard (void)
{
	DECLARE_GLOBAL_DATA_PTR;

	char str[64];
	int i = getenv_r ("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming HUB405");
	} else {
		puts(str);
	}

	if (getenv_r("bd_type", str, sizeof(str)) != -1) {
		printf(" (%s", str);
	} else {
		puts(" (Missing bd_type!");
	}

	gd->board_type = board_revision();
	printf(", Rev 1.%ld)\n", gd->board_type);

	/*
	 * Disable sleep mode in LXT971
	 */
	lxt971_no_sleep();

	return 0;
}


long int initdram (int board_type)
{
	unsigned long val;

	mtdcr(memcfga, mem_mb0cf);
	val = mfdcr(memcfgd);

#if 0
	printf("\nmb0cf=%x\n", val); /* test-only */
	printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif

	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}


int testdram (void)
{
	/* TODO: XXX XXX XXX */
	printf ("test: 16 MB - ok\n");

	return (0);
}


#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

void nand_init(void)
{
	nand_probe(CFG_NAND_BASE);
	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
		print_size(nand_dev_desc[0].totlen, "\n");
	}
}
#endif
Commit	Line	Data
a65cb682 SR	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <command.h>
	27	#include <malloc.h>
	28
31193c2c SR	29
31193c2c SR	30	extern void lxt971_no_sleep(void);
a65cb682 SR	31
a65cb682 SR	32
47b1e3d7 SR	33	int board_revision(void)
	34	{
	35	unsigned long osrl_reg;
	36	unsigned long isr1l_reg;
	37	unsigned long tcr_reg;
	38	unsigned long value;
	39
	40	/*
	41	* Get version of HUB405 board from GPIO's
	42	*/
	43
	44	/*
	45	* Setup GPIO pin(s) (IRQ6/GPIO23)
	46	*/
	47	osrl_reg = in32(GPIO0_OSRH);
	48	isr1l_reg = in32(GPIO0_ISR1H);
	49	tcr_reg = in32(GPIO0_TCR);
	50	out32(GPIO0_OSRH, osrl_reg & ~0x00030000); /* output select */
	51	out32(GPIO0_ISR1H, isr1l_reg \| 0x00030000); /* input select */
	52	out32(GPIO0_TCR, tcr_reg & ~0x00000100); /* select input */
	53
	54	udelay(1000); /* wait some time before reading input */
	55	value = in32(GPIO0_IR) & 0x00000100; /* get config bits */
	56
	57	/*
	58	* Restore GPIO settings
	59	*/
	60	out32(GPIO0_OSRH, osrl_reg); /* output select */
	61	out32(GPIO0_ISR1H, isr1l_reg); /* input select */
	62	out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
	63
	64	if (value & 0x00000100) {
	65	/* Revision 1.1 or 1.2 detected */
	66	return 1;
	67	}
	68
	69	/* Revision 1.0 */
	70	return 0;
	71	}
	72
	73
c837dcb1	74	int board_early_init_f (void)
a65cb682 SR	75	{
	76	/*
	77	* IRQ 0-15 405GP internally generated; active high; level sensitive
	78	* IRQ 16 405GP internally generated; active low; level sensitive
	79	* IRQ 17-24 RESERVED
	80	* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	81	* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	82	* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	83	* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	84	* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	85	* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	86	* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	87	*/
	88	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	89	mtdcr(uicer, 0x00000000); /* disable all ints */
	90	mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
	91	mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */
	92	mtdcr(uictr, 0x10000000); /* set int trigger levels */
	93	mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
	94	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	95
	96	/*
	97	* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	98	*/
	99	mtebc (epcr, 0xa8400000); /* ebc always driven */
	100
	101	return 0;
	102	}
	103
	104
a65cb682 SR	105	int misc_init_f (void)
	106	{
	107	return 0; /* dummy implementation */
	108	}
	109
	110
	111	int misc_init_r (void)
	112	{
47b1e3d7 SR	113	DECLARE_GLOBAL_DATA_PTR;
47b1e3d7 SR	114
a65cb682 SR	115	volatile unsigned char duart0_mcr = (unsigned char )((ulong)DUART0_BA + 4);
	116	volatile unsigned char duart1_mcr = (unsigned char )((ulong)DUART1_BA + 4);
	117	volatile unsigned char duart2_mcr = (unsigned char )((ulong)DUART2_BA + 4);
	118	volatile unsigned char duart3_mcr = (unsigned char )((ulong)DUART3_BA + 4);
31193c2c SR	119	volatile unsigned char led_reg = (unsigned char )((ulong)DUART0_BA + 0x20);
	120	unsigned long val;
	121	int delay, flashcnt;
	122	char *str;
47b1e3d7	123	char hw_rev[4];
a65cb682 SR	124
	125	/*
	126	* Enable interrupts in exar duart mcr[3]
	127	*/
	128	*duart0_mcr = 0x08;
	129	*duart1_mcr = 0x08;
	130	*duart2_mcr = 0x08;
	131	*duart3_mcr = 0x08;
	132
efe2a4d5	133	/*
31193c2c SR	134	* Set RS232/RS422 control (RS232 = high on GPIO)
	135	*/
	136	val = in32(GPIO0_OR);
	137	val &= ~(CFG_UART2_RS232 \| CFG_UART3_RS232 \| CFG_UART4_RS232 \| CFG_UART5_RS232);
	138
	139	str = getenv("phys0");
	140	if (!str \|\| (str && (str[0] == '0')))
	141	val \|= CFG_UART2_RS232;
	142
	143	str = getenv("phys1");
	144	if (!str \|\| (str && (str[0] == '0')))
	145	val \|= CFG_UART3_RS232;
	146
	147	str = getenv("phys2");
	148	if (!str \|\| (str && (str[0] == '0')))
	149	val \|= CFG_UART4_RS232;
	150
	151	str = getenv("phys3");
	152	if (!str \|\| (str && (str[0] == '0')))
	153	val \|= CFG_UART5_RS232;
	154
	155	out32(GPIO0_OR, val);
	156
a65cb682 SR	157	/*
	158	* Set NAND-FLASH GPIO signals to default
	159	*/
	160	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE \| CFG_NAND_ALE));
	161	out32(GPIO0_OR, in32(GPIO0_OR) \| CFG_NAND_CE);
	162
31193c2c SR	163	/*
	164	* check board type and setup AP power
	165	*/
	166	str = getenv("bd_type"); /* this is only set on non prototype hardware */
	167	if (str != NULL) {
47b1e3d7	168	if ((strcmp(str, "swch405") == 0) \|\| ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) {
31193c2c SR	169	unsigned char led_reg_default = 0;
	170	str = getenv("ap_pwr");
	171	if (!str \|\| (str && (str[0] == '1')))
	172	led_reg_default = 0x04 \| 0x02 ; /* U2_LED \| AP_PWR */
	173
	174	/*
47b1e3d7	175	* Flash LEDs
31193c2c SR	176	*/
	177	for (flashcnt = 0; flashcnt < 3; flashcnt++) {
	178	led_reg = led_reg_default; / LED_A..D off */
	179	for (delay = 0; delay < 100; delay++)
	180	udelay(1000);
	181	led_reg = led_reg_default \| 0xf0; / LED_A..D on */
	182	for (delay = 0; delay < 50; delay++)
	183	udelay(1000);
	184	}
	185	*led_reg = led_reg_default;
	186	}
	187	}
	188
	189	/*
	190	* Reset external DUARTs
	191	*/
	192	out32(GPIO0_OR, in32(GPIO0_OR) \| CFG_DUART_RST); /* set reset to high */
	193	udelay(10); /* wait 10us */
	194	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
	195	udelay(1000); /* wait 1ms */
	196
47b1e3d7 SR	197	/*
	198	* Store hardware revision in environment for further processing
	199	*/
	200	sprintf(hw_rev, "1.%ld", gd->board_type);
	201	setenv("hw_rev", hw_rev);
a65cb682 SR	202	return (0);
	203	}
	204
	205
	206	/*
	207	* Check Board Identity:
	208	*/
a65cb682 SR	209	int checkboard (void)
a65cb682 SR	210	{
47b1e3d7 SR	211	DECLARE_GLOBAL_DATA_PTR;
47b1e3d7 SR	212
77ddac94	213	char str[64];
a65cb682 SR	214	int i = getenv_r ("serial#", str, sizeof(str));
	215
	216	puts ("Board: ");
	217
	218	if (i == -1) {
	219	puts ("### No HW ID - assuming HUB405");
	220	} else {
	221	puts(str);
	222	}
	223
47b1e3d7 SR	224	if (getenv_r("bd_type", str, sizeof(str)) != -1) {
	225	printf(" (%s", str);
	226	} else {
	227	puts(" (Missing bd_type!");
	228	}
	229
	230	gd->board_type = board_revision();
	231	printf(", Rev 1.%ld)\n", gd->board_type);
a65cb682	232
31193c2c SR	233	/*
	234	* Disable sleep mode in LXT971
	235	*/
	236	lxt971_no_sleep();
	237
a65cb682 SR	238	return 0;
	239	}
	240
a65cb682 SR	241
	242	long int initdram (int board_type)
	243	{
	244	unsigned long val;
	245
	246	mtdcr(memcfga, mem_mb0cf);
	247	val = mfdcr(memcfgd);
	248
	249	#if 0
	250	printf("\nmb0cf=%x\n", val); /* test-only */
	251	printf("strap=%x\n", mfdcr(strap)); /* test-only */
	252	#endif
	253
	254	return (410241024 << ((val & 0x000e0000) >> 17));
	255	}
	256
a65cb682 SR	257
	258	int testdram (void)
	259	{
	260	/* TODO: XXX XXX XXX */
	261	printf ("test: 16 MB - ok\n");
	262
	263	return (0);
	264	}
	265
a65cb682 SR	266
	267	#if (CONFIG_COMMANDS & CFG_CMD_NAND)
	268	#include <linux/mtd/nand.h>
	269	extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
	270
	271	void nand_init(void)
	272	{
	273	nand_probe(CFG_NAND_BASE);
	274	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
	275	print_size(nand_dev_desc[0].totlen, "\n");
	276	}
	277	}
	278	#endif