[people/ms/u-boot.git] / board / esd / meesc / meesc.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * (C) Copyright 2009-2015
 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
 * esd electronic system design gmbh <www.esd.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h>
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_REVISION_TAG
static int hw_rev = -1;	/* hardware revision */

int get_hw_rev(void)
{
	if (hw_rev >= 0)
		return hw_rev;

	hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
	hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;

	if (hw_rev == 15)
		hw_rev = 0;

	return hw_rev;
}
#endif /* CONFIG_REVISION_TAG */

#ifdef CONFIG_CMD_NAND
static void meesc_nand_hw_init(void)
{
	unsigned long csa;
	at91_smc_t	*smc	= (at91_smc_t *) ATMEL_BASE_SMC0;
	at91_matrix_t	*matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;

	/* Enable CS3 */
	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
	writel(csa, &matrix->csa[0]);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
		&smc->cs[3].setup);

	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
		&smc->cs[3].pulse);

	writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
		&smc->cs[3].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
		AT91_SMC_MODE_DBW_8 |
		AT91_SMC_MODE_TDF_CYCLE(12),
		&smc->cs[3].mode);

	/* Configure RDY/BSY */
	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);

	/* Enable NandFlash */
	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif /* CONFIG_CMD_NAND */

#ifdef CONFIG_MACB
static void meesc_macb_hw_init(void)
{
	at91_periph_clk_enable(ATMEL_ID_EMAC);

	at91_macb_hw_init();
}
#endif

/*
 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
 * controller debugging
 * The ET1100 is located at physical address 0x70000000
 * Its process memory is located at physical address 0x70001000
 */
static void meesc_ethercat_hw_init(void)
{
	at91_smc_t	*smc1	= (at91_smc_t *) ATMEL_BASE_SMC1;

	/* Configure SMC EBI1_CS0 for EtherCAT */
	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
		&smc1->cs[0].setup);
	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
		AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
		&smc1->cs[0].pulse);
	writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
		&smc1->cs[0].cycle);
	/*
	 * Configure behavior at external wait signal, byte-select mode, 16 bit
	 * data bus width, none data float wait states and TDF optimization
	 */
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
		AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
		AT91_SMC_MODE_TDF, &smc1->cs[0].mode);

	/* Configure RDY/BSY */
	at91_set_b_periph(AT91_PIO_PORTE, 20, 0);	/* EBI1_NWAIT */
}

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
				PHYS_SDRAM_SIZE);
	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;

	return 0;
}

int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_MACB
	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
#endif
	return rc;
}

#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
	char str[32];
	u_char hw_type;	/* hardware type */

	/* read the "Type" register of the ET1100 controller */
	hw_type = readb(CONFIG_ET1100_BASE);

	switch (hw_type) {
	case 0x11:
	case 0x3F:
		/* ET1100 present, arch number of MEESC-Board */
		gd->bd->bi_arch_number = MACH_TYPE_MEESC;
		puts("Board: CAN-EtherCAT Gateway");
		break;
	case 0xFF:
		/* no ET1100 present, arch number of EtherCAN/2-Board */
		gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
		puts("Board: EtherCAN/2 Gateway");
		/* switch on LED1D */
		at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
		break;
	default:
		/* assume, no ET1100 present, arch number of EtherCAN/2-Board */
		gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
		printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
		puts("Board: EtherCAN/2 Gateway");
		break;
	}
	if (getenv_f("serial#", str, sizeof(str)) > 0) {
		puts(", serial# ");
		puts(str);
	}
#ifdef CONFIG_REVISION_TAG
	printf("\nHardware-revision: 1.%d\n", get_hw_rev());
#endif
	printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
	return 0;
}
#endif /* CONFIG_DISPLAY_BOARDINFO */

#ifdef CONFIG_SERIAL_TAG
void get_board_serial(struct tag_serialnr *serialnr)
{
	char *str;

	char *serial = getenv("serial#");
	if (serial) {
		str = strchr(serial, '_');
		if (str && (strlen(str) >= 4)) {
			serialnr->high = (*(str + 1) << 8) | *(str + 2);
			serialnr->low = simple_strtoul(str + 3, NULL, 16);
		}
	} else {
		serialnr->high = 0;
		serialnr->low = 0;
	}
}
#endif

#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
	return hw_rev | 0x100;
}
#endif

#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
	char		*str;
	char		buf[32];
	at91_pmc_t	*pmc = (at91_pmc_t *) ATMEL_BASE_PMC;

	/*
	 * Normally the processor clock has a divisor of 2.
	 * In some cases this this needs to be set to 4.
	 * Check the user has set environment mdiv to 4 to change the divisor.
	 */
	if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
		writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
			AT91SAM9_PMC_MDIV_4, &pmc->mckr);
		at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
		serial_setbrg();
		/* Notify the user that the clock is not default */
		printf("Setting master clock to %s MHz\n",
			strmhz(buf, get_mck_clk_rate()));
	}

	return 0;
}
#endif /* CONFIG_MISC_INIT_R */

int board_early_init_f(void)
{
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOB);
	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
	at91_periph_clk_enable(ATMEL_ID_UHP);

	at91_seriald_hw_init();

	return 0;
}

int board_init(void)
{
	/* initialize ET1100 Controller */
	meesc_ethercat_hw_init();

	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_CMD_NAND
	meesc_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
	at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_MACB
	meesc_macb_hw_init();
#endif
#ifdef CONFIG_AT91_CAN
	at91_can_hw_init();
#endif
#ifdef CONFIG_USB_OHCI_NEW
	at91_uhp_hw_init();
#endif
	return 0;
}
Commit	Line	Data
33b1d3f4 DG	1	/*
33b1d3f4 DG	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
33b1d3f4 DG	4	* Lead Tech Design <www.leadtechdesign.com>
33b1d3f4 DG	5	*
83bf0057	6	* (C) Copyright 2009-2015
33b1d3f4 DG	7	* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
	8	* esd electronic system design gmbh <www.esd.eu>
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
33b1d3f4 DG	11	*/
	12
	13	#include <common.h>
0cb77bfa	14	#include <asm/io.h>
ac45bb16	15	#include <asm/gpio.h>
33b1d3f4 DG	16	#include <asm/arch/at91sam9_smc.h>
	17	#include <asm/arch/at91_common.h>
	18	#include <asm/arch/at91_pmc.h>
	19	#include <asm/arch/at91_rstc.h>
d4562e09 DG	20	#include <asm/arch/at91_matrix.h>
d4562e09 DG	21	#include <asm/arch/at91_pio.h>
33b1d3f4	22	#include <asm/arch/clk.h>
33b1d3f4 DG	23	#include <netdev.h>
	24
	25	DECLARE_GLOBAL_DATA_PTR;
	26
	27	/*
	28	* Miscelaneous platform dependent initialisations
	29	*/
	30
83bf0057	31	#ifdef CONFIG_REVISION_TAG
33b1d3f4 DG	32	static int hw_rev = -1; /* hardware revision */
	33
	34	int get_hw_rev(void)
	35	{
	36	if (hw_rev >= 0)
	37	return hw_rev;
	38
d4562e09 DG	39	hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
	40	hw_rev \|= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
	41	hw_rev \|= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
	42	hw_rev \|= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
33b1d3f4 DG	43
	44	if (hw_rev == 15)
	45	hw_rev = 0;
	46
	47	return hw_rev;
	48	}
83bf0057	49	#endif /* CONFIG_REVISION_TAG */
33b1d3f4 DG	50
	51	#ifdef CONFIG_CMD_NAND
	52	static void meesc_nand_hw_init(void)
	53	{
	54	unsigned long csa;
0cb77bfa MF	55	at91_smc_t smc = (at91_smc_t ) ATMEL_BASE_SMC0;
0cb77bfa MF	56	at91_matrix_t matrix = (at91_matrix_t ) ATMEL_BASE_MATRIX;
33b1d3f4 DG	57
33b1d3f4 DG	58	/* Enable CS3 */
d4562e09 DG	59	csa = readl(&matrix->csa[0]) \| AT91_MATRIX_CSA_EBI_CS3A;
d4562e09 DG	60	writel(csa, &matrix->csa[0]);
33b1d3f4 DG	61
33b1d3f4 DG	62	/* Configure SMC CS3 for NAND/SmartMedia */
dd80264d DG	63	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(1) \|
dd80264d DG	64	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(2),
d4562e09 DG	65	&smc->cs[3].setup);
	66
	67	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(3) \|
	68	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(3),
	69	&smc->cs[3].pulse);
	70
dd80264d	71	writel(AT91_SMC_CYCLE_NWE(6) \| AT91_SMC_CYCLE_NRD(6),
d4562e09 DG	72	&smc->cs[3].cycle);
	73	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	74	AT91_SMC_MODE_EXNW_DISABLE \|
	75	AT91_SMC_MODE_DBW_8 \|
dd80264d	76	AT91_SMC_MODE_TDF_CYCLE(12),
d4562e09	77	&smc->cs[3].mode);
33b1d3f4 DG	78
33b1d3f4 DG	79	/* Configure RDY/BSY */
ac45bb16	80	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
33b1d3f4 DG	81
33b1d3f4 DG	82	/* Enable NandFlash */
ac45bb16	83	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
33b1d3f4 DG	84	}
	85	#endif /* CONFIG_CMD_NAND */
	86
	87	#ifdef CONFIG_MACB
	88	static void meesc_macb_hw_init(void)
	89	{
70341e2e WY	90	at91_periph_clk_enable(ATMEL_ID_EMAC);
70341e2e WY	91
33b1d3f4 DG	92	at91_macb_hw_init();
	93	}
	94	#endif
	95
	96	/*
	97	* Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
	98	* controller debugging
	99	* The ET1100 is located at physical address 0x70000000
	100	* Its process memory is located at physical address 0x70001000
	101	*/
	102	static void meesc_ethercat_hw_init(void)
	103	{
0cb77bfa	104	at91_smc_t smc1 = (at91_smc_t ) ATMEL_BASE_SMC1;
d4562e09	105
33b1d3f4	106	/* Configure SMC EBI1_CS0 for EtherCAT */
d4562e09 DG	107	writel(AT91_SMC_SETUP_NWE(0) \| AT91_SMC_SETUP_NCS_WR(0) \|
	108	AT91_SMC_SETUP_NRD(0) \| AT91_SMC_SETUP_NCS_RD(0),
	109	&smc1->cs[0].setup);
	110	writel(AT91_SMC_PULSE_NWE(4) \| AT91_SMC_PULSE_NCS_WR(9) \|
	111	AT91_SMC_PULSE_NRD(5) \| AT91_SMC_PULSE_NCS_RD(9),
	112	&smc1->cs[0].pulse);
	113	writel(AT91_SMC_CYCLE_NWE(10) \| AT91_SMC_CYCLE_NRD(6),
	114	&smc1->cs[0].cycle);
a380279b DG	115	/*
	116	* Configure behavior at external wait signal, byte-select mode, 16 bit
	117	* data bus width, none data float wait states and TDF optimization
	118	*/
d4562e09 DG	119	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_EXNW_READY \|
	120	AT91_SMC_MODE_DBW_16 \| AT91_SMC_MODE_TDF_CYCLE(0) \|
	121	AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
33b1d3f4 DG	122
33b1d3f4 DG	123	/* Configure RDY/BSY */
d4562e09	124	at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
33b1d3f4 DG	125	}
	126
	127	int dram_init(void)
	128	{
83bf0057 DG	129	/* dram_init must store complete ramsize in gd->ram_size */
	130	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
	131	PHYS_SDRAM_SIZE);
33b1d3f4 DG	132	return 0;
	133	}
	134
76b00aca	135	int dram_init_banksize(void)
83bf0057 DG	136	{
	137	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	138	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
76b00aca SG	139
76b00aca SG	140	return 0;
83bf0057 DG	141	}
83bf0057 DG	142
33b1d3f4 DG	143	int board_eth_init(bd_t *bis)
	144	{
	145	int rc = 0;
	146	#ifdef CONFIG_MACB
0cb77bfa	147	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
33b1d3f4 DG	148	#endif
	149	return rc;
	150	}
	151
83bf0057	152	#ifdef CONFIG_DISPLAY_BOARDINFO
33b1d3f4 DG	153	int checkboard(void)
	154	{
	155	char str[32];
a380279b DG	156	u_char hw_type; /* hardware type */
	157
	158	/* read the "Type" register of the ET1100 controller */
	159	hw_type = readb(CONFIG_ET1100_BASE);
	160
	161	switch (hw_type) {
	162	case 0x11:
	163	case 0x3F:
	164	/* ET1100 present, arch number of MEESC-Board */
	165	gd->bd->bi_arch_number = MACH_TYPE_MEESC;
	166	puts("Board: CAN-EtherCAT Gateway");
	167	break;
	168	case 0xFF:
	169	/* no ET1100 present, arch number of EtherCAN/2-Board */
	170	gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
	171	puts("Board: EtherCAN/2 Gateway");
	172	/* switch on LED1D */
d4562e09	173	at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
a380279b DG	174	break;
	175	default:
	176	/* assume, no ET1100 present, arch number of EtherCAN/2-Board */
	177	gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
	178	printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
	179	puts("Board: EtherCAN/2 Gateway");
	180	break;
	181	}
cdb74977	182	if (getenv_f("serial#", str, sizeof(str)) > 0) {
33b1d3f4 DG	183	puts(", serial# ");
	184	puts(str);
	185	}
83bf0057	186	#ifdef CONFIG_REVISION_TAG
33b1d3f4	187	printf("\nHardware-revision: 1.%d\n", get_hw_rev());
83bf0057	188	#endif
33b1d3f4 DG	189	printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
	190	return 0;
	191	}
83bf0057	192	#endif /* CONFIG_DISPLAY_BOARDINFO */
33b1d3f4	193
a380279b DG	194	#ifdef CONFIG_SERIAL_TAG
	195	void get_board_serial(struct tag_serialnr *serialnr)
	196	{
	197	char *str;
	198
	199	char *serial = getenv("serial#");
	200	if (serial) {
	201	str = strchr(serial, '_');
	202	if (str && (strlen(str) >= 4)) {
	203	serialnr->high = ((str + 1) << 8) \| (str + 2);
	204	serialnr->low = simple_strtoul(str + 3, NULL, 16);
	205	}
	206	} else {
	207	serialnr->high = 0;
	208	serialnr->low = 0;
	209	}
	210	}
	211	#endif
	212
	213	#ifdef CONFIG_REVISION_TAG
	214	u32 get_board_rev(void)
	215	{
	216	return hw_rev \| 0x100;
	217	}
	218	#endif
	219
a3f3897b DG	220	#ifdef CONFIG_MISC_INIT_R
	221	int misc_init_r(void)
	222	{
d4562e09 DG	223	char *str;
d4562e09 DG	224	char buf[32];
0cb77bfa	225	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
a3f3897b DG	226
	227	/*
	228	* Normally the processor clock has a divisor of 2.
	229	* In some cases this this needs to be set to 4.
	230	* Check the user has set environment mdiv to 4 to change the divisor.
	231	*/
	232	if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
d4562e09 DG	233	writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) \|
	234	AT91SAM9_PMC_MDIV_4, &pmc->mckr);
	235	at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
a3f3897b DG	236	serial_setbrg();
	237	/* Notify the user that the clock is not default */
	238	printf("Setting master clock to %s MHz\n",
	239	strmhz(buf, get_mck_clk_rate()));
	240	}
	241
	242	return 0;
	243	}
	244	#endif /* CONFIG_MISC_INIT_R */
	245
0cb77bfa	246	int board_early_init_f(void)
33b1d3f4	247	{
70341e2e WY	248	at91_periph_clk_enable(ATMEL_ID_PIOA);
	249	at91_periph_clk_enable(ATMEL_ID_PIOB);
	250	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
	251	at91_periph_clk_enable(ATMEL_ID_UHP);
33b1d3f4	252
0cb77bfa MF	253	at91_seriald_hw_init();
	254
	255	return 0;
	256	}
	257
	258	int board_init(void)
	259	{
a380279b DG	260	/* initialize ET1100 Controller */
a380279b DG	261	meesc_ethercat_hw_init();
33b1d3f4 DG	262
33b1d3f4 DG	263	/* adress of boot parameters */
0cb77bfa	264	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
33b1d3f4	265
33b1d3f4 DG	266	#ifdef CONFIG_CMD_NAND
	267	meesc_nand_hw_init();
	268	#endif
33b1d3f4 DG	269	#ifdef CONFIG_HAS_DATAFLASH
	270	at91_spi0_hw_init(1 << 0);
	271	#endif
	272	#ifdef CONFIG_MACB
	273	meesc_macb_hw_init();
	274	#endif
	275	#ifdef CONFIG_AT91_CAN
	276	at91_can_hw_init();
64037fb4 DG	277	#endif
	278	#ifdef CONFIG_USB_OHCI_NEW
	279	at91_uhp_hw_init();
33b1d3f4 DG	280	#endif
	281	return 0;
	282	}