[people/ms/u-boot.git] / board / esd / pf5200 / pf5200.c

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * pf5200.c - main board support/init for the esd pf5200.
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <command.h>
#include <netdev.h>

#include "mt46v16m16-75.h"

void init_power_switch(void);

static void sdram_start(int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *) MPC5XXX_SDRAM_CTRL =
	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *) MPC5XXX_SDRAM_CTRL =
	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register: extended mode */
	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *) MPC5XXX_SDRAM_CTRL =
	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *) MPC5XXX_SDRAM_CTRL =
	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");
}

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
 *            is something else than 0x00000000.
 */

phys_size_t initdram(int board_type)
{
	ulong dramsize = 0;
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

	/* set tap delay */
	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);

	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
		/* let SDRAM CS1 start right after CS0 */
		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
	} else {
#if 0
		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
		/* let SDRAM CS1 start right after CS0 */
		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
#else
		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
		/* let SDRAM CS1 start right after CS0 */
		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
#endif
	}

#if 0
	/* find RAM size using SDRAM CS1 only */
	sdram_start(0);
	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	sdram_start(1);
	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	sdram_start(0);
#endif
	/* set SDRAM CS1 size according to the amount of RAM found */

	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */

	init_power_switch();
	return (dramsize);
}

int checkboard(void)
{
	puts("Board: esd ParaFinder (pf5200)\n");
	return 0;
}

void flash_preinit(void)
{
	/*
	 * Now, when we are in RAM, enable flash write
	 * access for detection process.
	 * Note that CS_BOOT cannot be cleared when
	 * executing in flash.
	 */
	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
}

void flash_afterinit(ulong size)
{
	if (size == 0x02000000) {
		/* adjust mapping */
		*(vu_long *) MPC5XXX_BOOTCS_START =
		    *(vu_long *) MPC5XXX_CS0_START =
		    START_REG(CONFIG_SYS_BOOTCS_START | size);
		*(vu_long *) MPC5XXX_BOOTCS_STOP =
		    *(vu_long *) MPC5XXX_CS0_STOP =
		    STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
	}
}

#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void) {
	pci_mpc5xxx_init(&hose);
}
#endif

#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)

void init_ide_reset(void)
{
	debug("init_ide_reset\n");

	/* Configure PSC1_4 as GPIO output for ATA reset */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
}

void ide_set_reset(int idereset)
{
	debug("ide_reset(%d)\n", idereset);

	if (idereset) {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
	} else {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
	}
}
#endif

#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)

#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)

#define GPIO_WU6	0x40000000UL
#define GPIO_USB0       0x00010000UL
#define GPIO_USB9       0x08000000UL
#define GPIO_USB9S      0x00080000UL

void init_power_switch(void)
{
	debug("init_power_switch\n");

	/* Configure GPIO_WU6 as GPIO output for ATA reset */
	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
	__asm__ volatile ("sync");

	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
	__asm__ volatile ("sync");

	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
	__asm__ volatile ("sync");

	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
		__asm__ volatile ("sync");
	}
	*(vu_char *) CONFIG_SYS_CS1_START = 0x02;	/* Red Power LED on */
	__asm__ volatile ("sync");

	*(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02;	/* Disable driver for KB11 */
	__asm__ volatile ("sync");
}

int board_eth_init(bd_t *bis)
{
	return pci_eth_init(bis);
}

void power_set_reset(int power)
{
	debug("ide_set_reset(%d)\n", power);

	if (power) {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6;
		*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
	} else {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
		if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
		    0) {
			*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |=
			    GPIO_USB0;
		}

	}
}

int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	power_set_reset(1);
	return (0);
}

U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", NULL);

int phypower(int flag)
{
	u32 addr;
	vu_long *reg;
	int status;
	pci_dev_t dev;

	dev = PCI_BDF(0, 0x18, 0);
	status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
	if (status == 0) {
		reg = (vu_long *) (addr + 0x00000040);
		*reg |= 0x40000000;
		__asm__ volatile ("sync");

		reg = (vu_long *) (addr + 0x001000c);
		*reg |= 0x20000000;
		__asm__ volatile ("sync");

		reg = (vu_long *) (addr + 0x0010004);
		if (flag != 0) {
			*reg &= ~0x20000000;
		} else {
			*reg |= 0x20000000;
		}
		__asm__ volatile ("sync");
	}
	return (status);
}

int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	int status;

	if (argv[1][0] == '0') {
		status = phypower(0);
	} else {
		status = phypower(1);
	}
	return (0);
}

U_BOOT_CMD(phypower, 2, 2, do_phypower,
	   "Switch power of ethernet phy", NULL);

int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	unsigned int addr;
	unsigned int size;
	int i;
	volatile unsigned long *ptr;

	addr = simple_strtol(argv[1], NULL, 16);
	size = simple_strtol(argv[2], NULL, 16);

	printf("\nWriting at addr %08x, size %08x.\n", addr, size);

	while (1) {
		ptr = (volatile unsigned long *)addr;
		for (i = 0; i < (size >> 2); i++) {
			*ptr++ = i;
		}

		/* Abort if ctrl-c was pressed */
		if (ctrlc()) {
			puts("\nAbort\n");
			return 0;
		}
		putc('.');
	}
	return 0;
}

U_BOOT_CMD(writepci, 3, 1, do_writepci,
	   "Write some data to pcibus",
	   "<addr> <size>\n" "        - Write some data to pcibus.\n");
Commit	Line	Data
5e4b3361 SR	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	/*
	28	* pf5200.c - main board support/init for the esd pf5200.
	29	*/
	30
	31	#include <common.h>
	32	#include <mpc5xxx.h>
	33	#include <pci.h>
	34	#include <command.h>
19403633	35	#include <netdev.h>
5e4b3361 SR	36
	37	#include "mt46v16m16-75.h"
	38
	39	void init_power_switch(void);
	40
	41	static void sdram_start(int hi_addr)
	42	{
	43	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	44
	45	/* unlock mode register */
	46	(vu_long ) MPC5XXX_SDRAM_CTRL =
	47	SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
	48	__asm__ volatile ("sync");
	49
	50	/* precharge all banks */
	51	(vu_long ) MPC5XXX_SDRAM_CTRL =
	52	SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	53	__asm__ volatile ("sync");
	54
	55	/* set mode register: extended mode */
	56	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	57	__asm__ volatile ("sync");
	58
	59	/* set mode register: reset DLL */
	60	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
	61	__asm__ volatile ("sync");
	62
	63	/* precharge all banks */
	64	(vu_long ) MPC5XXX_SDRAM_CTRL =
	65	SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	66	__asm__ volatile ("sync");
	67
	68	/* auto refresh */
	69	(vu_long ) MPC5XXX_SDRAM_CTRL =
	70	SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
	71	__asm__ volatile ("sync");
	72
	73	/* set mode register */
	74	(vu_long ) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	75	__asm__ volatile ("sync");
	76
	77	/* normal operation */
	78	(vu_long ) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
	79	__asm__ volatile ("sync");
	80	}
	81
	82	/*
	83	* ATTENTION: Although partially referenced initdram does NOT make real use
6d0f6bcf	84	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
5e4b3361 SR	85	* is something else than 0x00000000.
	86	*/
	87
9973e3c6	88	phys_size_t initdram(int board_type)
5e4b3361 SR	89	{
	90	ulong dramsize = 0;
	91	ulong test1, test2;
	92
	93	/* setup SDRAM chip selects */
	94	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
	95	(vu_long ) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
	96	__asm__ volatile ("sync");
	97
	98	/* setup config registers */
	99	(vu_long ) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	100	(vu_long ) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	101	__asm__ volatile ("sync");
	102
	103	/* set tap delay */
	104	(vu_long ) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	105	__asm__ volatile ("sync");
	106
	107	/* find RAM size using SDRAM CS0 only */
	108	sdram_start(0);
6d0f6bcf	109	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
5e4b3361	110	sdram_start(1);
6d0f6bcf	111	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
5e4b3361 SR	112
	113	if (test1 > test2) {
	114	sdram_start(0);
	115	dramsize = test1;
	116	} else {
	117	dramsize = test2;
	118	}
	119
	120	/* memory smaller than 1MB is impossible */
	121	if (dramsize < (1 << 20)) {
	122	dramsize = 0;
	123	}
	124
	125	/* set SDRAM CS0 size according to the amount of RAM found */
	126	if (dramsize > 0) {
	127	(vu_long ) MPC5XXX_SDRAM_CS0CFG =
	128	0x13 + __builtin_ffs(dramsize >> 20) - 1;
	129	/* let SDRAM CS1 start right after CS0 */
	130	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
	131	} else {
	132	#if 0
	133	(vu_long ) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	134	/* let SDRAM CS1 start right after CS0 */
	135	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
	136	#else
	137	(vu_long ) MPC5XXX_SDRAM_CS0CFG =
	138	0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
	139	/* let SDRAM CS1 start right after CS0 */
	140	(vu_long ) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
	141	#endif
	142	}
	143
	144	#if 0
	145	/* find RAM size using SDRAM CS1 only */
	146	sdram_start(0);
6d0f6bcf	147	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
5e4b3361	148	sdram_start(1);
6d0f6bcf	149	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
5e4b3361 SR	150	sdram_start(0);
	151	#endif
	152	/* set SDRAM CS1 size according to the amount of RAM found */
	153
	154	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	155
	156	init_power_switch();
	157	return (dramsize);
	158	}
	159
	160	int checkboard(void)
	161	{
	162	puts("Board: esd ParaFinder (pf5200)\n");
	163	return 0;
	164	}
	165
	166	void flash_preinit(void)
	167	{
	168	/*
	169	* Now, when we are in RAM, enable flash write
	170	* access for detection process.
	171	* Note that CS_BOOT cannot be cleared when
	172	* executing in flash.
	173	*/
	174	(vu_long ) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	175	}
	176
	177	void flash_afterinit(ulong size)
	178	{
	179	if (size == 0x02000000) {
	180	/* adjust mapping */
	181	(vu_long ) MPC5XXX_BOOTCS_START =
	182	(vu_long ) MPC5XXX_CS0_START =
6d0f6bcf	183	START_REG(CONFIG_SYS_BOOTCS_START \| size);
5e4b3361 SR	184	(vu_long ) MPC5XXX_BOOTCS_STOP =
5e4b3361 SR	185	(vu_long ) MPC5XXX_CS0_STOP =
6d0f6bcf	186	STOP_REG(CONFIG_SYS_BOOTCS_START \| size, size);
5e4b3361 SR	187	}
	188	}
	189
	190	#ifdef CONFIG_PCI
	191	static struct pci_controller hose;
	192
	193	extern void pci_mpc5xxx_init(struct pci_controller *);
	194
dd520bf3	195	void pci_init_board(void) {
5e4b3361 SR	196	pci_mpc5xxx_init(&hose);
	197	}
	198	#endif
	199
77a31854	200	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
5e4b3361	201
5e4b3361 SR	202	void init_ide_reset(void)
	203	{
	204	debug("init_ide_reset\n");
	205
	206	/* Configure PSC1_4 as GPIO output for ATA reset */
	207	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
	208	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
	209	}
	210
	211	void ide_set_reset(int idereset)
	212	{
	213	debug("ide_reset(%d)\n", idereset);
	214
	215	if (idereset) {
dae80f3c	216	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
5e4b3361	217	} else {
dae80f3c	218	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
5e4b3361 SR	219	}
5e4b3361 SR	220	}
77a31854	221	#endif
5e4b3361 SR	222
	223	#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
	224	#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
	225	#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
	226	#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
	227
	228	#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
	229	#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
	230	#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
	231	#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
	232
	233	#define GPIO_WU6 0x40000000UL
	234	#define GPIO_USB0 0x00010000UL
	235	#define GPIO_USB9 0x08000000UL
	236	#define GPIO_USB9S 0x00080000UL
	237
	238	void init_power_switch(void)
	239	{
	240	debug("init_power_switch\n");
	241
	242	/* Configure GPIO_WU6 as GPIO output for ATA reset */
dae80f3c	243	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_WU6;
5e4b3361 SR	244	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_WU6;
	245	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_WU6;
	246	__asm__ volatile ("sync");
	247
	248	(vu_long ) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
	249	(vu_long ) MPC5XXX_SIMPLEIO_GPIO_ENABLE \|= GPIO_USB0;
	250	(vu_long ) MPC5XXX_SIMPLEIO_GPIO_DIR \|= GPIO_USB0;
	251	__asm__ volatile ("sync");
	252
	253	(vu_long ) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
	254	(vu_long ) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
	255	__asm__ volatile ("sync");
	256
	257	if (((vu_long ) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
	258	(vu_long ) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT \|= GPIO_USB0;
	259	__asm__ volatile ("sync");
	260	}
6d0f6bcf	261	(vu_char ) CONFIG_SYS_CS1_START = 0x02; /* Red Power LED on */
5e4b3361 SR	262	__asm__ volatile ("sync");
5e4b3361 SR	263
6d0f6bcf	264	(vu_char ) (CONFIG_SYS_CS1_START + 1) = 0x02; /* Disable driver for KB11 */
5e4b3361 SR	265	__asm__ volatile ("sync");
	266	}
	267
19403633 BW	268	int board_eth_init(bd_t *bis)
	269	{
	270	return pci_eth_init(bis);
	271	}
	272
5e4b3361 SR	273	void power_set_reset(int power)
	274	{
	275	debug("ide_set_reset(%d)\n", power);
	276
	277	if (power) {
dae80f3c	278	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6;
5e4b3361 SR	279	(vu_long ) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
5e4b3361 SR	280	} else {
dae80f3c	281	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_WU6;
5e4b3361 SR	282	if (((vu_long ) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
	283	0) {
	284	(vu_long ) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT \|=
	285	GPIO_USB0;
	286	}
	287
	288	}
	289	}
	290
	291	int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	292	{
	293	power_set_reset(1);
	294	return (0);
	295	}
	296
2fb2604d	297	U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", NULL);
5e4b3361 SR	298
	299	int phypower(int flag)
	300	{
	301	u32 addr;
	302	vu_long *reg;
	303	int status;
	304	pci_dev_t dev;
	305
	306	dev = PCI_BDF(0, 0x18, 0);
	307	status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
	308	if (status == 0) {
	309	reg = (vu_long *) (addr + 0x00000040);
	310	*reg \|= 0x40000000;
	311	__asm__ volatile ("sync");
	312
	313	reg = (vu_long *) (addr + 0x001000c);
	314	*reg \|= 0x20000000;
	315	__asm__ volatile ("sync");
	316
	317	reg = (vu_long *) (addr + 0x0010004);
	318	if (flag != 0) {
	319	*reg &= ~0x20000000;
	320	} else {
	321	*reg \|= 0x20000000;
	322	}
	323	__asm__ volatile ("sync");
	324	}
	325	return (status);
	326	}
	327
	328	int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	329	{
	330	int status;
	331
	332	if (argv[1][0] == '0') {
	333	status = phypower(0);
	334	} else {
	335	status = phypower(1);
	336	}
	337	return (0);
	338	}
	339
	340	U_BOOT_CMD(phypower, 2, 2, do_phypower,
2fb2604d	341	"Switch power of ethernet phy", NULL);
5e4b3361 SR	342
	343	int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	344	{
	345	unsigned int addr;
	346	unsigned int size;
	347	int i;
	348	volatile unsigned long *ptr;
	349
	350	addr = simple_strtol(argv[1], NULL, 16);
	351	size = simple_strtol(argv[2], NULL, 16);
	352
	353	printf("\nWriting at addr %08x, size %08x.\n", addr, size);
	354
	355	while (1) {
	356	ptr = (volatile unsigned long *)addr;
	357	for (i = 0; i < (size >> 2); i++) {
	358	*ptr++ = i;
	359	}
	360
	361	/* Abort if ctrl-c was pressed */
	362	if (ctrlc()) {
	363	puts("\nAbort\n");
	364	return 0;
	365	}
	366	putc('.');
	367	}
	368	return 0;
	369	}
	370
	371	U_BOOT_CMD(writepci, 3, 1, do_writepci,
2fb2604d	372	"Write some data to pcibus",
5e4b3361	373	"<addr> <size>\n" " - Write some data to pcibus.\n");