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071d897c SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
2076d0a1 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * (C) Copyright 2005 | |
6 | * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com | |
071d897c SR |
7 | * |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <asm/processor.h> | |
29 | #include <command.h> | |
071d897c SR |
30 | #include <malloc.h> |
31 | ||
d87080b7 | 32 | DECLARE_GLOBAL_DATA_PTR; |
071d897c | 33 | |
4510a7b7 SR |
34 | extern void lxt971_no_sleep(void); |
35 | ||
ef9e8685 SR |
36 | /* fpga configuration data - not compressed, generated by bin2c */ |
37 | const unsigned char fpgadata[] = | |
38 | { | |
39 | #include "fpgadata.c" | |
40 | }; | |
41 | int filesize = sizeof(fpgadata); | |
071d897c SR |
42 | |
43 | ||
c837dcb1 | 44 | int board_early_init_f (void) |
071d897c SR |
45 | { |
46 | /* | |
47 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
48 | * IRQ 16 405GP internally generated; active low; level sensitive | |
49 | * IRQ 17-24 RESERVED | |
50 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive | |
51 | * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive | |
52 | * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive | |
53 | * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive | |
54 | * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive | |
55 | * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive | |
56 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive | |
57 | */ | |
58 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
59 | mtdcr(uicer, 0x00000000); /* disable all ints */ | |
60 | mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ | |
61 | mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ | |
62 | mtdcr(uictr, 0x10000000); /* set int trigger levels */ | |
63 | mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ | |
64 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
65 | ||
66 | /* | |
67 | * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us | |
68 | */ | |
69 | mtebc (epcr, 0xa8400000); | |
70 | ||
4510a7b7 | 71 | /* |
2076d0a1 | 72 | * Setup GPIO pins |
4510a7b7 | 73 | */ |
4510a7b7 | 74 | |
6d0f6bcf JCPV |
75 | mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \ |
76 | CONFIG_SYS_FPGA_DONE | \ | |
77 | CONFIG_SYS_XEREADY | \ | |
78 | CONFIG_SYS_NONMONARCH | \ | |
79 | CONFIG_SYS_REV1_2) << 5)); | |
2076d0a1 | 80 | |
6d0f6bcf | 81 | if (!(in32(GPIO0_IR) & CONFIG_SYS_REV1_2)) { |
2076d0a1 | 82 | /* rev 1.2 boards */ |
6d0f6bcf JCPV |
83 | mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \ |
84 | CONFIG_SYS_SELF_RST) << 5)); | |
2076d0a1 SR |
85 | } |
86 | ||
87 | out32(GPIO0_OR, 0); | |
6d0f6bcf | 88 | out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); /* setup for output */ |
2076d0a1 SR |
89 | |
90 | /* - check if rev1_2 is low, then: | |
6d0f6bcf | 91 | * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST in TCR to assert INTA# or SELFRST# |
4510a7b7 | 92 | */ |
4510a7b7 | 93 | |
071d897c SR |
94 | return 0; |
95 | } | |
96 | ||
97 | ||
98 | /* ------------------------------------------------------------------------- */ | |
99 | ||
071d897c SR |
100 | |
101 | int misc_init_r (void) | |
102 | { | |
4510a7b7 SR |
103 | /* adjust flash start and offset */ |
104 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
105 | gd->bd->bi_flashoffset = 0; | |
106 | ||
6d0f6bcf | 107 | out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY); /* deassert EREADY# */ |
071d897c SR |
108 | return (0); |
109 | } | |
110 | ||
2076d0a1 SR |
111 | ushort pmc405_pci_subsys_deviceid(void) |
112 | { | |
113 | ulong val; | |
114 | val = in32(GPIO0_IR); | |
6d0f6bcf JCPV |
115 | if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ |
116 | if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */ | |
117 | return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH; | |
2076d0a1 | 118 | } |
6d0f6bcf | 119 | return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH; |
2076d0a1 | 120 | } |
6d0f6bcf | 121 | return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH; |
2076d0a1 | 122 | } |
071d897c SR |
123 | |
124 | /* | |
125 | * Check Board Identity: | |
126 | */ | |
071d897c SR |
127 | int checkboard (void) |
128 | { | |
2076d0a1 SR |
129 | ulong val; |
130 | ||
77ddac94 | 131 | char str[64]; |
071d897c SR |
132 | int i = getenv_r ("serial#", str, sizeof(str)); |
133 | ||
134 | puts ("Board: "); | |
135 | ||
136 | if (i == -1) { | |
ef9e8685 | 137 | puts ("### No HW ID - assuming PMC405"); |
071d897c SR |
138 | } else { |
139 | puts(str); | |
140 | } | |
141 | ||
2076d0a1 | 142 | val = in32(GPIO0_IR); |
6d0f6bcf | 143 | if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ |
2076d0a1 | 144 | puts(" rev1.2 ("); |
6d0f6bcf | 145 | if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */ |
2076d0a1 SR |
146 | puts("non-"); |
147 | } | |
148 | puts("monarch)"); | |
149 | } else { | |
150 | puts(" <=rev1.1"); | |
151 | } | |
071d897c | 152 | |
2076d0a1 | 153 | putc ('\n'); |
4510a7b7 | 154 | |
071d897c SR |
155 | return 0; |
156 | } | |
157 | ||
2076d0a1 SR |
158 | /* ------------------------------------------------------------------------- */ |
159 | void reset_phy(void) | |
071d897c | 160 | { |
2076d0a1 | 161 | #ifdef CONFIG_LXT971_NO_SLEEP |
071d897c | 162 | |
2076d0a1 SR |
163 | /* |
164 | * Disable sleep mode in LXT971 | |
165 | */ | |
166 | lxt971_no_sleep(); | |
167 | #endif | |
071d897c SR |
168 | } |
169 | ||
4510a7b7 SR |
170 | |
171 | int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
172 | { | |
173 | ulong addr; | |
174 | volatile uchar *ptr; | |
175 | volatile uchar val; | |
176 | int i; | |
177 | ||
178 | addr = simple_strtol (argv[1], NULL, 16) + 0x16; | |
179 | ||
180 | i = 0; | |
181 | for (;;) { | |
182 | ptr = (uchar *)addr; | |
183 | for (i=0; i<8; i++) { | |
184 | *ptr = i; | |
185 | val = *ptr; | |
186 | ||
187 | if (val != i) { | |
188 | printf("ERROR: addr=%p write=0x%02X, read=0x%02X\n", ptr, i, val); | |
189 | return 0; | |
190 | } | |
191 | ||
192 | /* Abort if ctrl-c was pressed */ | |
193 | if (ctrlc()) { | |
194 | puts("\nAbort\n"); | |
195 | return 0; | |
196 | } | |
197 | ||
198 | ptr++; | |
199 | } | |
200 | } | |
201 | ||
202 | return 0; | |
203 | } | |
204 | U_BOOT_CMD( | |
205 | cantest, 3, 1, do_cantest, | |
206 | "cantest - Test CAN controller", | |
207 | NULL | |
208 | ); |